Thank you, Giacomo!
I'll take a look at the links you provide and try to merge the implemented
GICv3 support into my local repo.
Regards,
Pedro.
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Hi all
I'm trying to boot arm FS with KVM in an ARM machine (an Nvidia Jetson) with
multiple cores.
I had it working last year, on gem5 version 21.1.0.0. Later I had to update
gem5 to version 21.1.0.2 because of some
errors in the stats generation of version 21.1.0.0.
So I had a lot of
Hi all,
I'm extending the ARM ISA with a custom Load macroop.
I saw that some memory instructions (neon especially) refer to "XURa" operand
in .isa
when referring to the register that contains the base address for the load,
while "normal"
loads will refer to the "XBase" operand.
Both are of
Hi all, follow-up question.
In ARMv8, the LDP instruction:
LDP , , [{, #}]
Will load a pair of 128-bit values (256 in total) from memory to two Q
registers (128-bit vector registers).
When I run debug gem5 to see how the said LDP instruction operates (in
AtomicCPU, for now), I see that it is
Hi,
Sorry, that was just a guess. I've not tried myself. Perhaps the NOP
instruction has a different format and is decoded differently, which breaks the
decoding generated code. Maybe you could also try a Unknown64(machInst)
instead. Otherwise, I better leave it for some more experienced
Hi Liyuchao,
I'm assuming you are referring to ARM ISA...
BTI is appearing on your code but it's not implemented.
"A BTI instruction is used to guard against the execution of instructions that
are not the intended target of a branch. Outside of a guarded memory region, a
BTI instruction
Hi Jason,
First of all, thank you for your time and answer. I really appreciate it.
I'll go through the repository that you mentioned, it looks like a promising
source to get inspiration from.
Also, thanks for your support! I think I'm starting to understand the flow of
adding instructions
Hi all,
I want to implement some new instructions on gem5 (ARM) and I've been taking a
look at the .isa files as they seem to be the place where one defines how new
instruction works.
The decoding part is straightforward to understand, until the point it returns
a new instruction (yea, I
Thank you for the detailed answer, Giacomo.
I think case (2) will cover what I want to do. (1) is ok, but since my
instruction will load data from memory, the number of cycles will depend on
where the source data is in the memory hierarchy and I'm not sure I'll be able
to model all involved
Hi Giacomo,
First of all, thanks for your time answering the question.
Your assumption about KVM is correct. I just use it to fast-forward, and I do
not need to execute the instruction I want to implement in KVM mode.
Long story short: the same code for the ROI is executed during the
Just to partially answer my own question 2.
I just realized that M5 ops are pseudo instructions and they work with KVM
("_addr" version), so I guess I could manage to do the same with my own
instructions, if I was to implement them as pseudo-instructions.
I still don't know if there is a way
Hi all,
I came to the point where I'll have to add some new instructions to gem5.
Something like load a number of bytes and process.
I have some "high-level" questions that I'd like to ask for more experienced
users, so that I don't find myself in a dead-end later on.
1 - First,
If the modules you need require installation (e.g., through pip install), you
need to have the modules in the image that you use to simulate. gem5 does not
"forward" or expose the python modules of your host machine to the simulation
environment.
A way to do it is by booting your image with
I just saw you sent a fix to gem5 repo and there is a new minor version that
should solve this problem. I'll try it out. Thanks.
Pedro.
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Hi Meng,
Did you found a solution to this problem? Rollback the code to the previous
version?
I have the same weird behavior on my stats.txt with gem5 version 21.1.0.0.
Best,
Pedro.
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Hi Sindhuja,
Are you using your own python script to configure the simulation?
If I'm not mistaken calling the /sbin/m5 checkpoint exits the m5.simulate()
(from the script), returning the exit_event (a string "checkpoint").
Then, your python script should capture that exit_event and create
Hi all,
First of all, thank you Giacomo for the support, I finally got KVM + arm +
multiple cores working! Kernel 4.14 worked, btw.
Just a list of things I had to do, in case someone else ends up in the same
situation I did.
For the MSR (immediate) undefined instruction, the solution goes
Hi there,
`build/ARM/sim/kernel_workload.cc:43: info: No kernel set for full system
simulation.
Assuming you know what you're doing.`
I think you should also specify a kernel (--kernel) to the fs.py script (and
also a bootloader). You can build them on your own
Hi Giacomo,
Thanks! Now that you mentioned UAO I found this:
https://gem5.atlassian.net/browse/GEM5-685?focusedCommentId=11858 (comment in a
gem5 Jira issue), reporting that disabling UAO when building the kernel worked.
So I'm going to try that and I'll report the steps here if it goes well!
Hi Giacomo,
KVM indeed worked in x86, but my target application would eventually hang with
O3CPU because gem5-X86 does not guarantee the atomicity of synchronization
variables in multithreaded programs with the classic memory system (needed by
KVM).
So I'm once again considering gem5+ARM,
Just an update for the sake of completeness.
I commented out the assertion and rebuilt gem5, just to advance the simulation
to the point where I thought the code was getting stuck.
I'm getting a lot of "queued_spin_lock_slowpath" instructions and the output is
never updated. So it was not a
Hello gem5 community,
I'm afraid my simulation is getting stuck when restoring KVM checkpoints with
DerivO3CPU while running a multithreaded application.
I'm running a full system with x86. Simulation is ok when restoring with
AtomicSimpleCPU (i.e., output prints all expected info).
I tried to
Hello gem5 community,
I'm running an application with FS (fs.py), for which I have generated some
checkpoints.
Now I can restore the checkpoints and run for a given number of ticks. All good.
My application outputs data to a file as the execution goes on. This file is
written in the image,
Modify guest binary so init script points to init.gem5.addr
Then run:
$ export M5_PATH=/scratch/pedro/aarch-system-20210904
$ ./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py --big-cpus 2
--little-cpus 0 --cpu-type kvm --disk /scratch/pedro/ubuntu-18.04-arm64-8gb.img
--kernel
Hi,
Adding the -no-pie flag when linking the target application solves the problem.
Hence, step 2 turns into:
$ gcc m5_exit_addr.o -o m5_exit_addr -L/home/pedro/gem5/util/m5/build/x86/out
-lm5 -no-pie
Best,
Pedro.
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Hi all,
I'm trying to use the address version of m5ops with x86, to use it with
X86KvmCPU. I compiled the x86 libm5.a following the docs:
https://www.gem5.org/documentation/general_docs/m5ops/.
I'm using the m5_exit_addr.c from gem5-resources
Hi again,
Just to report that moving to x86 works: It is possible to create a checkpoint
with KVM and restore from it using --cpu-type AtomicSimpleCPU (or any other
gem5 cpu model) combined with --restore-with-cpu AtomicSimpleCPU, with multiple
cores. So I don't even need to go to these other
Hi all,
I'm still trying to make my kvm dependent setup to work, and any help would be
very much appreciated.
TL;DR; after restoring from arm kvm checkpoints simulation never advances. I'd
also like to accelerate gem5 simulation with arm kvm but generate checkpoints
with atomic, so I could
Update.
I was reading a related discussion in the archive
(https://www.mail-archive.com/gem5-users@gem5.org/msg19217.htm) where the OP
reported they could successfully run kvm up to 8 cores with the
configs/example/arm/fs_bigLITTLE.py script. So I tried running gem5 with his
parameters and
Hi all,
I'm trying to boot Linux (from
https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries) with
multiple cores and KVM. The target ISA is aarch64, so I am running gem5 on an
aarch64 host machine, with KVM support. I'm trying with the latest stable gem5
version
Hi,
If you want to run a binary that is inside the Linux image, then fs.py has a
--script flag, which you can use. It allows you to pass a .rcS script to be
read inside FS simulation through the /sbin/m5_readfile, which you can redirect
to a local file (inside the simulation) and then execute.
Hi all,
Does gem5 have a way to output stats per thread out-of-the-box? Stats.txt is
fine, but as you know it reports stats per CPU.
FIY, I am running a multi-threaded application in arm64 FS mode.
I saw an option in fs.py:
--enable-context-switch-stats-dump
Enable
Hi all,
I'm running gem5 (v20.1.0.4) on an x86 machine, targeting an ARM (aarch64) FS,
and I'd like to speed up my simulation (it takes 3 days to finish with
AtomicSimpleCPU and I'm still running a 'small' workload, likely to increase a
lot).
One option I'd like to try is to fast-forward the
Ok, found a solution.
I more or less merged the existent init.gem5 with the one suggested here
https://www.gem5.org/documentation/general_docs/fullsystem/disks
So the /init.gem5 inside the img file ended up like this:
---
#!/bin/sh
set -ex
mount -t proc - /proc
mount -t sysfs - /sys
mount -t
Thank you, Giacomo and Wenqi for the feedback.
For now, I'll stick with the pre-built images approach because it is simpler
and less error-prone I guess.
However, modifying the gem5.init is leading to a kernel panic
This is the script I'm pointing with the --script option (test.rcS):
#!/bin/sh
Hi all,
I'm trying to use the --script flag to run a script after boot in full-system
mode. However, the script is not executed; the terminal keeps waiting to be
used.
Does anyone knows if the guest binaries
(https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries) are
Hi Giacomo,
Removing the --root flag completely solved question 2). The boot is successful
and I can use the booted Linux (e.g., "uname") through the m5term.
Refreshing to see things working!
Thanks a lot for your help!
Pedro.
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Update: found an answer to question 1) I made before, updating for everyone
here.
I was extracting the tarballs with the graphical interface. But I noticed that
the extensions between the old and new guest binaries were different, (.tar.xz
and .tar.bz2). In fact, that was causing corruption
Hi Giacomo,
Just re-build gem5 from scratch (after `rm -rf` the build folder).
Also, thanks for the info about the --bare-metal. I was posting for
completeness, but won't use it any further.
I've re-downloaded the guest binary. Executing:
$ readelf -e -s $M5_PATH/binaries/vmlinux.arm64
Thanks, Arthur and Giocomon for the feedback.
I tried the suggestions but none of them worked. Let me give you more
information about each of them:
1) fs.py with older image:
same panic error as above.
2) fs.py with --bare-metal and --param 'system.highest_el_is_64 = True' (but no
--param
Hi all,
I've been recently advised to try full-system instead of syscall emulation due
to some errors I was having with the latter.
Since I never ran gem5 + full-system before I want to do the simplest thing
possible: boot and exit. However, I'm getting errors as displayed below.
To
Hi all,
I'm using gem5 to run a multithreaded & multicore application compiled for ARM
(aarch64).
My application under test is also dynamically compiled. I provide the
--interpr-dir and --redirects flags to se.py so it can find the interpreter and
libraries.
I'm able to successfully run a
Hi Jason, thanks for the feedback!
About your suggestions:
- Yes, pthreads worked correctly for the simple examples I tried. But still has
this drawback of shared memory I was trying to avoid..
- Do you have any pointers on implementing syscalls on gem5? It could be
anything I could take as a
Hi all,
Is it possible to do any form of communication between two applications running
in SE mode?
I know we can span two apps with the se.py script with -c "app1;app2", but if
one of these apps try to use syscalls like shmget() or shmat() simulation does
not work because the syscalls are
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