Re: [gem5-users] LSQ bottleneck when using X86 TSO

2014-05-05 Thread Srinivasan Narayanamoorthy via gem5-users
Hi, That can happen.. But why is the behavior you describe not acceptable? if another structure is added, then incoming snoops have to CAM into that structure too and hardware implementation wise, may be not efficient. Thanks Srini On 05/05/14, Adrián Colaso Diego via gem5-users wrote:

Re: [gem5-users] Coherence protocol Deadlock

2014-04-23 Thread Srinivasan Narayanamoorthy
) or by restricting the resource usage (wait-hold relationship), in this case the MSHRs by ³reserving² enough space in advance. Could you elaborate on why this would not be addressing the fundamental problem? Thanks, Andreas On 23/04/2014 01:45, Srinivasan Narayanamoorthy narayanam...@wisc.edu wrote

[gem5-users] Coherence protocol Deadlock

2014-04-22 Thread Srinivasan Narayanamoorthy
Hi, I am using gem5 ARM with classic memory config and l2 tride prefetcher. There are 4 cores in the system and a shared l2. I think I may have hit a coherence protocol deadlock. Here's whats happening. Cycle 0: Core 2: Schedules an UpgradeReq to be sent out at Cycle 2. Between Cycle 0 and

Re: [gem5-users] Coherence protocol Deadlock

2014-04-22 Thread Srinivasan Narayanamoorthy
number of mshrs in the system. I think that will solve your issue and it sounds like a reasonable approach. Ali On 22.04.2014 12:15, Srinivasan Narayanamoorthy wrote: Hi, I am using gem5 ARM with classic memory config and l2 tride prefetcher. There are 4 cores in the system

[gem5-users] ARM WFI implementation

2014-04-16 Thread Srinivasan Narayanamoorthy
Hi all, I am trying to run some android benchmarks in gem5 and often, the cpu is put to sleep by executing a 'WFI'(Wait for interrupt) instruction. The task requires me to take checkpoints frequently during program execution. I found that when performing drain before writing the checkpoint,

Re: [gem5-users] Issues while Draining the CPUs

2014-04-15 Thread Srinivasan Narayanamoorthy
and never comes out. It keeps spinning in the loop with no progress. Any help for debugging further will be great! Thanks -Pushkar On Mon, Apr 14, 2014 at 7:27 PM, Srinivasan Narayanamoorthy narayanam...@wisc.edu(javascript:main.compose() wrote: Hi  1) For the first

Re: [gem5-users] Issues while Draining the CPUs

2014-04-14 Thread Srinivasan Narayanamoorthy
Hi  1) For the first problem, I suspect that the threadcontext is suspended and for some reason it never wakes up. You can look for any quiesce() instructions that is not accompanied by a respective wakeup(). 2) The basic problem here is that a drain is signalled when a pipelined op whose

Re: [gem5-users] DVFS in Quiesce states

2014-03-24 Thread Srinivasan Narayanamoorthy
that is to be DVFS-ed (obviously requiring wakeup). HTH, Stephan On 23.03.2014 14:26, Srinivasan Narayanamoorthy narayanam...@wisc.edu wrote: Hi all, I have implemented a per-core DVFS in gem5, mimicking an on-demand governer. My question here is if the cpu is in quiesce state(TC

[gem5-users] DVFS in Quiesce states

2014-03-23 Thread Srinivasan Narayanamoorthy
Hi all, I have implemented a per-core DVFS in gem5, mimicking an on-demand governer. My question here is if the cpu is in quiesce state(TC is suspended) while DVFS routine is scheduled, should I wakeup() the suspended TC?. Similarly while doing a drain and switching to a different cpu model,

Re: [gem5-users] memReq assertion in O3 CPU when using repeat-switch

2014-03-11 Thread Srinivasan Narayanamoorthy
, it would be good to fix this issue. Judging by your first e-mail it sounds like you more or less coded up a fix already, so I¹d say go ahead and post it on the review board. Andreas On 11/03/2014 02:34, Srinivasan Narayanamoorthy narayanam...@wisc.edu wrote: Hi Andreas,Thanks

[gem5-users] memReq assertion in O3 CPU when using repeat-switch

2014-03-10 Thread Srinivasan Narayanamoorthy
Hi, I am trying to switch between two detailed ARM cpu models using repeat-switch for bbench. I am hitting the assert(!memReq) assertion in drainSanityCheck() after around around 3 seconds (300 switches) of simulation time. I looked at the code but could not think of a situation where drain

Re: [gem5-users] memReq assertion in O3 CPU when using repeat-switch

2014-03-10 Thread Srinivasan Narayanamoorthy
...I am not sure how to handle recvRetry() though in this case.. I am pretty sure that i might be missing something in either of the two solutions. I would be very thankful if a solution can be suggested. Thanks Srini  On 03/10/14, Srinivasan Narayanamoorthy wrote: Hi, I am trying

Re: [gem5-users] memReq assertion in O3 CPU when using repeat-switch

2014-03-10 Thread Srinivasan Narayanamoorthy
that would fix the problem. In essence the bus would then _not_ be considered drained until the packet gets to retry and succeeds. It might be worth trying. How easy is it for you to reproduce the problem? Andreas On 3/10/14, 10:14 PM, Srinivasan Narayanamoorthy narayanam...@wisc.edu wrote

Re: [gem5-users] Freeing functional units

2014-03-03 Thread Srinivasan Narayanamoorthy
21:41 GMT+01:00 Srinivasan Narayanamoorthy narayanam...@wisc.edu(javascript:main.compose(): Hi, I observed the following in the drain code. if (drained !fuPool-isDrained()) { DPRINTF(Drain, FU pool still busy.\n); drained = false; } Consider

[gem5-users] Freeing functional units

2014-02-20 Thread Srinivasan Narayanamoorthy
Hi, I observed the following in the drain code. if (drained !fuPool-isDrained()) { DPRINTF(Drain, FU pool still busy.\n); drained = false; } Consider a pipelined computation with op_latency cycles(1). By default, the functional units are freed in the next cycle and hence Drain

Re: [gem5-users] repeat switch drain and resume

2014-02-06 Thread Srinivasan Narayanamoorthy
page. Also, try running your switching test with the default detailed configuratin as well as your configuration. There might be hidden assumptions in the O3 model that break when you change the configuration. //Andreas On 2014-02-04 01:51, Srinivasan Narayanamoorthy wrote: Hi Andreas

[gem5-users] Per core DFS implementation

2014-02-04 Thread Srinivasan Narayanamoorthy
Hi,This is Srini. I have implemented a system level DFS in gem5 and it seems to be working. Now I am trying to implement per-core DFS in gem5. With the current class hierarchy, clockedObject is the parent of the cpu classes and there is just one _clockPeriod member. Thus all cpu's update the

[gem5-users] repeat switch drain and resume

2014-02-03 Thread Srinivasan Narayanamoorthy
Hi,I am Srini. I am kind of a new user to gem5 and for some of my experiments, I need to repeatedly switch between two cpu models. I figured configuring repeat-switch option is an easy way of doing it but was soon hitting some drain related assertions. Turns out that when the drain manager is

Re: [gem5-users] repeat switch drain and resume

2014-02-03 Thread Srinivasan Narayanamoorthy
from last Sunday or newer, otherwise rflags synchronization on x86 won't work because of a regression introduced a couple of months ago. //Andreas On 2014-02-03 22:13, Srinivasan Narayanamoorthy wrote: Hi,I am Srini. I am kind of a new user to gem5 and for some of my experiments, I need