, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
};
The implementation of the individual microops ld, sub and others can be
found in:
src/arch/x86/isa/microops/*.isa
Cheers,
Swapnil Haria,
PhD Candidate,
Dept of Computer Sciences,
University of Wisconsin-Madison
http://pages.cs.wisc.edu/~swapnilh
" lfence \n"
" movl %%eax, %%esi \n"
" movl (%1), %%eax \n"
" lfence \n"
" rdtsc \n"
" subl %%esi, %%eax \n"
: "=a" (time)
: "c" (addr)
: "%esi&qu
the memory controller
queues. So I think the load after a CLFLUSH would simply read the value
from the memory controller queue itself. So the load latency might be
similar to cache latency and not memory latency.
I will look into this further.
Cheers,
Swapnil Haria,
PhD Candidate,
Dept of Computer
Your script seems to execute fft for only one processor. The -p command
line parameter for FFT corresponds to number of available processors. This
would probably fix it:
./FFT -t -p4
Cheers,
Swapnil Haria,
PhD Candidate,
Dept of Computer Sciences,
University of Wisconsin-Madison
On Thu, Apr
Hey Maximilian,
I have recently submitted a patch for this. You can find it here:
https://gem5-review.googlesource.com/c/public/gem5/+/7401
This patch allows CLFLUSH, CLFLUSHOPT and CLWB to be used with the classic
caches.
Cheers,
Swapnil Haria,
PhD Candidate,
Dept of Computer Sciences
*pt =
dynamic_cast<MultiLevelPageTable *>(pTable);
pt->map(, , , );
Check out src/mem/pagetable.hh for the map function, and
src/arch/x86/process.cc and src/sim/process.cc for more information about
this.
Cheers,
Swapnil Haria,
Graduate Student,
Dept of Computer Sciences,
U
rce.
Cheers,
Swapnil Haria,
Graduate Student,
Dept of Computer Sciences,
University of Wisconsin-Madison
On Mon, Nov 21, 2016 at 12:30 AM, Azin Heidarshenas <
azin.heidarshe...@gmail.com> wrote:
> Hi,
> Is it possible to have uncacheable memory address space in Ruby?
>
>
insts) to see if you are switching and stopping
correctly.
You are correct, after the switch, timing mode is enabled.
Cheers,
Swapnil Haria,
Graduate Student,
Dept of Computer Sciences,
University of Wisconsin-Madison
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gem5-u
insts) to see if you are switching and stopping
correctly.
You are correct, after the switch, timing mode is enabled.
Cheers,
Swapnil Haria,
Graduate Student,
Dept of Computer Sciences,
University of Wisconsin-Madison
On Fri, Oct 28, 2016 at 9:15 AM, Swapnil Haria <swapnils...@gmail.com>
w
/Simulation.py). You will need to do
something similar in your own config file.
Cheers,
Swapnil Haria,
Graduate Student,
Dept of Computer Sciences,
University of Wisconsin-Madison
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with the
latest version of gem5.
Have you made any local changes? Having a few more details of your
simulation would also help us understand this.
Cheers,
Swapnil Haria,
Graduate Student,
Dept of Computer Sciences,
University of Wisconsin-Madison
___
gem5
/General_Memory_System, but keep in mind that it is
outdated.
Also, to help you explore the gem5 caches, you could try part V of this
tutorial - http://gem5.org/Gem5_101
Cheers,
Swapnil Haria,
Graduate Student,
Dept of Computer Sciences,
University of Wisconsin-Madison
II) could also help you get started -
http://www.lowepower.com/jason/learning_gem5/
Cheers,
Swapnil Haria
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