[gem5-users] Hello everyone, how to count the distribution of requests sent by core to cache in each cycle

2021-11-10 Thread zhen bang via gem5-users
Hello everyone, how to count the distribution of requests sent by the core to cache in each cycle? Is it to count the requests entering the port in the MandatoryQueue? How should this be implemented in gem5? ___ gem5-users mailing list --

[gem5-users] Re: write if-else statement in slicc transition code blocks.

2021-02-01 Thread zhen bang via gem5-users
Hello Jason, Thank you for your reply, thank you very much. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] write if-else statement in slicc transition code blocks.

2021-01-31 Thread zhen bang via gem5-users
Hello everyone: Recently, I am making some changes to the cache coherence protocol in Gem5, in the SLICC documents, I should add some if-else statements, but the transitions code blocks seem do not to cover this case, it shows syntax error >>if<<. If I do so, should I change the related parts

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2021-01-26 Thread zhen bang via gem5-users
Hello Jason: Thank you for your reply, thank you very much. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2021-01-23 Thread zhen bang via gem5-users
Hello Jason: I have tag every transition in the cache controller (i.e., MESI_Three_Level-L0cache.sm) with the required resources, but there is something wrong, during the implementation of the L0 multi-bank, I have doubt whether need to add L1 RequestType? It also means require L1 cache

[gem5-users] In Ruby, I have changed my MESI_Three_Level-L0cache.sm, but panic: Runtime error, assert failure

2021-01-23 Thread zhen bang via gem5-users
Hello everyone: I have changed my MESI_Three_Level-L0cache.sm, but panic: Runtime error, assert failure. void setState(TBE tbe, Entry cache_entry, Address addr, State state） assert((Dcache.isTagPresent(addr) && Icache.isTagPresent(addr)) == false); if(is_valid(tbe)) { return

[gem5-users] In Ruby, I have changed my MESI_Three_Level-L0cache.sm, but panic: Runtime error, assert failure

2021-01-23 Thread zhen bang via gem5-users
Hello everyone: I have changed my MESI_Three_Level-L0cache.sm, but panic: Runtime error, assert failure ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Re: A question regarding to VIPT/PIPT

2020-11-18 Thread zhen bang via gem5-users
Hi Ayaz, (1) I want to model VIPT cache in gem5 under Ruby system, but Ruby does not seem to call the method in the classic system, that is, the script in the src/mem/cache . Which files should I modify to model VIPT in Ruby? (2) According to my understanding of VIPT and PIPT, the latency

[gem5-users] Tag lookup latency and Data access latency in Ruby

2020-11-18 Thread zhen bang via gem5-users
Hello everyone: I have two questions about the cache access parameters of Ruby: (1) In classic system, tag_latency = Param.Cycles("Tag lookup latency") and data_latency = Param.Cycles("Data access latency") In Ruby system, what is the corresponding tag_latency and data_latency ? I only find

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-11-08 Thread zhen bang via gem5-users
Hello Jason: Comparing resource stalls to model banking with "real banking", (1) I think the biggest difference is that the former does not implement a port for each bank, is it right? (2) I have read MOESI_AMD_Base-corepaire.sm that you have mentioned, during the implementing L0 multi-bank, I

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-29 Thread zhen bang via gem5-users
Hello Jason: (1) Can I use resource stalls to simulate the multi-bank implementation of L0 and L1, and model L2 a distributed cache? By the way, the implementation of L2 multi-bank in gem5 is not interleaving (multi-bank), right? (2) "add annotations to the transitions in the L0 and L1 cache",

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

2020-10-28 Thread zhen bang via gem5-users
Hello Jason: I would use the resource stalls to model banking, I have read src/mem/ruby/structures/Rubycache.py and src/mem/ruby/structures/BankedArray.cc (1) I have seen dataArrayBanks = Param.Int(1, "Number of banks for the data array") tagArrayBanks = Param.Int(1, "Number of banks for the