Thanks, Sharjeel. I will try to run ARM NoC with your configuration.
FYI, I've modified .dts file, and then generated .dtb file that supports
larger memory capacity. I did not fully test it, but it looks like working.
Thanks again.
Regards,
Dong Wan Kim
On Tue, Dec 12, 2017 at 2:38 AM, SHARJE
Hi David,
I am sorry for late response. Here is the configuration I used to simulate
my NoC
./build/ARM/gem5.fast configs/example/fs.py --l1d_size=32kB --l1i_size=32kB
--num-l2caches 4 --l2_size=1MB --cacheline_size=64
--machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/
Thanks Sharjeel,
So, does each core have its own 1GB memory in your configuration?
Would you please briefly explain your system configuration?
On Fri, Dec 1, 2017 at 1:34 PM, SHARJEEL KHILJI <
sharjeelsaeedkhi...@gmail.com> wrote:
> Hi,
>
> I have simulated ARM NoC (4 and 8 cores) with 4 and 8
Hi,
I have simulated ARM NoC (4 and 8 cores) with 4 and 8GB with
VEXPRESS_GEM5_V1 platform. You can try with this platform.
regards,
Sharjeel
On 1 December 2017 at 23:55, David Kim wrote:
> Hello,
>
> I am going to simulate a system with large memory capacity.
>
> As far as I know, the curr
Hello,
I am going to simulate a system with large memory capacity.
As far as I know, the current gem5 ARM platform can support up to 2GB
memory (VExpress_EMM machine).
I thought this limitation is a bit related to VExpress target board
configuration. So I am trying to manipulate dtb file to incre
