[gem5-users] Re: gem5 stats , LLC average miss latency

Hi Arun, That time is in simulator *ticks*, not cycles. By default, the tick time is 1ps, so that would be an average latency of 3.8us, which is high, but seems possible for non-volatile memory. Cheers, Jason On Sun, Nov 15, 2020 at 11:43 PM Arun Kavumkal via gem5-users < gem5-users@gem5.org> wr

[gem5-users] Re: Multi-process shared memory in SE mode

Hi Pedro, No, I don't have any specific pointers beyond the code in src/sim/. One quick note: on develop there is something in flux about how syscalls work. There's been some recent changes from Gabe to the "Workload" and the syscall dispatch. I have to admit I don't understand them, but it might

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

Hello, (1) Yes, I believe so. (2) I thought MOESI_hammer was annotated, but it doesn't look like (huh...). However, AMD MOESI Base is annotated. See all of the transition in the core-pair file, for instance: https://gem5.googlesource.com/public/gem5/+/refs/tags/v20.1.0.0/src/mem/ruby/protocol/MOES

[gem5-users] Re: What is the role of TimeBuffer in gem5?

Hello, I've been using gem5 for ~10 years, and this is the first time I've ever seen this code :D. It was committed 14 years ago, and it hasn't been touched since. It looks to me like it's used for gathering statistics about the activity of different CPU pipeline stages. However, I *know* it's n

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

Hello, For (1), yes. You can set this *in the python configuration file*. You should not modify the SimObject description file to change a default parameter. For (2), yes, that's exactly where you should modify. Cheers, Jason On Wed, Oct 28, 2020 at 9:47 AM zhen bang via gem5-users < gem5-users

[gem5-users] Re: Multi-level TLB is implemented in performance

Yes, this is possible, and I believe it's already implemented for Arm. The best place to start is src/arch//tlb.cc Cheers, Jason On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users < gem5-users@gem5.org> wrote: > Hi,all. I would like to know if it is possible to implement multi-level > T

[gem5-users] Re: Multi-process shared memory in SE mode

Hi Predro, It would certainly be easier in FS mode :D. Also, I would worry that the system call emulation layer might not model your application with high enough fidelity if you care about multithreaded apps (e.g., the futex system call will take 0 time in SE mode). If you dynamically link your a

[gem5-users] Re: How to run Python code with TensorFlow in Gem5 syscall emulation mode?

Hi Hasan, I agree with Abhishek. Something as complex as tensorflow is going to be very difficult to get working in syscall emulation mode. Using full system mode should work (though without things like GPU acceleration, of course). Cheers, Jason On Fri, Oct 23, 2020 at 1:55 PM Abhishek Singh vi

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

In this case, I would use the resource stalls to model banking. You can extend the BankedCache implementation to model arbitrary address interleaving, if that's important to your model. To do this, you'll have to add annotations to the transitions in the L0 and L1 cache, but this should be easier t

[gem5-users] Re: Add FLUSH in MESI prtocol

Honestly, I'm not sure. I would need to dig much deeper into the MESI_Three_Level protocol to be able to help. Jason On Tue, Oct 20, 2020 at 9:06 PM 1154063264--- via gem5-users < gem5-users@gem5.org> wrote: > In MOESI_hammer, the state transition in the I state is defined as follows, > > transi

[gem5-users] Re: Add FLUSH in MESI prtocol

I would look to see how it's done in MOESI_hammer. https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/mem/ruby/protocol/MOESI_hammer-cache.sm#902 Cheers, Jason On Tue, Oct 20, 2020 at 9:04 AM 1154063264--- via gem5-users < gem5-users@gem5.org> wrote: > Hello Jason: > It is really

[gem5-users] Re: Add FLUSH in MESI prtocol

Hello, The lack of error when writing a checkpoint doesn't mean it was successful. Likely, the data was not written back to memory correctly if the random test is failing. No, you cannot use `writeCallbackScFail`. This is to signal that a store conditional has failed. It might help to learn abou

[gem5-users] Re: Any one bootup with fs.py in gem5 version 20.1 with dramsim3 or nvmain succuessfully

Hello, DRAMSim isn't a drop in replacement for the memory object anymore. Since the change in the memory interface ( http://www.gem5.org/project/2020/10/01/gem5-20-1.html#new-dram-interface-contributed-by-wendy-elsasser) you can't just drop in a different type of DRAM model. You'll probably have

[gem5-users] Re: Configure multi-bank cache in ruby ​mode with MESI coherence protocol

Hello, It depends on how you want to model banking. If you just want to set and limit the bandwidth to a cache, you can use the "resourceStalls = true" option on the RubyCache object and set the tag and data array values. You will also have to tag every transition in the cache controller (i.e., ME

[gem5-users] Re: Add FLUSH in MESI prtocol

Hello, It's difficult for me to say for certain without digging much deeper. However, my gut says the latter is probably closer to correct. I doubt that you can drop the line without first receiving an ack (somehow). I'm not sure if this was said before, but you can use the Ruby random tester in

[gem5-users] Re: X86KvmCPU fails -- reason code 0x80000021

af04439240c532d3530a02773b75b9853f77 >>>>> >>>>> I get the following error when I try to run a full-system >>>>> (configs/example/fs.py) with the X86KvmCPU: >>>>> >>>>> panic: KVM: Failed to enter virtualized mode (hw reason: 0x8021)

[gem5-users] Re: Add FLUSH in MESI prtocol

Hello, If the block is already in I, then there shouldn't be anything to flush/write back. You should be able to simply do something like transition(I, Flush_line) { flushRespsonse; } action(flushResponse) { sequencer.flushResponse(); (or whatever this function is on the sequencer) } Cheers, Ja

[gem5-users] Re: Invalid RubyRequestType

Hi Teo, That error is because you're still using MESI_Two_Level. You need to recompile gem5 to use a different protocol. I.e., to use MESI_Two_Level you could do the following: > scons build/X86_MESI_Two_Level/gem5.opt > build/X86_MESI_Two_Level/gem5.opt To use MOESI_hammer you could do the fo

[gem5-users] Re: Add FLUSH in MESI prtocol

Hello, It's hard for me to know what's wrong. Debugging protocols is hard! It looks like you're moving in the right direction, though. Other than giving you encouragement, I'm not sure I can help much. Cheers, Jason On Thu, Oct 8, 2020 at 7:58 PM 1154063264--- via gem5-users < gem5-users@gem5.or

[gem5-users] Re: CPU configuration and default values

Hi Davide, I echo 100% of what Giacomo said. Also, there's a proposal for updating the Python API here: https://gem5.atlassian.net/browse/GEM5-432. That proposal is a pretty extreme example, and we'll probably end up with something closer to the status quo. You can also check out Learning gem5 to

[gem5-users] Re: some questions while using kvm

check out the latest release. BTW, > could you let me know how to use he MMIO/address version of the m5ops? > I make the m5term in util/term. > > -- > Best regards, > > Yifan Song > > -原始邮件- > *发件人:*"Jason Lowe-Power" > *发送时间:*2020-10-08 04:55:

[gem5-users] Re: some questions while using kvm

Hi Yifan, First of all, the branch that you referred to is pretty old. I would use gem5-20.1. You can check out the gem5-resources for information on how to get KVM+x86 working with SPEC, Parsec, and other benchmarks. http://www.gem5.org/documentation/general_docs/gem5_resources/ Switching CPUs

[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

ol You wrote: > Thanks Jason, > > I just thought that FLUSH request can be handled with invalidate and > write-back. Could you let me know what other things should be considered > for FLUSH? Or is it fine modifying the CPU sequencer that it just ignore > the FLUSH request? >

[gem5-users] Re: Regarding ruby prefetcher requestIssued and requestCompleted bitset

Hi Kavya, This looks like a bug! The RubyPrefetcher has never been regularly tested, as far as I know. I would guess the place where these were updated got deleted at some point and no one noticed. I'd try checking out a gem5 from 5 years ago and see if it's there. We would welcome a contribution

[gem5-users] Re: Adjusting gem5 CPU simulation granularity in heterogeneous memory environments?

Hi Balazs, What you suggest sounds like a panacea! I'm not sure it's possible, though :(. There are multiple different levels of fidelity between the O3 CPU and the Timing Simple CPU. You could imagine other CPU models with more or less fidelity as well, but currently these are the two main model

[gem5-users] Re: FLUSH request from CPU sequencer to cache controller

Hi Daecheol, Unfortunately, the flush command is a bit more complicated to implement than just a simple replacement. I responded to another message about this on the mailing list a few minutes ago that you can see for more information. Cheers, Jason On Mon, Sep 28, 2020 at 8:59 PM Daecheol You v

[gem5-users] Re: How to initialize the the Stats:Scalar value and convert it to unsigned value

Hi Shougang, I think you can use .value() to get the actual value out of the stat. That should be easy to cast to an unsigned, if needed. However, I think there might be some confusion on how to register/use the stats. If you've registered it correctly and it is updated during simulation (e.g., s

[gem5-users] Re: Add FLUSH in MESI prtocol

Hello, Yeah, adding flush to a protocol is a pretty large task, but it shouldn't be too difficult. The key difficulty will be testing it, but the Ruby tester does support testing flushes (probably not out of the box with ruby_random_test.py, though). There's no particular reason except that we ha

[gem5-users] A quick note for the gem5 community

Hi everyone, We are sending this email to be as transparent as possible. The gem5 community is respectful and inclusive of all people, and we enforce these standards in all community spaces. We as members, contributors, and leaders pledge to make participation in our community a harassment-free ex

[gem5-users] Re: Segmentation fault in gem5,

political opinions. Let's work > together to keep it away from it. > > Hope you all have a good weekend. > > Thanks, > > [image: Screen Shot 2020-10-02 at 5.41.55 PM.png] > > > -Tao > > > On Fri, Oct 2, 2020 at 10:26 AM Jason Lowe-Power via gem5-users <

[gem5-users] Re: Segmentation fault in gem5,

Hi everyone, A few things: 1. Being polite is important! We strive to make the gem5 community inclusive and welcoming. :) 2. Email can be very impersonal. Adding a greeting and a signature with your name helps create a more welcoming environment! 3. When asking questions on the mailing list, help

[gem5-users] Re: Question about MESI_Three_Level protocol

Hi Daecheol, You're correct that MESI_Three_Level, like MESI_Two_Level has a shared (banked) LLC. The L2 cache is chosen based on the function "mapAddressToRange" (see https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm#403 ). The mapAd

[gem5-users] Re: Tracking read()/write() system calls in gem5

See the `readFunc` and `writeFunc` implementations in sycall_emul.hh: https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/syscall_emul.hh#2454 On Tue, Sep 22, 2020 at 12:25 PM ABD ALRHMAN ABO ALKHEEL via gem5-users < gem5-users@gem5.org> wrote: > Hi All, can I track the read()/w

[gem5-users] Re: Indirect target predictor

Hi Shyam, I don't think so! However, we'd be happy to accept the contribution of new indirect predictors! Cheers, Jason On Fri, Sep 18, 2020 at 4:07 PM Shyam Murthy via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > Is there any other target predictor for indirect jumps on gem5 apart fr

[gem5-users] Re: trigger is not recongnized for MSI protocol withRuby in gem5

Hi Shaikhul, "trigger" isn't really a function. It's a language statement (like, `if` in C/C++). SLICC doesn't always give the most helpful errors. However, I notice that the eros is actually showing line 124, not line 219. That seems suspicious to me, and I'd look more into that. Also, you can

[gem5-users] Re: Why using guest code with pseudo-instructions has less number of simulated ticks

Hi Aamir, Slight changes (e.g., less that 1%) wouldn't be too surprising as SE mode isn't always deterministic. Additionally, you're changing the number of instructions and the layout of the binary when you add instructions. So, again, slight changes wouldn't be surprising. If the changes in simu

[gem5-users] Re: Queries regarding banking and response bypass in gem5 classic cache

Hi Aritra, See answers inline below. Cheers, Jason On Tue, Sep 15, 2020 at 3:12 AM Aritra Bagchi via gem5-users < gem5-users@gem5.org> wrote: > Hi all, > > I have two questions regarding the classic cache of gem5. They are as > follows: > > 1. Last-level caches in real hardware are usually not

[gem5-users] Re: Are there any ideas to accelerate the speed of m5.checkpoint on disks?

above. > Any use of the > information contained herein in any way (including, but not limited to, > total or partial > disclosure, reproduction, or dissemination) by persons other than the > intended > recipient(s) is prohibited. If you receive this e-mail in error, please > notify

[gem5-users] Re: Are there any ideas to accelerate the speed of m5.checkpoint on disks?

This isn't a problem we've seen before, but it's not particularly surprising. I believe we make many small writes to disk (i.e., each object is a separate write). I'm not sure how to fix this, but it might be a place to start. Another place to look is that most of the data written is the contents

[gem5-users] Re: Approximating the value of L1 misses

Hi Farhad, The short answer is "no". You're modifying the cache behavior, which is going to have implications on the coherence protocol. This is both the good thing and the bad thing about using Ruby... it forces you to think through many of the actual implementation details. Cheers, Jason On Th

[gem5-users] Re: Garnet - Query regarding Faux-Filesystem

Hi Sampad, Srikant can probably answer this better, but you're probably correct. If that fixes the problem for you, we would appreciate it if you could push the change to gerrit for review! See https://gem5.googlesource.com/public/gem5/+/refs/heads/master/CONTRIBUTING.md for details. Cheers, Jas

[gem5-users] Re: BTB hits reported as 0 and direct/indirect branch instruction classification missing

Is this on the stable branch (master, gem5-20.0) or develop? I believe there are some related issues: https://gem5.atlassian.net/browse/GEM5-338 https://gem5.atlassian.net/browse/GEM5-732 https://gem5.atlassian.net/browse/GEM5-720 Some of those have been resolved and will be part of the 20.1 rele

[gem5-users] Re: Modelling port contentions in gem5

Hello, Generally, it's difficult to queue up writeback requests at the cache controller and maintain coherence. The different cache models in gem5 implement this in different ways. In the classic caches, the MSHR queues handle the queuing for writebacks. When a line is evicted a writeback request

[gem5-users] Re: Privileged Instruction in Full System Mode

o implement those checks to get > correct (or correct enough) behavior, and secondarily it avoids a small > amount of overhead from having to do the checks. Having the checks probably > wouldn't be a bad thing, but it's just not been a priority. > > Gabe > > On Thu

[gem5-users] Re: Privileged Instruction in Full System Mode

Hi David, That is very strange. I would also expect gem5 to produce a protection fault on that code. I would try a couple of things: 1. Try running interactively in gem5 (e.g., with m5term) and seeing what happens 2. Try using gdb interactive *in gem5*. In other words, run gdb inside the simulator

[gem5-users] Re: version `GLIBC_2.17' not found when running c program in gem5 in FS mode

Hi Jaspinder, The problem is likely that your disk image is using a different OS (or version of the OS) than your host where you compiled the benchmark. I suggest using an up to date OS on your disk image (e.g., Ubuntu 20.04). You can see examples here: http://www.gem5.org/documentation/general_do

[gem5-users] Re: Making gem5 Simulation Multithreaded

In short, no. It turns out that parallelizing something like gem5 is *very* difficult. There are few specific cases where it can be done, but it's not something that we've been able to get working generally. Usually, to take advantage of large scale systems, we run many simulations in parallel.

[gem5-users] Re: Gem5 and Python3 status

Hi Dimitrios, Yes. As of gem5-20.0 we fully support python3. I believe the error you're seeing is unrelated :). I believe all you need to do to build with python3 is to use the option `PYTHON_CONFIG=python3-config` when building with scons. If python3 is the only python binary on your system, you

[gem5-users] Re: SLICC: Main memory overwhelmed by requests?

Hi Theo, It's possible that if you increase the deadlock timeout your protocol will "just work". There's an infinite queue between the memory controller (DRAMCtrl) and the Ruby directory (which sends the memory requests to the memory controller). We've made some progress to correctly model backpre

[gem5-users] Re: Functional read failed while using pthread lock in program

Hello, m5threads is not supported in gem5. I would suggest using full system simulation if you are investigating multithreaded workloads. Cheers, Jason On Wed, Aug 19, 2020 at 11:42 PM VIPIN PATEL via gem5-users < gem5-users@gem5.org> wrote: > Hi All, > > After following the discussion on the J

[gem5-users] Re: Sending more than one memory request to the memory through sendTimingReq

Hello, This depends on your memory system. If your cache can accept more than one request per cycle, then the CPU can send more than one request. The `sendTimingReq` returns false when the receiver cannot receive another request. It's hard to know exactly what your memory system looks like, but i

[gem5-users] Re: Reading from memory in Gem5

esses. For instance, let us assume that the address that load > instruction loads data from it is (0x78226e68), can I read the content > of this memory address? Also can I read the 256 bytes of this address ( > 0x78226e00-0x78226eff)? If so, how? > > Thanks > > &

[gem5-users] Re: Getting tick number from C code

You can also use curTick() from python. For instance: m5.simulate() m5.checkpoint() print(f'The current tick value is {m5.curTick()}') Cheers, Jason On Thu, Aug 6, 2020 at 10:17 AM Daniel Gerzhoy via gem5-users < gem5-users@gem5.org> wrote: > There is the m5_rpns() pseudo instruction that retur

[gem5-users] Re: gem5 aborted when increase mem-size in FS mode

Hi Yifan, Is it possible that your system is running out of memory? It's possible this is a gem5 bug (what version are you using?), but I haven't heard of this issue before. Cheers, Jason On Wed, Aug 5, 2020 at 1:34 AM syf1997--- via gem5-users < gem5-users@gem5.org> wrote: > Hi all, > > I am t

[gem5-users] Re: Reading from memory in Gem5

s. After a specific time, I want to access the memory to read > the data from those addresses. Can I use getSystemPort function to access > the memory and read the data from those addresses? If so, should I use the > virtual address or the physical address? > > Thanks > > > -

[gem5-users] Re: Reading from memory in Gem5

Hello, This sounds like you probably want to use "functional" accesses. These are built for introspection and debugging, which is what it sounds like you want to do. Using the System object, there is a `getSystemPort` function that will return a gem5 port that you can use with functional accesses

[gem5-users] Re: Error creating a SimObject

Hi Saideepak, This looks like the Param type for the parameter is wrong. I suggest looking at this documentation to get an idea of how to pass SimObjects as parameters: http://www.gem5.org/documentation/learning_gem5/part2/parameters/#other-simobjects-as-parameters Cheers, Jason On Sat, Aug 1, 2

[gem5-users] Re: QUESTION ABOUT PACKET MEMCMD

Yes, that's correct. If you're writing a full cache system from scratch, then these commands shouldn't matter to you. These are only used in the "classic" cache model to maintain coherence. Cheers, Jason On Wed, Jul 29, 2020 at 2:12 AM 616653241 via gem5-users < gem5-users@gem5.org> wrote: > Hi

[gem5-users] Re: Current status of gem5 capabilities regarding multicores full system simulation

Hi Nathanael, I'm not an expert on the current ARM support, but I believe what you're trying to do should work. I suggest checking out the scripts in configs/example/arm/, specifically, starter_fs.py. These will be more likely to work with current ARM software/OSes. You may also want to check out

[gem5-users] Re: Warning when running GARNET Standalone

Hi Chamika, I believe the problem is that the default tick rate for garnet tests is too small. See this line: https://gem5.googlesource.com/public/gem5/+/refs/heads/master/configs/example/garnet_synth_traffic.py#148 . You can change that line to '1ps' (or get rid of it altogether which would set

[gem5-users] Re: Regarding SMT

Hi Saideepak, I believe that Arm supports SMT. I'm not sure if *any* ISA's support for SMT is tested regularly, though. So it may or may not work. Cheers, Jason On Wed, Jul 22, 2020 at 1:07 AM Saideepak Bejawada via gem5-users < gem5-users@gem5.org> wrote: > Thanks, Jason. > I should have given

[gem5-users] Re: Regarding SMT

Hello Saideepak, Unfortunately, gem5 doesn't support x86+SMT right now. See https://gem5.atlassian.net/browse/GEM5-332 for details. Cheers, Jason On Sat, Jul 18, 2020 at 7:58 PM Saideepak Bejawada via gem5-users < gem5-users@gem5.org> wrote: > Hi all, > > I have a few questions regarding SMT in

[gem5-users] Re: An error occurred in i8237 DMA controller when running CPU SPEC 2017 benchmarks

Hi Jinpeng, Thanks for pointing this out! I haven't personally seen this error before. We've been trying to test SPEC 2017 with gem5-20. Could you give more guest details (e.g., kernel, OS, benchmark, inputs) and simulator details (e.g., ISA, CPU model, memory system, cores, etc.) so we can try to

[gem5-users] gem5-20 paper on arXiv

Hi everyone! I'm excited to announce that we've published a new gem5 paper! Right now, it's available on arXiv at this URL: https://arxiv.org/abs/2007.03152 I tried to reach out to everyone who has been involved in gem5 development since its inception in 2011. However, I'm certain to have missed

[gem5-users] Re: How to track the register values of instructions.

ueue and the ROB. > > Best regards. > Yuan > > On Tue, Jul 7, 2020 at 5:35 PM Jason Lowe-Power > wrote: > >> Hi Yuan, >> >> A couple of suggestions: >> 1. You can use "--debug-file" to output to a file. Or, you can even use a >> named

[gem5-users] Re: How to create two memory object in SE mode

Hi May, This is definitely possible, and it's enabled by these recent changesets: https://gem5-review.googlesource.com/c/public/gem5/+/29027 They haven't been merged, yet, but I'm hopeful they'll be merged soon. Feel free to download them from gerrit and apply them locally :). You should see a do

[gem5-users] Re: How to track the register values of instructions.

when it is > executed or when it is in the commit stage. I tried to check the static or > dynamic instruction classes, but seems that these values are not > carried/stored with each instruction? Am I correct? Could you please give > more hints? > > Best regards. > Yuan > >

[gem5-users] gem5-20.1 roadmap

Hi all, We have just posted the gem5-20.1 roadmap to the gem5 website: http://www.gem5.org/project/2020/07/01/gem5-20-1-roadmap.html After our successful release of gem5-20, it’s

[gem5-users] Re: Syntax Error in gem5 while using bitset template.

Hi Vipin, I don't think you can use templated types in SLICC (in all cases). There have been a few hacks over the years for special cases (if I'm remembering correctly). That said, the easiest thing to do would be to use something other than a bitset in your object. You should be able to use Mach

[gem5-users] Re: RISC-V Full System Simulation

s not what is left and > where I can look. > > Thanks, > Ali > > On Mon, Jul 6, 2020 at 8:26 PM Jason Lowe-Power > wrote: > >> Hi Ali, >> >> See >> https://gem5.googlesource.com/public/gem5/+/refs/heads/master/RELEASE-NOTES.md#new-features. >> In gem5

[gem5-users] Re: RISC-V Full System Simulation

Hi Ali, See https://gem5.googlesource.com/public/gem5/+/refs/heads/master/RELEASE-NOTES.md#new-features. In gem5-20, we added *some* support for full system RISC-V, but not quite enough to boot Linux. TBH, I'm not sure exactly what support is missing. Nils might be able to answer better than I can

[gem5-users] Re: Stores always cause SC_Failed in Ruby/SLICC protocol

Hi Theo, There are a number of poorly documented "rules" to writing SLICC protocols. One rule is that you should not do *anything* other than trigger a transition (call trigger()) in a in_port. This sounds like the underlying problem that you ran into. Another rule that isn't documented is that t

[gem5-users] Re: Stores always cause SC_Failed in Ruby/SLICC protocol

Hi Theo, Yes, it's quite fishy that you're seeing SC_Failed when running an x86 binary. Looking at the code, and to stay with the fish metaphor, I think that it's a red herring. See line 287 in Sequencer.cc. It just always prints llscSuccess whether or not the instruction is an LLSC instruction!

[gem5-users] Re: How to track the register values of instructions.

Hi Yuan, You might find the Exec and ExecAll debug flags useful. Cheers, Jason On Thu, Jul 2, 2020 at 7:48 AM Shougang Yuan via gem5-users < gem5-users@gem5.org> wrote: > Hi, All, > > I am trying to modify the gem5 code and suffer some memory corruption > bugs. I want to look at more details of

[gem5-users] Re: Who translates vaddr to paddr using pagetable_walker? (not vtophys.cc?)

Hi Soramichi, If you're in SE mode, you can call the function "map(Addr vaddr, Addr paddr, int sz, bool cacheable=true);" on the process object from Python. For instance: ``` # Default to running 'hello', use the compiled ISA to find the binary # grab the specific path to the binary thispath = os

[gem5-users] Re: how to run program on gem5 across different number of cycles

Hello, When you call the simulate() function in python, it takes a single parameter, the number of *ticks* to execute. Ticks are usually 1ps. So, it depends on your cycle time what you would pass to simulate. There's a useful function for converting, though. Say you have a clock domain like the f

[gem5-users] Re: Muti-thread workload bug in new version

Hi Taiyu, This seems like a different bug than https://gem5.atlassian.net/browse/GEM5-332. We should probably open a new ticket on Jira. I'm a bit surprised our threads tests didn't catch this. We'll look into it. @Hoa Nguyen , can you create a ticket on Jira and see if you can reproduce this? C

[gem5-users] Re: Hammer protocol

Hi Antonio, Here's the gem5 documentation on it: http://www.gem5.org/documentation/general_docs/ruby/MOESI_hammer/. I believe there were a couple of published papers in the mid to late 2000s on the protocol as well that might be helpful. The Primer on Coherence and Consistency would probably have

[gem5-users] Re: Problem with gem5 memory latency

Hi everyone, Just FYI, it's not the best practice to modify files in src/ (e.g., src/mem/cache/Cache.py) if you want to change a parameter. Those are *source* files. Everything in those files can be overridden in the *python configuration* files. You can simply change something in your config file

[gem5-users] Re: [gem5-dev] [Suggestion] Replace gem5-users mailing-list with Discourse

+1 for Discourse :). Just to give a bit more context: I'm also trying to find a good forum for community engagement during my online Learning gem5 class this summer. I would like to find a platform that could be used generally for my class this summer, future iterations of the class, and general g

[gem5-users] Re: Suggestion required for additonal structure for metadata

Hi Vipin, It depends. If modeling the coherence and interconnection network is important to your results, then SLICC/Ruby/Garnet is probably the way to go. If you're focusing on some other aspect of the system, then making minor modifications to the Cache object and adding a new SimObject for you

[gem5-users] Re: Regarding RISCV's Compressed conditional branching instructions

Hi Anuj, Does this result in incorrect execution? Could you give us a full example of where this happens so we can reproduce it? Thanks, Jason On Fri, Jun 5, 2020 at 8:07 AM Anuj Falcon via gem5-users < gem5-users@gem5.org> wrote: > In RISCV, when the condition of the conditional compressed bra

[gem5-users] Re: [SE Multicore Ruby] Assertion failed for multicore simulation

Hi Taiyu, Can you give us more details on what you are running so we can reproduce this issue? It could be as simple as the path to the binary is wrong :). However, it's hard to tell with just the error message. Cheers, Jason On Thu, Jun 4, 2020 at 10:38 PM Taiyu Zhou via gem5-users < gem5-users

[gem5-users] Re: a problem about memory access latency of HMC

Hello, This is a good question for which I don't have a simple answer. I think we would need more context in the access stream/debug trace. I also suggest digging into the code to see what happens when the line "Single request, going to a busy rank" is printed. The code around that DPRINTF will pr

[gem5-users] Call for topics at gem5 town hall

Hi everyone! As you may be aware, we're going to have a gem5 virtual town hall event on Thursday with the gem5 workshop. I'm super excited for the opportunity to bring the community together and hear feedback! Details: http://www.gem5.org/events/isca-2020#workshop-schedule-june-4th Registration (

[gem5-users] Re: Problem compiling gem5 with Ubuntu 20.04

No such file or directory > > I was wondering if "a temporary issue with python3 support" has been > resolved or it is still a working progress. > > Thanks > Sam > > On Mon, May 18, 2020 at 3:07 PM Jason Lowe-Power > wrote: > >> Hi Sam, >> >&

[gem5-users] gem5 workshop details: June 3rd and 4th

2020 . gem5 Town hall On Thursday June 4th, we will host a gem5 community town hall. This town hall will begin with an introduction and short keynote from Jason Lowe-Power on gem5-20 and the future of gem5. Then, we will have a set of discussion topics to solicit feedback from the broader community.

[gem5-users] Re: Any way to add randomization into full system simulation?

Hi Heng, I suggest modifying the Bridge object to allow for random latency. Then, you can "splice" (see port.splice) the Bridge between your LLC and memory controllers. You can also set the random seed from the python run script (I don't remember exactly how, but grep for "random" in the src/m5 di

[gem5-users] Re: GEM5/Ruby

Hi Javed, Unfortunately, there's no protocols in gem5 out of the box that model *exactly* what you need. However, SLICC allows you to write your own protocols! It sounds like that is what would be best if you need such a specific coherence protocol. See http://www.gem5.org/documentation/general_do

[gem5-users] Re: Problem compiling gem5 with Ubuntu 20.04

Hi Sam, This is a temporary issue with python3 support. Once gem5-20 is released (hopefully today or tomorrow), this issue should be resolved. In the meantime, you can try to downgrade to python 2 and run `python2 scons` or use an ubuntu 18.04 docker image (see http://www.gem5.org/documentatio

[gem5-users] Re: Adding new source files

Hi Alex, Have you read through part 2 of Learning gem5? http://www.gem5.org/documentation/learning_gem5/part2/environment/ That might help this confusion. It sounds like you added the SimObject() call to the wrong Sconscript file. You have to add it to the file in the same directory. Also, your f

[gem5-users] Re: Traces of instructions only.

Hi Øivind, I would check out the documentation on the TraceCPU: http://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU. I think that page describes how to capture the traces. Cheers, Jaosn On Wed, May 6, 2020 at 12:53 PM Øivind Harket Bakke via gem5-users < gem5-users@gem5.org> wrote

[gem5-users] Re: Running simple program with atomic memory at different frequencies. Tick count in the traces are confusing.

Hi Øivind, Atomic mode should not be used for timing. While *some* timing is required even in atomic mode (gem5 is still an event driven simulator), the timing is meaningless. To answer your question as to "why": it's because only the memory system is "atomic" the rest of the simulator is still o

[gem5-users] Re: [UPDATE] gem5 Workshop with ISCA 2020

ttp://www.gem5.org/events/isca-2020 for details. You can submit your abstracts via this google form: https://forms.gle/UnpFXRvpLEFKJBb46 Looking forward to reading your abstracts! Cheers, Jason & the gem5 workshop team On Wed, Apr 8, 2020 at 5:36 PM Jason Lowe-Power wrote: > Hi all, > >

[gem5-users] Re: How to access registers while processing cache miss?

Hi Abhijith, I'm not sure exactly what you're asking here. However, the request object (in the packet) should have a masterID which refers to the original requestor. You can use `system->lookupMasterId` to get the SimObject that created that request. Cheers, Jason On Mon, Apr 27, 2020 at 5:47 A

[gem5-users] Call for help: gem5-20 release

Hi everyone! I'm super excited to say that we're getting close to our first new release: gem5-20! However, there's a ton of work left for us to have a successful release. Anything you (anyone and everyone!) can do to help would be greatly appreciated! As some of you may have noticed, our Gerrit r

[gem5-users] Re: [NOTICE] Mailing lists successfully migrated!

Thanks, Bobby! To everyone: In the past few months, we've had many reports of "missing" emails where emails sent to gem5-users or gem5-dev were only received by some people on the list. If you notice this happening again, please let us know ASAP so we can look into it on the new mail server. Chee

[gem5-users] [UPDATE] gem5 Workshop with ISCA 2020

2020 at 4:41 PM Jason Lowe-Power wrote: > Hi all, > > [Apologies if you receive multiple notices!] > > In conjunction with ISCA 2020, we will be holding a gem5 Tutorial and > Workshop on May 30th in Valencia, Spain. In the morning, we will be running > a Learning gem5 Tuto

Re: [gem5-users] gem5 gcn3 (GPU) power model

Hi Dan, We're currently working on getting the branch here: https://gem5.googlesource.com/amd/gem5/+/refs/heads/agutierr/master-gcn3-staging into the mainline. From what I understand, that branch contains the most up to date GPU code. However, there is no power model for the GPU. As far as McPAT

Re: [gem5-users] Regarding status matrix

Hi Kavya, We currently don't have any ARM FS tests or MESI_Three_Level tests set up to run. I'm hoping soon to have a page describing how to contribute to gem5art to add more tests. Keep an eye out on the gem5 blog for this in the coming weeks. Cheers, Jason On Mon, Apr 6, 2020 at 8:08 PM Kavya

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