Re: [gem5-users] devices.py

Hello Please see comments in-line. Tks JO > -Original Message- > From: Ciro Santilli [mailto:ciro.santi...@arm.com] > Sent: 04 November 2019 18:07 > To: gem5 users mailing list ; Javed Osmany > > Subject: Re: [gem5-users] devices.py > > > > On 10/29/1

[gem5-users] gem5 stats

Hello I wanted to experiment with enabling/disabling the existing stats in GEM5 before I start delving into adding stats. What would be the simplest way that I can disable some existing stats in GEM5 and check that the stat has not been generated by checking the m5out/stats.txt file after

Re: [gem5-users] gem5 stable release proposal [PLEASE VOTE!]

Hello Jason My vote is: "I think master should be stable" Best regards J.Osmany > -Original Message- > From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Jason > Lowe-Power > Sent: 16 December 2019 19:50 > To: gem5 Developer List ; gem5 users mailing list > > Subject:

[gem5-users] ARM HPI model not working on latest version of GEM5

Hello I cloned a cleaned version of GEM5 from the repository and got the ARM Isa gem5.opt built. However, when I run the simple hello world test for the HPI() arm model, I am getting the following error: [j00533938@lhrplinux1 gem5]$ ./build/ARM/gem5.opt configs/example/arm/starter_se.py

Re: [gem5-users] ARM HPI model not working on latest version of GEM5

Hello Have tried the new fix and this is now working okay. Tks From: Gabe Black [mailto:gabebl...@google.com] Sent: 26 October 2019 06:18 To: Ciro Santilli Cc: gem5 users mailing list ; Javed Osmany Subject: Re: ARM HPI model not working on latest version of GEM5 Can you give this a try

[gem5-users] system.cpu

Hello I have a simple system simulation configuration script where I set system.cpu: system.cpu = O3_ARM_v7a.O3_ARM_v7a_3() I then try to print this to confirm and then furthermore set the system.mem_mode depending upon the cpu type being used. However, when I try print ("System CPU type

[gem5-users] devices.py

Hello I am trying to model a simple system using the MinorCPU() model. In the Arm Research Starter kit documentation they give an example (page 17) where they make use of devices.L1I, devices.L1D, devices.WalkCache and devices.L2 to instantiate the L1I$, L1D$, L2$ cache subsystem. In my

[gem5-users] FW: Running Dhrystone on GEM5

From: Javed Osmany Sent: 16 October 2019 07:15 To: gem5-users-requ...@gem5.org Cc: Javed Osmany Subject: FW: Running Dhrystone on GEM5 From: Javed Osmany Sent: 15 October 2019 17:54 To: gem5-users-requ...@gem5.org<mailto:gem5-users-requ...@gem5.org> Cc: Javed Osmany mailto:jav

Re: [gem5-users] Difference cpu clock and sys clock

Hello If one wants to set the CPU clock to be different to the system clock, how does one go about doing this? I could not find the mechanism to set the [cpu, system] clocks separately. Regards JO From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Abhishek Singh Sent: 27

Re: [gem5-users] Difference cpu clock and sys clock

bject (e.g., cpu is the child of system if you say system.cpu = TimingSimpleCPU()) is the same as its parent. The Learning gem5 book Part I which covers configuration scripts may be helpful. http://learning.gem5.org/book/part1/simple_config.html Cheers, Jason On Wed, Nov 27, 2019 at 7:47 AM Ja

Re: [gem5-users] Difference cpu clock and sys clock

in your command line —cpu-clock=‘xGHz’ —sys-clock=‘yGHz’ On Wed, Nov 27, 2019 at 2:16 AM Javed Osmany mailto:javed.osm...@huawei.com>> wrote: Hello If one wants to set the CPU clock to be different to the system clock, how does one go about doing this? I could not find the mechanism to set th

[gem5-users] gem5 stats

Hello I wanted to experiment with enabling/disabling the existing stats in GEM5 before I start delving into adding stats. I am assuming that all the stats implemented are enabled by default. What would be the simplest way that I can disable some existing stats in GEM5 and check that the stat

[gem5-users] Cache coherence modelling in GEm5/Ruby

Hi I want to start modelling a multicore architecture in GEM5/Ruby to explore cache coherence protocols. Currently I want to model snoop based coherence protocol - Is this supported in Ruby? Also, any pointers to get started on the cache coherence modelling in GEM5/Ruby would be much

Re: [gem5-users] Cache coherence modelling in GEm5/Ruby

a subsection all about cache coherence that does a great job of explaining it. http://www.gem5.org/documentation/learning_gem5/introduction/ On Fri, Feb 28, 2020 at 6:49 AM Javed Osmany mailto:javed.osm...@huawei.com>> wrote: Hi I want to start modelling a multicore architecture in GEM

Re: [gem5-users] Possible website outage during changeover

On Tue, Feb 11, 2020 at 4:48 PM Javed Osmany mailto:javed.osm...@huawei.com>> wrote: Hi When I try to access http://new.gem5.org, I am getting The Host is not resolvable,please make sure the URL is correct. Is the above the correct URL for accessing the new GEM5 website? Tks in advan

Re: [gem5-users] Possible website outage during changeover

Hi When I try to access http://new.gem5.org, I am getting The Host is not resolvable,please make sure the URL is correct. Is the above the correct URL for accessing the new GEM5 website? Tks in advance JO From: gem5-users [mailto:gem5-users-boun...@gem5.org] On Behalf Of Jason Lowe-Power

[gem5-users] Re: CHI and GEM5 v22.0.0.2

the reporter: https://gem5.atlassian.net/browse/GEM5-1195 Thanks, Tiago ____ From: Javed Osmany mailto:javed.osm...@huawei.com>> Sent: Thursday, September 22, 2022 4:40 PM To: Bobby Bruce mailto:bbr...@ucdavis.edu>>; The gem5 Users mailing list mailto

[gem5-users] CHI and GEM5 v22.0.0.2

Hello I have downloaded GEM5 v22.0.0.2 and wanted to know how many of the reported CHI issues have been fixed in this release? Also is there a way to determine if a particular reported bug has been fixed and included in the latest release? Thanks in advance JO

[gem5-users] Re: CHI and GEM5 v22.0.0.2

Hello Dr Bruce Yes, I was referring to the open Jira issues. OK, I will check the Jira issues for CHI. Best Regards JO From: Bobby Bruce Sent: 22 September 2022 11:41 To: The gem5 Users mailing list Cc: Tiago Muck ; Javed Osmany Subject: Re: [gem5-users] CHI and GEM5 v22.0.0.2 Are you

[gem5-users] GEM5/Ruby

Hello I would like to define a multicore system in GEM5 and then use the Ruby memory system to simulate the different coherence protocols. In my system I have three levels of caches (L1I$, L1D$ (using MSI), unified L2$ (using MOESI) and LLC (using MESI)) How to generate the optimised GEM5

[gem5-users] Re: GEM5/Ruby

Many Thanks Jason for the answer and pointers. Best Regards J.Osmany From: Jason Lowe-Power [mailto:ja...@lowepower.com] Sent: 18 May 2020 21:25 To: gem5 users mailing list Cc: Javed Osmany Subject: Re: [gem5-users] GEM5/Ruby Hi Javed, Unfortunately, there's no protocols in gem5 out

[gem5-users] GEM5/Ruby and MESI_Three_Level protocol

Hello 1. I am able to successfully generate the executable gem5 simulator for [ARM ISA, MESI_Three_Level protocol]. The command I used being: a. scons -j4 build/ARM_MESI_3_level/gem5.opt --default=ARM PROTOCOL=MESI_Three_Level SLICC_HTML=True 2. Also, I am able

[gem5-users] Re: GEM5/Ruby and MESI_Three_Level protocol

To: gem5 users mailing list Cc: Javed Osmany Subject: Re: [gem5-users] GEM5/Ruby and MESI_Three_Level protocol Which files do you think are missing? There are some shared files between MESI_Three_Level and MESI_Two-Level such as the L2 controller. You can find a list of all files used

[gem5-users] Running Gem5/Ruby tests

Hello I am trying to get started running some very simple tests on Gem5/Ruby. However, I am getting errors: [j00533938@lhrplinux1 gem5]$ ./build/X86_MSI/gem5.opt configs/example/se.py --ruby --cpu_type=timing -c tests/test-progs/hello/bin/x86/linux/hello ./build/X86_MSI/gem5.opt:

[gem5-users] Re: Running Gem5/Ruby tests

.so.6.0.19 Just wondering if this is an issue with not linking to the correct version of libstdc++.so Tks in advance. JO From: Javed Osmany Sent: 02 June 2020 16:11 To: gem5 users mailing list Cc: Javed Osmany Subject: Running Gem5/Ruby tests Hello I am trying to get started running some v

[gem5-users] System() and RubySystem()

Hello Trying to understand the following: So in example config scripts I see the following: system = System() // Is this then instantiating the default overall system ?? Now, I understand that there are two types of memory system, namely classic and Ruby. And then if "-ruby" is

[gem5-users] FW: System() and RubySystem()

Hello Wondering if any help to clear up the issues listed in my previous email? Tks JO From: Javed Osmany Sent: 14 June 2021 14:18 To: gem5 users mailing list Cc: Javed Osmany Subject: System() and RubySystem() Hello Trying to understand the following: So in example config scripts I see

[gem5-users] Re: System() and RubySystem()

Many thanks for the clarification Giacomo. Best regards JO -Original Message- From: Giacomo Travaglini [mailto:giacomo.travagl...@arm.com] Sent: 16 June 2021 11:36 To: gem5 users mailing list Cc: Javed Osmany Subject: RE: System() and RubySystem() Hi Javed, You are correct in your

[gem5-users] Arm bitLITTLE config

Hello The system I would like to model consists of three clusters [Big, Middle, Little] Each cluster can have different CPU types and either private or shared L2 cache. Can the config/example/arm/fs_bigLITTLE.py config 1) Support three different clusters? 2) If the answer to 1) is

[gem5-users] Re: Arm bitLITTLE config

Hello Giacomo Many thanks for your answers. Best regards JO -Original Message- From: Giacomo Travaglini [mailto:giacomo.travagl...@arm.com] Sent: 09 June 2021 15:44 To: gem5 users mailing list Cc: Javed Osmany Subject: RE: Arm bitLITTLE config Hi Javed > -Original Mess

[gem5-users] Re: [Big, Little] clusters with CHI and SE mode

Hello Gabriel Thank you for the pointer. Made a start on this and just wanted to check if I have understood you correctly.. >> 1- Define two more options in CHI.py to specify the number of big (B) and the number of little (L) cpus from the command line Okay, Done. >> 2- Define the

[gem5-users] Re: [Big, Little] clusters with CHI and SE mode

Many thanks for the pointers, Gabriel. Best Regards J.Osmany -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 21 June 2021 17:02 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: [Big, Little] clusters with CHI and SE mode

[gem5-users] [Big, Little] clusters with CHI and SE mode

Hello I am trying to model a system such as 1) Initially there are two clusters, [big, little] a. Have studied fs_bigLITTLE.py to see how the different clusters are generated. 2) Make use of CHI 3) Run the system in SE mode. The command I am planning to use is the following

[gem5-users] CHI and caches

Hello I have been studying the CHI documentation and the configs/ruby/CHI.py file. Both the code and the documentation mention about 1) Map each CPU in the system to an RNF with private and split L1 caches 2) Add a private L2 cache to each RNF So what happens if the CPU model

[gem5-users] Re: CHI and caches

Many thanks for the clarification, Gabriel. Best regards JO -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 18 June 2021 17:02 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: CHI and caches Hi, O3_ARM_v7a_3 comes with

[gem5-users] Using the CHI protocol for GEM5

Hello Previously, when experimenting with MESI or MOESI coherence protocol, the approach was to build the gem5.opt for the specific protocol. For example scons -j4 build/ARM_MESI_3_level/gem5.opt --default=ARM PROTOCOL=MESI_Three_Level SLICC_HTML=True I would like to experiment with the CHI

[gem5-users] Re: Using the CHI protocol for GEM5

Hello Giacomo Thanks for the info. Yes, I have been going through the documentation and the blog. Best regards JO -Original Message- From: Giacomo Travaglini [mailto:giacomo.travagl...@arm.com] Sent: 18 May 2021 14:52 To: gem5 users mailing list Cc: Javed Osmany Subject: RE: Using

[gem5-users] Re: Running CHI protocol configurations

then generated a run time error. Best regards JO From: Gabriel Busnot [mailto:gabriel.bus...@arteris.com] Sent: 02 June 2021 15:44 To: gem5 users mailing list Cc: Javed Osmany Subject: RE: Running CHI protocol configurations Hi Javed, Answers inline. Best, Gabriel From: Javed Osmany via gem5-use

[gem5-users] Running CHI protocol configurations

Hello Have generated an ARM ISA gem5.opt executable, where the PROTOCOL CHI. Running the simple "Hello World" program on a config of [4 RNFs, 2 HNFs, 2 SNFs] and looking at the config.ini file, there are a few things I don't understand. The command I use being: ./build/ARM/gem5.opt

[gem5-users] Re: [Big, Little] clusters with CHI and SE mode

Hello Gabriel Thank you for the updated information. Will try to follow for the implementation. Best regards JO -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 24 June 2021 08:33 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users]

[gem5-users] Re: [Big, Little] clusters with CHI and SE mode

regards JO -Original Message- From: Javed Osmany Sent: 28 June 2021 12:58 To: gem5 users mailing list Cc: Gabriel Busnot ; Javed Osmany Subject: RE: [gem5-users] Re: [Big, Little] clusters with CHI and SE mode Hello Gabriel Thank you for the pointer. Best regards J.Osmany -Original

[gem5-users] Re: [Big, Little] clusters with CHI and SE mode

tem.cpu0.l1d.data_channel_size without default or user set value Any pointers as to where I should look to resolve the errors? Thanks in advance JO -Original Message- From: Javed Osmany Sent: 24 June 2021 10:09 To: gem5 users mailing list Cc: Gabriel Busnot ; Javed Osmany Subject: RE: [gem5-u

[gem5-users] Re: [Big, Little] clusters with CHI and SE mode

Hi Gabriel Outlook blocked the attachments. Resending the two files as WinRar archive. Best regards JO _ From: Javed Osmany Sent: 28 June 2021 11:35 To: gem5 users mailing list Cc: Gabriel Busnot ; Javed Osmany Subject: RE: [gem5-users] Re: [Big

[gem5-users] Re: [Big, Little] clusters with CHI and SE mode

Hello Gabriel Thank you for the pointer. Best regards J.Osmany -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 28 June 2021 12:49 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: [Big, Little] clusters with CHI and SE mode

[gem5-users] CHI - Cluster CPUs having a private L2 cache

Hello I am using CHI and I want to model the scenario where the CPUs are in a cluster and each cluster CPU has private L1 and L2 caches. I have modified CHI.py and CHI_config.py. In CHI_config.py, I have taken a copy of CHI_RNF() class object and renamed the copied version

[gem5-users] Re: CHI - Cluster CPUs having a private L2 cache

Hello Gabriel Thank you for your reply. Will realise your suggestions. Best regards JO -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 12 July 2021 09:23 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: CHI - Cluster CPUs

[gem5-users] Re: CHI and Ruby Cache block size

Hello Gabriel Thank you for the clarification. Best regards J.Osmany -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 17 August 2021 09:33 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: CHI and Ruby Cache block size Hi

[gem5-users] Re: CHI, Ruby - changing cacheline size

Hello Gabriel Thank you, once again, for the pointers. Best regards J.Osmany -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 27 August 2021 10:53 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: CHI, Ruby - changing

[gem5-users] CHI, Ruby - changing cacheline size

Hello I am using CHI protocol and the Ruby memory system. I am trying to run the Parsec and Splash2 benchmarks by varying the cache line size using the command line option cacheline_size. It works for cacheline_size = 64, 128, 256 but not for 32. I am using gem5-21.0 Command I am using is

[gem5-users] CHI and Ruby Cache block size

Hello I am using the CHI protocol with Ruby. The CHI L1 Cache and L2 Cache are derived from the RubyCache class model. My question: Within Ruby, is it possible to have different cache line size for the L1 and L2 caches? I had a look at src/mem/ruby/structures/RubyCache.py and there is only

[gem5-users] Re: CHI - Cluster CPUs having a shared L2 cache

-inclusive of the upstream L1 caches. Can you please confirm if this is the case? Best regards J.Osmany _ From: Javed Osmany Sent: 04 August 2021 08:38 To: gem5 users mailing list Cc: Gabriel Busnot ; Javed Osmany Subject: RE: [gem5-users] Re: CHI

[gem5-users] Re: CHI - Cluster CPUs having a shared L2 cache

Hello Gabriel Many thanks for your thoughts. Just checking, is Tiago's email tiago.m...@arm.com? Best regards J.Osmany -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 10 August 2021 09:59 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject:

[gem5-users] Re: CHI - Cluster CPUs having a shared L2 cache

is assertion issue would be much appreciated. I am attaching (as a winzip rar file) the updated CHI.py, CHI_config.py files. Also included is the custom version of the se.py used to run the test and the snippet of the trace file prior to the assertion firing when DPRINTF is enabled. Best regards J

[gem5-users] Re: Access to gem5 101 course

: Access to gem5 101 course Hello Javed Osmany, Did you try clicking the links to the different parts of the course? Thanks, Scott Blankenberg ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org

[gem5-users] Re: Access to gem5 101 course

Hello No progress on accessing that link for me. However, the following two urls might give some insight. http://pages.cs.wisc.edu/~david/courses/cs752/Fall2015/ https://pages.cs.wisc.edu/~sinclair/courses/cs752/fall2020/includes/schedule.html BR JO -Original Message- From: Ioannis

[gem5-users] Re: set cache line size under o3 cpu

Hello This is because the fetchBufferSize in O3CPU.py is set to 64 bytes and you are trying to set the cache line size to 32 bytes. In your local version of se.py, add the following code: if (options.cacheline_size == 32): DerivO3CPU.fetchBufferSize = 32 Best regards J.Osmany

[gem5-users] CHI_config.py

Hello In CHI_config.py, for the class CHI_HNFController we have class CHI_HNFController(CHI_Cache_controller): : : # Some reasonable default TBE params self.number_of_TBEs = 32 self.number_of_repl_TBEs = 32 self.number_of_snoop_TBEs = 1 #

[gem5-users] Re: CHI_config.py

roller class objects. In these cases the number_of_snoop_TBEs attribute is used to handle the number of snoop requests the respective cache controller can receive. Best regards J.Osmany From: Javed Osmany Sent: 05 October 2021 16:33 To: gem5-users@gem5.org Cc: Javed Osmany Subject: CHI_conf

[gem5-users] Re: Access to gem5 101 course

The link is working okay for me. Best regards JO From: Bobby Bruce via gem5-users [mailto:gem5-users@gem5.org] Sent: 22 September 2021 18:53 To: gem5 users mailing list Cc: scot...@synopsys.com; Bobby Bruce Subject: [gem5-users] Re: Access to gem5 101 course Yip, dead link for me as well.

[gem5-users] Re: CHI - Cluster CPUs having a shared L2 cache

ment the shared L2Cache would be much appreciated. Thanks in advance JO -Original Message- From: Javed Osmany Sent: 12 July 2021 09:29 To: gem5 users mailing list Cc: Gabriel Busnot ; Javed Osmany Subject: RE: [gem5-users] Re: CHI - Cluster CPUs having a private L2 cache Hello Gab

[gem5-users] Re: CHI - Cluster CPUs having a shared L2 cache

Hello Gabriel >> addSharedL2Cache is only called on lines 465 and 470 of CHI.py and these >> lines are touched only if options.littleclust_l2cache == 'shared'. >> You don't set it in the command line and the default value is 'private', >> which explains why it never gets called. The command

[gem5-users] Re: CHI - Cluster CPUs having a shared L2 cache

Hi Gabriel Many thanks for your insight and input. I have taken on board your suggestion and simplified the customisation of CHI.py and CHI_config.py by just using the CHI_Config.CHI_RNF() class object and adding another method to CHI_Config.CHI_RNF(), called addSharedL2Cache. Also I have

[gem5-users] CHI

Hello I am using the latest version of gem5 (21.2.1.0). Previously, when using gem5 version 21.0.0.0, in the function "def define_options(parser)" (in CHI.py), I added some command line options as such: def define_options(parser): parser.add_option("--chi-config", action="store",

[gem5-users] Re: CHI

in the latest gem5 release? Tks in advance JO From: Javed Osmany Sent: 02 March 2022 15:00 To: gem5 users mailing list Cc: Javed Osmany Subject: CHI Hello I am using the latest version of gem5 (21.2.1.0). Previously, when using gem5 version 21.0.0.0, in the function "def define_op

[gem5-users] Re: CHI

to download the latest gem5 (21.2.1.0) directly from github and am now able to successfully compile it for the CHI protocol. Regards JO From: Javed Osmany Sent: 02 March 2022 15:44 To: gem5 users mailing list Cc: Javed Osmany Subject: RE: CHI Hello So I thought the reason why my previous

[gem5-users] Re: CHI

Hello Bobby It was our local gitlab repository, where the problem resided. Tks JO From: Bobby Bruce [mailto:bbr...@ucdavis.edu] Sent: 03 March 2022 22:07 To: gem5 users mailing list Cc: Javed Osmany Subject: Re: [gem5-users] Re: CHI Which gitlab repository was this? I don't believe we

[gem5-users] CHI - data/tag latency modelling for HNF/L3$

Hello I am trying to model a multicore SOC system using Ruby and CHI and I am trying to model data/tag latency for the L3$ which resides in the HNF. Looking in CHI.py and CHI_config.py, I could not see any mechanisms to model this. Could someone please let me know if this is possible and if

[gem5-users] Re: Re：CHI - data/tag latency modelling for HNF/L3$

Hello Fu Thks for that. I was looking at CHI.py yesterday evening, but somehow missed that. Best regards JO From: zexin Fu via gem5-users [mailto:gem5-users@gem5.org] Sent: 08 April 2022 08:04 To: zexin Fu via gem5-users Cc: zexin Fu <1056844...@qq.com> Subject: [gem5-users] Re: Re：CHI -

[gem5-users] CHI - measure of the snoop traffic

Hello I am modelling a Ruby based CHI multicore, 3-cluster system with two different configs. In one config, all the cluster CPUs have a private L2$ and in the other config, for two clusters, the CPUs share an L2$. I wanted to check the snoop out traffic at the L2$ controller and the HNCache

[gem5-users] Re: CHi - assertion error when modelling "mostly inclusive" for private L2$

lidate the upstream cache line. Any insight as to why the above encoding for mostly exclusive might be wrong and thus causing the assertions to fire, would be greatly appreciated. Thanks in advance JO From: Javed Osmany Sent: 21 April 2022 16:03 To: gem5 users mailing list Cc: Javed

[gem5-users] CHi - assertion error when modelling "mostly inclusive" for private L2$

Hello I am simulating a multicore Ruby system using CHI, using the Parsec/Splash2 benchmarks & gem5-21.2.1.0. It consists of three clusters : 1) Little cluster of 4 CPUs, each CPU has private L1$ and L2$ 2) Middle cluster of 3 CPUs, each CPU has private L1$ and L2$ 3) Big

[gem5-users] Re: CHi - assertion error when modelling "mostly inclusive" for private L2$

pdating the directory state within HNF1. The L2$ wants to make the requested cache line to be exclusive. Thus dir_sharers.count should be zero (as the cache line now only resides in a single L2$). QS: Is this possibly a CHI bug? P.S : I have also attached the gzipped version of the log file.