[gem5-users] Support for multicore for X86 O3 CPU Full System with classical memory

Hello All, I am running into trouble running full system simulation with 2 X86 O3 cores and classical memory system where the system seems to get stuck during script execution. I read in other (relatively) old posts that multicore might not be supported for this configuration (X86-O3-classical

Re: [gem5-users] [EXT] Accessing logical (software) thread ID in gem5

UPDATE: If I call curTaskPIDFromTaskStruct() instead of curTaskPID() both kernels give the same error of "panic: vtophys page walk returned fault" On Mon, Jan 14, 2019 at 12:19 PM Shehab Elsayed wrote: > So, I tried adding this patch to kernels 4.3 and 4.8.13. Both kern

Re: [gem5-users] [EXT] Accessing logical (software) thread ID in gem5

.com/gem5/linux-arm-gem5-legacy/commit/516ba2d255b502b1dad07662bd18110f3bf37b1b > > > > *From:* gem5-users [mailto:gem5-users-boun...@gem5.org] *On Behalf Of *Shehab > Elsayed > *Sent:* Friday, January 11, 2019 10:58 PM > *To:* gem5 users mailing list > *Subject:* Re: [gem5-users] [EXT] Accessin

Re: [gem5-users] Support for multicore for X86 O3 CPU Full System with classical memory

I'm not specifically aware of a problem with O3 and multicore on x86. Can > you point out the posts you're referring to? O3 and multicore both add a > dimension of complexity, so that would be a more likely place for bugs to > crop up. > > Gabe > > On Fri, Nov 16, 2018 at 7:20 AM

[gem5-users] Accessing logical (software) thread ID in gem5

Hello All, I was wondering if there is a way to differentiate between different logical (software) threads in gem5. I am trying to collect some stats for each logical thread and so far all I could find in gem5 is access to physical threads. I know that logical threads is the responsibility of the

Re: [gem5-users] [EXT] Accessing logical (software) thread ID in gem5

I’ve worked on this sort of thing but you might be able to look at > this patch for some hints about where to look: > > > > https://gem5-review.googlesource.com/c/public/gem5/+/2640 > > > > > > Cheeers, > > Paul > > > > *From:* gem5-users [mailto:gem5

[gem5-users] Full System hangs or exits to login

Hello All, When I try running some benchmarks (Splash 3) in Full System, gem5 seems to hang after some time, usually in the middle of a print statement in the gem5 terminal or some other times it seems to exit the benchmark to the Ubuntu log in prompt! My setup: I create a checkpoint after

[gem5-users] Full system sometimes ignores rcS script

Hello All, Is it normal that a full system simulation sometimes ignores the rcS script and just goes to the ubuntu log in screen directly? I sometimes run into this problem and then I just run the command again without any change and it starts executing the rcS script. Thanks in advance, Shehab

Re: [gem5-users] Full system sometimes ignores rcS script

ipt with a checkpoint? > > Ryan Gambord > > > > > On Thu, Jun 27, 2019 at 2:48 PM Shehab Elsayed > wrote: > >> Hello All, >> >> Is it normal that a full system simulation sometimes ignores the rcS >> script and just goes to the ubuntu log in screen direct

Re: [gem5-users] Indeterministic gem5 behavior

e load instruction that is not > executed. > > Best, > > On Mon, Sep 9, 2019 at 11:28 AM Shehab Elsayed > wrote: > >> I am not sure that prefetch_nta is the problem. For different runs the >> simulation would fail after different periods after printing the prefetch &

Re: [gem5-users] Indeterministic gem5 behavior

recently non-temporal > ones that I added) that are executed as two 64-bit loads, and possibly the > second one is failing due to the cda check that we do, and that stops the > load from being committed. > > Best, > > On Wed, Sep 11, 2019 at 1:16 PM Shehab Elsayed > wrote: &g

Re: [gem5-users] Indeterministic gem5 behavior

t, > > On Fri, Sep 6, 2019 at 8:58 AM Shehab Elsayed > wrote: > >> First of all, thanks for your replies, Ryan and Jason. >> >> I have already pulled the latest changes by Pouya and the problem still >> persists. >> >> As for checkpointing, I was

Re: [gem5-users] Indeterministic gem5 behavior

-start and --debug-end > you should be able to get that. > > Best, > > On Wed, Sep 11, 2019 at 2:15 PM Shehab Elsayed > wrote: > >> Is there a way to get the macroop from the corresponding instruction >> pointer? >> >> >> On Wed, Sep 11, 2019 at 5:07

Re: [gem5-users] Indeterministic gem5 behavior

needsTSO to True and consequently force_squash to True as well). But looks like the Instructions are not squashed as far as I can tell. I am not sure if this helps narrow down the problem or not but I hope it helps! On Thu, Sep 12, 2019 at 2:52 PM Shehab Elsayed wrote: > Looks l

Re: [gem5-users] Indeterministic gem5 behavior

n older architecture with less optimization on a "newer" > system is the equivalent of not using "parts/features" of your system (e.g. > SIMD units, direct prefetch, etc), which would (possibly) directly impact > any study you are working on. > > Best, > > On S

Re: [gem5-users] Indeterministic gem5 behavior

6, 2019 at 11:47 AM Jason Lowe-Power > wrote: > >> Hi Shehab, >> >> IIRC, there are some issues when using classic caches + x86 + multiple >> cores on full system mode. I suggest using Ruby (MESI_two_level or >> MOESI_hammer) for FS simulations. >> &g

Re: [gem5-users] Indeterministic gem5 behavior

inst->clearExecuted(); continue; } // End of added check . . . . } I am having better luck with this modification but Ruby (MOESI_hammer) still sometimes runs into deadlock On Mon, Sep 16, 2019 at 2:52 PM Shehab E

Re: [gem5-users] Indeterministic gem5 behavior

ts. > > One other note: Pouya has pushed some changes which implement some x86 > instructions that were causing issues for him. You can try with the current > gem5 mainline to see if that helps. > > Cheers, > Jason > > On Fri, Sep 6, 2019 at 8:22 AM Shehab Elsayed > wrote: &

Re: [gem5-users] Indeterministic gem5 behavior

I was wondering if anyone is running into the same problem or if anyone has any suggestions on how to proceed with debugging this problem. On Mon, Jul 29, 2019 at 4:57 PM Shehab Elsayed wrote: > Sorry for the spam. I just forgot to mention that the system configuration > I am using is

Re: [gem5-users] Indeterministic gem5 behavior

inside an ubuntu vm on qemu and have had much more > consistent results. I haven't tried running kvm gem5 inside a kvm qemu vm, > so not sure how that works, but might be worth trying. > > Ryan > > > On Fri, Sep 6, 2019, 08:07 Shehab Elsayed wrote: > >> I was wonderin

Re: [gem5-users] Indeterministic gem5 behavior

) Any help is really appreciated. On Tue, Jul 23, 2019 at 11:01 AM Shehab Elsayed wrote: > When I enable the Exec debug flag I can see that it seems to be stuck in a > spin lock (queued_spin_lock_slowpath) > > On Fri, Jul 19, 2019 at 5:28 PM Shehab Elsayed > wrote: > &g

Re: [gem5-users] Indeterministic gem5 behavior

dwards S. Rogers Sr. Dept. of Electrical and Computer Engineering University of Toronto E-mail: shehaby...@gmail.com <https://webmail.rice.edu/imp/message.php?mailbox=INBOX=11#> On Mon, Jul 29, 2019 at 4:08 PM Shehab Elsayed wrote: > I have set up a repo with gem5 that demonstra

[gem5-users] Indeterministic gem5 behavior

Hello All, I have a gem5 X86 full system set up that starts with KVM cores and then switches to O3 cores once the benchmark reaches the region of interest. Right now I am testing with a simple multithreaded hello world benchmark. Sometimes the benchmark completes successfully while others gem5

Re: [gem5-users] Indeterministic gem5 behavior

When I enable the Exec debug flag I can see that it seems to be stuck in a spin lock (queued_spin_lock_slowpath) On Fri, Jul 19, 2019 at 5:28 PM Shehab Elsayed wrote: > Hello All, > > I have a gem5 X86 full system set up that starts with KVM cores and then > switches to O

[gem5-users] Panic: Invalid microop with X86 and MinorCPU

Hello All, I recently started testing the MinorCPU model and X86_MOESI_hammer in full system. However, the simulation terminates with this error panic: Invalid microop The exact same test runs fine with TimingSimpleCPU. Is there anything special that has to be done in order to get MinorCPU to

[gem5-users] Adding pseudo instructions in ARM

Hello All, I was wondering if there a document or a tutorial somewhere describing how to add pseudo instructions in the ARM architecture. I went through the process before but for X86. However, I see there are some differences especially in adding the extra instructions to the ISA. Thanks in

[gem5-users] O3 LSQ operation

Hello All, First of all, I should point out that this is related to a previous question I have posted in https://www.mail-archive.com/gem5-users@gem5.org/msg16701.html but I believe the discussion has diverted from the initial problem so I thought it might be a good idea to start another thread.

[gem5-users] Configuring cache bandwidth in Ruby/classical memory system

Hello All, I was wondering if there is a way to specify the bandwidths for the different caches in the simulated system? For example, let's say I want to simulate a system that resembles the Ivy Bridge architecture as much as possible which according to this link (

Re: [gem5-users] Problem with DerivO3CPU and Ruby in FS

and then you run the application from > userland after boot? > > Do you boot with Atomic and restore the checkpoint, or did full boot in O3? > ---------- > *From:* gem5-users on behalf of Shehab > Elsayed > *Sent:* Tuesday, October 22, 2019 7:39 PM &

[gem5-users] Problem with DerivO3CPU and Ruby in FS

Hello All, Could someone please confirm whether DerivO3CPU with Ruby are working properly? I have been having the same problem with both X86 and ARM when running a multithreaded application (a simple hello world program with 2 threads) on DerivO3CPU and Ruby. After some time I get an assertion

Re: [gem5-users] Delayed printing to telent localhost 3456

, 2019 at 11:55 AM Shehab Elsayed wrote: > Hi Jason, > > Thanks for the quick reply. I will give it a try with the m5 writefile. I > will also keep this thread updated with any findings I might have. > > Best Regards, > Shehab > > On Fri, Oct 4, 2019 at 11:46 AM Jason L

Re: [gem5-users] Problem with DerivO3CPU and Ruby in FS

as trying to achieve. Any ideas on how to properly fix this? Thanks! On Thu, Oct 17, 2019 at 10:34 AM Shehab Elsayed wrote: > Hello All, > > Could someone please confirm whether DerivO3CPU with Ruby are working > properly? > > I have been having the same problem with both X86 and ARM

Re: [gem5-users] Delayed printing to telent localhost 3456

instead of the terminal. > > Cheers, > Jason > > On Fri, Oct 4, 2019 at 8:40 AM Shehab Elsayed > wrote: > >> Hello All, >> >> I have an rcS script that prints a statement to the terminal and then >> switches cpus and does some more stuff. I can see the effect of

[gem5-users] Delayed printing to telent localhost 3456

Hello All, I have an rcS script that prints a statement to the terminal and then switches cpus and does some more stuff. I can see the effect of switching cpus in the gem5 (host) terminal a very long time before the printed statement starts appearing on the simulated (guest) terminal. I even have

Re: [gem5-users] Adding pseudo instructions in ARM

--- > *From:* gem5-users on behalf of Shehab > Elsayed > *Sent:* Tuesday, October 1, 2019 3:30 PM > *To:* gem5 users mailing list > *Subject:* [gem5-users] Adding pseudo instructions in ARM > > Hello All, > > I was wondering if there a document or a tutorial somewhere des

[gem5-users] Changing configuration between checkpoint and restore

Hello All, I was wondering which configuration parameters are safe to change between taking a checkpoint and restoring from the same checkpoint. For example, cache configuration, core configuration, number of LLC banks, number of cores, Also, Is there a way to tell whether a configuration

Re: [gem5-users] Fwd: Changing configuration between checkpoint and restore

I am afraid I don't know what you mean! On Mon, Jan 6, 2020 at 11:11 AM CS18M010 RICHA CHAUDHRY < cs18m...@iittp.ac.in> wrote: > how to install gem 5 initial stage > > -- Forwarded message ----- > From: Shehab Elsayed > Date: Mon, Jan 6, 2020 at 9:39 PM &

Re: [gem5-users] Changing configuration between checkpoint and restore

Thanks, Ciro! This makes sense. So I guess one example for things that shouldn't change between checkpointing and restoring is the number of cores while the cache sizes should be OK to change. On Mon, Jan 6, 2020 at 11:50 AM Ciro Santilli wrote: > On Mon, Jan 6, 2020 at 4:09 PM Shehab Elsa

[gem5-users] Simulation terminates successfully on one machine and runs into assertion failure on another

Hello All, I am trying to run the same experiment (ARM full system with RUBY MESI_Three_level that boots from checkpoint) on two different machines. It terminates successfully on one but runs into assertion failure on the other. This is the terminating message: Addr Request::getPaddr() const:

Re: [gem5-users] Simulation terminates successfully on one machine and runs into assertion failure on another

detail as possible about content, and ensure you have > https://gem5-review.googlesource.com/c/public/gem5/+/22283/4 ideally on a > bug report at: > https://gem5-review.googlesource.com/c/public/gem5/+/22283/4 > -- > *From:* gem5-users on behalf of Sheh

Re: [gem5-users] Ruby functional read fails and potential fix

patchset: > https://gem5-review.googlesource.com/c/public/gem5/+/22022/1 > > On Thu, Apr 9, 2020 at 6:22 PM Shehab Elsayed > wrote: > > > > Hello All, > > > > I was running some experiments and I ran into a problem with ruby where > a functional re

[gem5-users] Ruby functional read fails and potential fix

Hello All, I was running some experiments and I ran into a problem with ruby where a functional read was failing. After some investigation I found that the reason was that the functional read was trying to read a line that was in a MaybeStale state (no ReadOnly or ReadWrite versions). I

[gem5-users] Question about Ruby cache latencies

Hello All, In MOESI_CMP_directory, the ruby cache latencies (tagAccessLatency and dataAccessLatency) are included in the SLICC cache controllers through cacheReponsLatency() function. However, the function is only included in messages that include a data response while all other messages use the

[gem5-users] Re: Question about Ruby cache latencies

del since each protocol > can have different assumptions regarding how a cache lookup/update latency > would affect each transaction. > > Best, > Tiago > ---------- > *From:* Shehab Elsayed > *Sent:* Thursday, May 14, 2020 11:50 AM > *To:* gem5 us

[gem5-users] Re: Question about Ruby cache latencies

Thank you very much for your reply and explanation, Tiago! Wouldn't it be more generic to add the latencies at the time of performing the access in the cache itself instead of having it in the controllers since any cache access should incur access latency? I am not sure how easy that would be

[gem5-users] Re: GEM5/Ruby and MESI_Three_Level protocol

Which files do you think are missing? There are some shared files between MESI_Three_Level and MESI_Two-Level such as the L2 controller. You can find a list of all files used by the MESI_Three_Level protocol in src/mem/ruby/protocol/MESI_Three_Level.slicc. I hope this helps. On Thu, May 28, 2020

[gem5-users] Re: 2 level TLB in ARM Full System with Ruby

matter since the TLB sits behind > caches anyways? I believe that model will work for either classic or Ruby. > ---------- > *From:* Shehab Elsayed via gem5-users > *Sent:* Tuesday, June 23, 2020 12:20 AM > *To:* gem5 users mailing list > *Cc:* Shehab Elsayed

[gem5-users] 2 level TLB in ARM Full System with Ruby

Hello All, I was wondering if there is a way to simulate a system with 2 levels of TLBs in full system simulation with ruby for ARM? I have seen other examples that use the classical memory model and use a cache as the second level TLB. Is there something similar that can be done in Ruby memory

[gem5-users] Modelling a deeper pipeline (O3-ARM)

Hello All, I am trying to model a deeper O3 pipeline as suggested in https://gem5-users.gem5.narkive.com/LNMJQ1M5/model-deeper-pipeline-in-x86 but I keep running into some assertion failures related to the time buffers and skid buffers even though that patch mentioned in the previous link is

[gem5-users] Setting up cluster for gem5

Hello All, My group is in the process of upgrading our cluster and since many of us are using gem5 I was wondering if anyone has experience or recommendation they would like to share about the process for a smooth gem5 operation. Mainly I am concerned about 2 issues: 1) Required hard disk and

[gem5-users] Re: Setting up cluster for gem5

t; > Dan Gerzhoy > PhD Candidate, Computer Engineering > University of Maryland College Park > > On Fri, Nov 6, 2020 at 8:38 AM Shehab Elsayed via gem5-users < > gem5-users@gem5.org> wrote: > >> Hello All, >> >> My group is in the process of upgrading ou