[gem5-users] Re: How to check ...
It's a regular inorder 5 stage pipeline model designed to mimic the microarchitectural states of actual C-class processor mentioned here. https://gitlab.com/shaktiproject/cores/c-class Has fetch, decode(modified), execute, memaccess, writeback connected through pipe like structures containing FIFOs, with operand forward. Working on BPU and Fault handling. Currently tested only with RISCV ISA in baremetal full system simulation. The model can be found here : https://gitlab.com/shaktiproject/tools/core-models-gem5 On Fri, 3 Jul, 2020, 4:07 AM Anuj Falcon, wrote: > How to know if my CPU model qualifies to be upstreamed with the rest of > the CPU models in gem 5 ? > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] How to check ...
How to know if my CPU model qualifies to be upstreamed with the rest of the CPU models in gem 5 ? ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Directly accessing certain regions of memory...
With the caches on, is there a way to define certain memory ranges for the CPU to directly access memory (Not through the L1 or L2) ? Can somebody provide any example on how to do that ? -- - J ANUJ - ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Regarding RISCV's Compressed conditional branching instructions
Sorry that I couldn't share the setup due to the complexity involved in sharing it. I am still working on it. Meanwhile, I tried running the same program on TimingSimpleCPU with BaremetalRISCV. It worked. So it looks like the error is with my CPU model. Sorry for posting a question without double-checking it. On Fri, Jun 5, 2020 at 8:57 PM Jason Lowe-Power wrote: > Hi Anuj, > > Does this result in incorrect execution? Could you give us a full example > of where this happens so we can reproduce it? > > Thanks, > Jason > > On Fri, Jun 5, 2020 at 8:07 AM Anuj Falcon via gem5-users < > gem5-users@gem5.org> wrote: > >> In RISCV, when the condition of the conditional compressed branching >> instruction is false, it's incrementing the PC value by 4 rather than 2. >> Has anyone faced this issue with RISCV ISA? If yes, how to go about it? >> >> -- >> >> - >> J ANUJ >> >> - >> ___ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-le...@gem5.org >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > > -- - J ANUJ - ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Regarding RISCV's Compressed conditional branching instructions
In RISCV, when the condition of the conditional compressed branching instruction is false, it's incrementing the PC value by 4 rather than 2. Has anyone faced this issue with RISCV ISA? If yes, how to go about it? -- - J ANUJ - ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
Re: [gem5-users] Running bare-metal RISCV simulations ...
I have attached the config script I developed and use for running baremetal
RISCV system.
Place the file at gem5/configs/example/riscv/
--
-
J ANUJ
-
#Author : Anuj J
from __future__ import print_function
from __future__ import absolute_import
import optparse
import sys
import m5
# from m5.defines import buildEnv
from m5.objects import *
from m5.util import addToPath #, fatal, warn
# from m5.util.fdthelper import *
addToPath('../../')
from ruby import Ruby
from common.FSConfig import *
# from common.SysPaths import *
# from common.Benchmarks import *
from common import Simulation
from common import CacheConfig
# from common import CpuConfig
# from common import MemConfig
# from common import ObjectList
from m5.objects import Cache
# from common.learning_gem5.part1.caches import *
from common import Options
from common import SimpleOpts
class L1Cache(Cache):
"""Simple L1 Cache with default values"""
assoc = 2
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
def __init__(self, options=None):
super(L1Cache, self).__init__()
pass
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
self.mem_side = bus.slave
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU-side port
This must be defined in a subclass"""
raise NotImplementedError
class L1ICache(L1Cache):
"""Simple L1 instruction cache with default values"""
# Set the default size
size = '16kB'
SimpleOpts.add_option('--l1i_size',
help="L1 instruction cache size. Default: %s" % size)
def __init__(self, opts=None):
super(L1ICache, self).__init__(opts)
if not opts or not opts.l1i_size:
return
self.size = opts.l1i_size
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU icache port"""
self.cpu_side = cpu.icache_port
class L1DCache(L1Cache):
"""Simple L1 data cache with default values"""
# Set the default size
size = '64kB'
SimpleOpts.add_option('--l1d_size',
help="L1 data cache size. Default: %s" % size)
def __init__(self, opts=None):
super(L1DCache, self).__init__(opts)
if not opts or not opts.l1d_size:
return
self.size = opts.l1d_size
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU dcache port"""
self.cpu_side = cpu.dcache_port
class L2Cache(Cache):
"""Simple L2 Cache with default values"""
# Default parameters
size = '256kB'
assoc = 8
tag_latency = 20
data_latency = 20
response_latency = 20
mshrs = 20
tgts_per_mshr = 12
SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
def __init__(self, opts=None):
super(L2Cache, self).__init__()
if not opts or not opts.l2_size:
return
self.size = opts.l2_size
def connectCPUSideBus(self, bus):
self.cpu_side = bus.master
def connectMemSideBus(self, bus):
self.mem_side = bus.slave
mulSgs = 2
divSgs = 32
SimpleOpts.add_option('--mul_stages', help="Number of multiplier stages. Default: %s" % mulSgs)
SimpleOpts.add_option('--div_stages', help="Number of divider stages. Default: %s" % divSgs)
# SimpleOpts.set_usage("usage: %prog [options] ")
(opts, args) = SimpleOpts.parse_args()
system = BareMetalRiscvSystem()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '2GHz'
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('2GB')]
system.membus = SystemXBar()
system.mem_ctrl = DDR3_1600_8x8()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
system.system_port = system.membus.slave
if opts and opts.mul_stages:
mulSgs = opts.mul_stages
if opts and opts.div_stages:
divSgs = opts.div_stages
system.cpu = ProtoCPU(divStages = divSgs, mulStages = mulSgs)
system.cpu.icache = L1ICache(opts)
system.cpu.dcache = L1DCache(opts)
system.cpu.icache.connectCPU(system.cpu)
system.cpu.dcache.connectCPU(system.cpu)
system.l2bus = L2XBar()
# Hook the CPU ports up to the l2bus
system.cpu.icache.connectBus(system.l2bus)
system.cpu.dcache.connectBus(system.l2bus)
# Create an L2 cache and connect it to the l2bus
system.l2cache = L2Cache(opts)
system.l2cache.connectCPUSideBus(system.l2bus)
# Connect the L2 cache to the membus
system.l2cache.connectMemSideBus(system.membus)
# system.cpu.icache_port = system.membus.slave
# system.cpu.dcache_port = system.membus.slave
system.cpu.createInterruptController()
system.bootloader = '/home/-/gem5/Test_components/a.out'
# system.kernel = '/home/-/gem5/Test_components/a.out'
[gem5-users] RISCV nop executed as c.addi...
c.addi instruction executes with zero immediate value, which is wrong according to ISA specification and it is the opcode for nop (0x0001 in hex). Can someone let me know why? -- - J ANUJ - ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Problem with system.membus unable to find destination error msg.
The *Unable to find destination for [Addr. Range] on system.membus *message doesn't appear when address bits 63:3 are set and results in a segmentation fault. All the other forms of addresses trigger the error message (except when address is within the memory range - which is normal.) Why is that ? -- - J ANUJ - ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Default stack pointer value...
What causes writeData() function in packet.hh to cause segmentation fault in the context of gem5? How to resolve this? - J ANUJ - ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] gem5 stable release proposal [PLEASE VOTE!]
I am happy for the efforts put in to make the GEM5 stable. "Developers can meddle. Please let the user have the pleasure of accessing stable version in main branch" "1 sounds late, 3 sounds obsessive, 2 is active. If possible make it 2 release per annum - just my opinion, discard if impossible" ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] gem5 build error with gcc-9.2.1
Though I switched back to gcc-7.4 to get the job done, I faced the error message below while building with gcc-9.2.1 in Ubuntu 19.10. In file included from build/RISCV/cpu/base.hh:64, from build/RISCV/kern/linux/events.cc:51: build/RISCV/sim/insttracer.hh: In member function 'void Trace::InstRecord::setData(VecRegContainer<8>&)': build/RISCV/sim/insttracer.hh:203:71: *error: implicitly-declared 'constexpr VecRegContainer<8>::VecRegContainer(const VecRegContainer<8>&)' is deprecated [-Werror=deprecated-copy]* 203 | data.as_vec = new ::VecRegContainer(d); -- - J ANUJ - ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] How to go about understanding the built-in functions provided for developing a CPU model from scratch.
I have been experimenting and going through the code base of TimingSimpleCPU and LearningSimpleCPU for about a month but still find it hard to understand the* built-in functionalities* provided (execContext, Memory request...) to get a bare minimum CPU model up in GEM5. For that matter, can anybody point me to any useful documentation or reference material ? And any tips on how to get started with CPU modelling in GEM5 would be greatly appreciated. Thank you! J Anuj Project Associate RISE Lab | CSE Department | IIT Madras - ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
