Re: [gem5-users] RISCV ISA : "C" (compressed) extension supported?

[Jason Lowe-Power]

Hi Marcelo,

For future reference, if someone else has this issue... Another possibility
is that the branch predictor is the problem. It looks like it could be
predicting that instruction is a branch. I'm not sure if it's specifically
because of the compressed format or not, though. It's another place for the
next person to start digging.

Cheers,
Jason

On Fri, May 25, 2018 at 8:20 AM Marcelo Brandalero 
wrote:

> Hi Jason, Alec,
>
> Just to provide some feedback on this issue, it seems that the processor
> is mistakenly identifying (add reg, reg, reg) in compressed format as a
> branch instruction.
>
> I'm running a kernel that looks like this (result from 
> *riscv64-unknown-elf-objdump
> -D*)
>
> 0001019a :
>   1019a:   06400793li  a5,100
>   1019e:   4701li  a4,0
>   101a0:   4681li  a3,0
>   101a2:   4601li  a2,0
>   101a4:   0c800513li  a0,200
>   101a8:   952aadd a0,a0,a0
>   101aa:   9632add a2,a2,a2
>   101ac:   96b6add a3,a3,a3
>   101ae:   973aadd a4,a4,a4
>
>
>
>
> *   101b0:   952aadd a0,a0,a0   101b2:
>   9632add a2,a2,a2   101b4:   96b6
>add a3,a3,a3   101b6:   973a
>add a4,a4,a4*(repeat the four instructions above
> until this:)
>   104b8:   952aadd a0,a0,a0
>   104ba:   9632add a2,a2,a2
>   104bc:   96b6add a3,a3,a3
>   104be:   973aadd a4,a4,a4
>   104c0:   952aadd a0,a0,a0
>   104c2:   2501sext.w  a0,a0
>   104c4:   9632add a2,a2,a2
>   104c6:   2601sext.w  a2,a2
>   104c8:   96b6add a3,a3,a3
>   104ca:   2681sext.w  a3,a3
>   104cc:   973aadd a4,a4,a4
>   104ce:   2701sext.w  a4,a4
>   104d0:   37fdaddiw   a5,a5,-1
>   104d2:   cc079be3bneza5,101a8 
>
> And what the Fetch stage looks like when fetching this code block is this:
>
> 4048968: system.cpu.fetch: [tid:0] Waking up from cache miss.
> 4048968: system.cpu.fetch: Running stage.
> 4048968: system.cpu.fetch: Attempting to fetch from [tid:0]
> 4048968: system.cpu.fetch: [tid:0]: Icache miss is complete.
> 4048968: system.cpu.fetch: [tid:0]: Adding instructions to queue to decode.
> 4048968: system.cpu.fetch: [tid:0]: Instruction PC 0x101a8 (0) created
> [sn:8124].
> 4048968: system.cpu.fetch: [tid:0]: Instruction is: c_add a0, a0, a0
> 4048968: system.cpu.fetch: [tid:0]: Fetch queue entry created (1/256).
> *4048968: system.cpu.fetch: Branch detected with PC =
> (0x101a8=>0x101aa).(0=>1)*
> 4048968: system.cpu.fetch: [tid:0]: Done fetching, predicted branch
> instruction encountered.
> 4048968: system.cpu.fetch: [tid:0][sn:8124]: Sending instruction to decode
> from fetch queue. Fetch queue size: 1.
> 4049281: system.cpu.fetch: Running stage.
> 4049281: system.cpu.fetch: Attempting to fetch from [tid:0]
> 4049281: system.cpu.fetch: [tid:0]: Adding instructions to queue to decode.
> 4049281: system.cpu.fetch: [tid:0]: Instruction PC 0x101aa (0) created
> [sn:8125].
> 4049281: system.cpu.fetch: [tid:0]: Instruction is: c_add a2, a2, a2
> 4049281: system.cpu.fetch: [tid:0]: Fetch queue entry created (1/256).
> *4049281: system.cpu.fetch: Branch detected with PC =
> (0x101aa=>0x101ac).(0=>1)*
> 4049281: system.cpu.fetch: [tid:0]: Done fetching, predicted branch
> instruction encountered.
> 4049281: system.cpu.fetch: [tid:0][sn:8125]: Sending instruction to decode
> from fetch queue. Fetch queue size: 1.
> 4049594: system.cpu.fetch: Running stage.
> 4049594: system.cpu.fetch: Attempting to fetch from [tid:0]
> 4049594: system.cpu.fetch: [tid:0]: Adding instructions to queue to decode.
> 4049594: system.cpu.fetch: [tid:0]: Instruction PC 0x101ac (0) created
> [sn:8126].
> 4049594: system.cpu.fetch: [tid:0]: Instruction is: c_add a3, a3, a3
> 4049594: system.cpu.fetch: [tid:0]: Fetch queue entry created (1/256).
> *4049594: system.cpu.fetch: Branch detected with PC =
> (0x101ac=>0x101ae).(0=>1)*
> 4049594: system.cpu.fetch: [tid:0]: Done fetching, predicted branch
> instruction encountered.
> 4049594: system.cpu.fetch: [tid:0][sn:8126]: Sending instruction to decode
> from fetch queue. Fetch queue size: 1.
> 4049907: system.cpu.fetch: Running stage.
> 4049907: system.cpu.fetch: Attempting to fetch from [tid:0]
> 4049907: system.cpu.fetch: [tid:0]: Adding instructions to queue to decode.
> 4049907: system.cpu.fetch: [tid:0]: Instruction PC 0x101ae (0) created
> [sn:8127].
> 

Re: [gem5-users] RISCV ISA : "C" (compressed) extension supported?

[Marcelo Brandalero]

Hi Jason, Alec,

Just to provide some feedback on this issue, it seems that the processor is
mistakenly identifying (add reg, reg, reg) in compressed format as a branch
instruction.

I'm running a kernel that looks like this (result from
*riscv64-unknown-elf-objdump
-D*)

0001019a :
  1019a:   06400793li  a5,100
  1019e:   4701li  a4,0
  101a0:   4681li  a3,0
  101a2:   4601li  a2,0
  101a4:   0c800513li  a0,200
  101a8:   952aadd a0,a0,a0
  101aa:   9632add a2,a2,a2
  101ac:   96b6add a3,a3,a3
  101ae:   973aadd a4,a4,a4




*   101b0:   952aadd a0,a0,a0   101b2:
  9632add a2,a2,a2   101b4:   96b6
   add a3,a3,a3   101b6:   973a
   add a4,a4,a4*(repeat the four instructions above
until this:)
  104b8:   952aadd a0,a0,a0
  104ba:   9632add a2,a2,a2
  104bc:   96b6add a3,a3,a3
  104be:   973aadd a4,a4,a4
  104c0:   952aadd a0,a0,a0
  104c2:   2501sext.w  a0,a0
  104c4:   9632add a2,a2,a2
  104c6:   2601sext.w  a2,a2
  104c8:   96b6add a3,a3,a3
  104ca:   2681sext.w  a3,a3
  104cc:   973aadd a4,a4,a4
  104ce:   2701sext.w  a4,a4
  104d0:   37fdaddiw   a5,a5,-1
  104d2:   cc079be3bneza5,101a8 

And what the Fetch stage looks like when fetching this code block is this:

4048968: system.cpu.fetch: [tid:0] Waking up from cache miss.
4048968: system.cpu.fetch: Running stage.
4048968: system.cpu.fetch: Attempting to fetch from [tid:0]
4048968: system.cpu.fetch: [tid:0]: Icache miss is complete.
4048968: system.cpu.fetch: [tid:0]: Adding instructions to queue to decode.
4048968: system.cpu.fetch: [tid:0]: Instruction PC 0x101a8 (0) created
[sn:8124].
4048968: system.cpu.fetch: [tid:0]: Instruction is: c_add a0, a0, a0
4048968: system.cpu.fetch: [tid:0]: Fetch queue entry created (1/256).
*4048968: system.cpu.fetch: Branch detected with PC =
(0x101a8=>0x101aa).(0=>1)*
4048968: system.cpu.fetch: [tid:0]: Done fetching, predicted branch
instruction encountered.
4048968: system.cpu.fetch: [tid:0][sn:8124]: Sending instruction to decode
from fetch queue. Fetch queue size: 1.
4049281: system.cpu.fetch: Running stage.
4049281: system.cpu.fetch: Attempting to fetch from [tid:0]
4049281: system.cpu.fetch: [tid:0]: Adding instructions to queue to decode.
4049281: system.cpu.fetch: [tid:0]: Instruction PC 0x101aa (0) created
[sn:8125].
4049281: system.cpu.fetch: [tid:0]: Instruction is: c_add a2, a2, a2
4049281: system.cpu.fetch: [tid:0]: Fetch queue entry created (1/256).
*4049281: system.cpu.fetch: Branch detected with PC =
(0x101aa=>0x101ac).(0=>1)*
4049281: system.cpu.fetch: [tid:0]: Done fetching, predicted branch
instruction encountered.
4049281: system.cpu.fetch: [tid:0][sn:8125]: Sending instruction to decode
from fetch queue. Fetch queue size: 1.
4049594: system.cpu.fetch: Running stage.
4049594: system.cpu.fetch: Attempting to fetch from [tid:0]
4049594: system.cpu.fetch: [tid:0]: Adding instructions to queue to decode.
4049594: system.cpu.fetch: [tid:0]: Instruction PC 0x101ac (0) created
[sn:8126].
4049594: system.cpu.fetch: [tid:0]: Instruction is: c_add a3, a3, a3
4049594: system.cpu.fetch: [tid:0]: Fetch queue entry created (1/256).
*4049594: system.cpu.fetch: Branch detected with PC =
(0x101ac=>0x101ae).(0=>1)*
4049594: system.cpu.fetch: [tid:0]: Done fetching, predicted branch
instruction encountered.
4049594: system.cpu.fetch: [tid:0][sn:8126]: Sending instruction to decode
from fetch queue. Fetch queue size: 1.
4049907: system.cpu.fetch: Running stage.
4049907: system.cpu.fetch: Attempting to fetch from [tid:0]
4049907: system.cpu.fetch: [tid:0]: Adding instructions to queue to decode.
4049907: system.cpu.fetch: [tid:0]: Instruction PC 0x101ae (0) created
[sn:8127].
4049907: system.cpu.fetch: [tid:0]: Instruction is: c_add a4, a4, a4
4049907: system.cpu.fetch: [tid:0]: Fetch queue entry created (1/256).
*4049907: system.cpu.fetch: Branch detected with PC =
(0x101ae=>0x101b0).(0=>1)*
4049907: system.cpu.fetch: [tid:0]: Done fetching, predicted branch
instruction encountered.
4049907: system.cpu.fetch: [tid:0][sn:8127]: Sending instruction to decode
from fetch queue. Fetch queue size: 1.
4050220: system.cpu.fetch: Running stage.
4050220: system.cpu.fetch: Attempting to fetch from [tid:0]
4050220: system.cpu.fetch: [tid:0]: Adding instructions to queue to decode.
4050220: 

Re: [gem5-users] RISCV ISA : "C" (compressed) extension supported?

[Marcelo Brandalero]

 Hi Jason, Alec,

Thanks for the fast responses!

I can say I managed to run a lot of benchmarks on O3 and none of them
crashed. I did notice however that their performance on for distinct-width
O3 processors had only minor differences (on x86, the differences were much
more significant).

I ran into this particular issue only today, though, so I can only say it
*seems* *to affect only binaries compíled with C extensions*.

I'll run the tests suggested by both of you and reply here in case I find
anything interesting.

Best regards,


On Thu, May 24, 2018 at 9:29 PM, Marcelo Brandalero 
wrote:

> Hi Jason, Alec,
>
> Thanks for the fast responses!
>
> I can say I managed to run a lot of benchmarks on O3 and none of them
> crashed. I did notice however that their performance on for distinct-width
> O3 processors had only minor differences (on x86, the differences were much
> more significant).
>
> I ran into this particular issue only today, though, so I can only say it
> *seems* *to affect only binaries compíled with C extensions*.
>
> I'll run the tests suggested and reply here in case I find anything
> interesting.
>
> Best regards,
>
> On Thu, May 24, 2018 at 9:06 PM, Alec Roelke  wrote:
>
>> Hi Marcelo,
>>
>> Yes, gem5 does support the C extension (64-bit version only, though).  I
>> don't know what could be causing your particular issue.  I'm not sure
>> advancePC is the issue, though, because all that essentially does is call
>> PCState::advance(), which is inherited unchanged from
>> GenericISA::UPCState.  Try doing as Jason suggests and run your simulation
>> with the Fetch debug flag enabled, and maybe that will shed some light on
>> the issue.
>>
>> -Alec
>>
>> On Thu, May 24, 2018 at 7:20 PM, Jason Lowe-Power 
>> wrote:
>>
>>> Hi Marcelo,
>>>
>>> I'm not sure if RISC-V has been tested with the out of order CPU at all!
>>> I'm happy that at least it doesn't completely fail!
>>>
>>> For you problem of only fetching 1 instruction per cycle... I think it's
>>> going to take some digging. My first guess would be that it could be a
>>> problem with the advancePC() function that's implemented in the RISC-V
>>> decoder (in gem5/arch/riscv), but I don't really have any specific reason
>>> to think that :).
>>>
>>> You could try turning on some debug flags for the O3 CPU. Specifically,
>>> Fetch might be helpful.
>>>
>>> Cheers,
>>> Jason
>>>
>>> On Thu, May 24, 2018 at 4:06 PM Marcelo Brandalero <
>>> mbrandal...@inf.ufrgs.br> wrote:
>>>
 Hi all,

 I recently switched from gem5/x86 to gem5/RISCV due to some advantages
 of this ISA.

 I'm getting some weird simulation results and I realized my compiler
 was generating instructions for the compressed RISCV ISA extension (chp
 12 in the user level ISA specification
 ). The weirdness disappears when I
 use *--march* to remove these extensions.

 *So the question is: does gem5/RISCV support this ISA extension? *If
 so, I can share the weird results (maybe I'm missing something) but
 basically a wide-issue O3 processor fetches only max 1 instruction/cycle
 when it should probably be fetching more.

 If it doesn't support then it's all OK, I just find it a bit weird that
 the program executes normally with no warnings whatsoever.

 Best regards,

 --
 Marcelo Brandalero
 PhD Candidate
 Programa de Pós Graduação em Computação
 Universidade Federal do Rio Grande do Sul
 ___
 gem5-users mailing list
 gem5-users@gem5.org
 http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>>
>>>
>>
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
>
>
> --
> Marcelo Brandalero
>



-- 
Marcelo Brandalero
PhD Candidate
Programa de Pós Graduação em Computação
Universidade Federal do Rio Grande do Sul
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Re: [gem5-users] RISCV ISA : "C" (compressed) extension supported?

[Alec Roelke]

Hi Marcelo,

Yes, gem5 does support the C extension (64-bit version only, though).  I
don't know what could be causing your particular issue.  I'm not sure
advancePC is the issue, though, because all that essentially does is call
PCState::advance(), which is inherited unchanged from
GenericISA::UPCState.  Try doing as Jason suggests and run your simulation
with the Fetch debug flag enabled, and maybe that will shed some light on
the issue.

-Alec

On Thu, May 24, 2018 at 7:20 PM, Jason Lowe-Power 
wrote:

> Hi Marcelo,
>
> I'm not sure if RISC-V has been tested with the out of order CPU at all!
> I'm happy that at least it doesn't completely fail!
>
> For you problem of only fetching 1 instruction per cycle... I think it's
> going to take some digging. My first guess would be that it could be a
> problem with the advancePC() function that's implemented in the RISC-V
> decoder (in gem5/arch/riscv), but I don't really have any specific reason
> to think that :).
>
> You could try turning on some debug flags for the O3 CPU. Specifically,
> Fetch might be helpful.
>
> Cheers,
> Jason
>
> On Thu, May 24, 2018 at 4:06 PM Marcelo Brandalero <
> mbrandal...@inf.ufrgs.br> wrote:
>
>> Hi all,
>>
>> I recently switched from gem5/x86 to gem5/RISCV due to some advantages of
>> this ISA.
>>
>> I'm getting some weird simulation results and I realized my compiler was
>> generating instructions for the compressed RISCV ISA extension (chp 12
>> in the user level ISA specification ).
>> The weirdness disappears when I use *--march* to remove these extensions.
>>
>> *So the question is: does gem5/RISCV support this ISA extension? *If so,
>> I can share the weird results (maybe I'm missing something) but basically a
>> wide-issue O3 processor fetches only max 1 instruction/cycle when it should
>> probably be fetching more.
>>
>> If it doesn't support then it's all OK, I just find it a bit weird that
>> the program executes normally with no warnings whatsoever.
>>
>> Best regards,
>>
>> --
>> Marcelo Brandalero
>> PhD Candidate
>> Programa de Pós Graduação em Computação
>> Universidade Federal do Rio Grande do Sul
>> ___
>> gem5-users mailing list
>> gem5-users@gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
>
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Re: [gem5-users] RISCV ISA : "C" (compressed) extension supported?

[Jason Lowe-Power]

Hi Marcelo,

I'm not sure if RISC-V has been tested with the out of order CPU at all!
I'm happy that at least it doesn't completely fail!

For you problem of only fetching 1 instruction per cycle... I think it's
going to take some digging. My first guess would be that it could be a
problem with the advancePC() function that's implemented in the RISC-V
decoder (in gem5/arch/riscv), but I don't really have any specific reason
to think that :).

You could try turning on some debug flags for the O3 CPU. Specifically,
Fetch might be helpful.

Cheers,
Jason

On Thu, May 24, 2018 at 4:06 PM Marcelo Brandalero 
wrote:

> Hi all,
>
> I recently switched from gem5/x86 to gem5/RISCV due to some advantages of
> this ISA.
>
> I'm getting some weird simulation results and I realized my compiler was
> generating instructions for the compressed RISCV ISA extension (chp 12 in
> the user level ISA specification ).
> The weirdness disappears when I use *--march* to remove these extensions.
>
> *So the question is: does gem5/RISCV support this ISA extension? *If so,
> I can share the weird results (maybe I'm missing something) but basically a
> wide-issue O3 processor fetches only max 1 instruction/cycle when it should
> probably be fetching more.
>
> If it doesn't support then it's all OK, I just find it a bit weird that
> the program executes normally with no warnings whatsoever.
>
> Best regards,
>
> --
> Marcelo Brandalero
> PhD Candidate
> Programa de Pós Graduação em Computação
> Universidade Federal do Rio Grande do Sul
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
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[gem5-users] RISCV ISA : "C" (compressed) extension supported?

[Marcelo Brandalero]

Hi all,

I recently switched from gem5/x86 to gem5/RISCV due to some advantages of
this ISA.

I'm getting some weird simulation results and I realized my compiler was
generating instructions for the compressed RISCV ISA extension (chp 12 in
the user level ISA specification ). The
weirdness disappears when I use *--march* to remove these extensions.

*So the question is: does gem5/RISCV support this ISA extension? *If so, I
can share the weird results (maybe I'm missing something) but basically a
wide-issue O3 processor fetches only max 1 instruction/cycle when it should
probably be fetching more.

If it doesn't support then it's all OK, I just find it a bit weird that the
program executes normally with no warnings whatsoever.

Best regards,

-- 
Marcelo Brandalero
PhD Candidate
Programa de Pós Graduação em Computação
Universidade Federal do Rio Grande do Sul
___
gem5-users mailing list
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