Hi all,
I am looking into simulating some multithreaded benchmarks in se mode. I
compiled m5threads both for x86 and arm. Running binaries linked to
m5threads works fine natively, as well as when simulating a processor in
the atomic model. However, when simulating an* out-of-order detailed model *
These patches "fix" the problem. However, they may not apply cleanly to
HEAD and they definitely are not cleanly implemented.
https://gem5-review.googlesource.com/c/public/gem5/+/7362
https://gem5-review.googlesource.com/c/public/gem5/+/7361
Cheers,
Jason
On Wed, Feb 7, 2018 at 8:49 PM Da Zhang
Hi Varun,
Some comments inline below.
On Tue, Feb 6, 2018 at 11:33 PM Saivarun R wrote:
> Hi Jason,
>
> As you pointed out, I went through the dram_ctrl.cc file and spent some
> time designing the implementation. I want to know if what I understood is
> correct regarding the implementation or n
See
https://gem5.googlesource.com/public/gem5/+/master/configs/common/MemConfig.py#135
for
an example of using interleaved ranges.
One thing to keep in mind is that if you use the same bits for interleaving
as indexing the cache you will be artificially constraining the size of
your cache. (E.g.,
Dear all,
I am having following error while using the Garnet 2.0 network.
build/ARM/mem/ruby/network/MessageBuffer.cc:220: Tick
MessageBuffer::dequeue(Tick, bool): Assertion `isReady(current_time)'
failed.
and core dumped.
I am using following system
./build/ARM/gem5.fast configs/example/fs.p
Hi Jason,
The batch you provided works! I was able to run linux kernel v4.8.13 with
ubuntu 16.04.1 with the latest gem5 applying the patch. Sorry that I am new
to use these patches, and didn't apply it in a correct way.
Thanks a lot.
best,
Da
On Fri, Feb 2, 2018 at 4:20 PM, Da Zhang wrote:
> I
Hi Jason
The package works (I used the second one)! And it also works with the
package you provided (
https://gem5-review.googlesource.com/c/public/gem5/+/7301) in my another
email to fix the keyboard and mouse issue for running later linux kernel
and ubuntu. (However, there are some conflicts in
Hi Jason,
Thank you for the your help. I will work on that.
Thank you
Varun
On Thu, Feb 8, 2018 at 10:39 PM, Jason Lowe-Power
wrote:
> Hi Varun,
>
> Some comments inline below.
>
> On Tue, Feb 6, 2018 at 11:33 PM Saivarun R wrote:
>
>> Hi Jason,
>>
>> As you pointed out, I went through the dr
Dear, all.
According to below link,
http://repo.gem5.org/gem5?cmd=changeset;node=17b37f38944a
DDR4_2400_8x8 uses a 8-bit width device and 8 devices are in a rank.
My doubt is the below.
DDR4_2400_8x8 class is overriding DDR4_2400_16x4 class in DRAMCtrl.py
However, the devices_per_rank is still
