On Sun, 12 May 2024 16:23:33 -0500
mikeegg1 via "Users help list for gnucap." wrote:
> How do I test gnu cap to make sure it’s ok and functioning properly?
There is a README file in "tests" that explains how to run the test
suite.
> When I run gnu cap on a single file in the tests directory I
Also posting to the devel list. This thread really should be there,
because it is developer related.
On Thu, 31 Mar 2022 16:47:33 +0200 (CEST)
k...@aspodata.se wrote:
> > Not sure what you mean. What is a top module?
>
>
On Fri, 25 Mar 2022 22:43:14 +0100 (CET)
k...@aspodata.se wrote:
> Would something like this suffice ?
Actually, no, but it's a start.
>
> $ lepton-netlist -g verilog arm_can_test.sch
> $ head -30 output.net
> /* structural Verilog generated by lepton-netlist */
> /* WARNING: This is a
On Fri, 25 Mar 2022 21:14:30 +0100 (CET)
k...@aspodata.se wrote:
> That repo is a little strange, I get this:
>.
> It seems it consists of a few non-connected branches.
That repo is for any plugins except models, trying to avoid setting up
a new repo for every new set of plugins.
On Wed, 2 Feb 2022 18:52:55 +0100 (CET)
k...@aspodata.se wrote:
> If it just me, I'd just edit the files to suit my system.
That's what I would do.
In your case, it looks like the problem was that libtermcap was not
installed properly. I link was missing.
>
> But your message makes me ask:
>
On Mon, 20 Apr 2020 08:43:55 +0200
patrick wrote:
> module m(1,2);
>^ ? need 4 more nodes
>
...
> Surely I am missing some things... anyway thanks for your help.
>
I think it's in spice mode .. expecting spice syntax.
In spice syntax, a line beginning with 'm' is a mosfet
On Fri, 14 Feb 2020 10:52:12 +0100
Matthias Brennwald wrote:
> I have your PDF documentation from 2006, which I found on Google. Can you
> point me to the documentation of the current Gnucap version?
From that Google search, any link except that one will lead you to
something more recent. The
On Thu, 7 Sep 2017 11:15:36 -0500
Edgar Ricardo Perdomo Ayala wrote:
> what am I doing wrong?
You didn't say what version or anything like that, but the list
postings you refer to are about 9 years old. A lot has happened since
then.
This is the latest "release".
On Tue, 4 Apr 2017 22:59:15 -0600
alan somers wrote:
> Yep, that diff fixes the build with the default link order.
Thanks .. now I need to think about how to really fix it.
It has to do with the order that destructors are run in .. It's the
reverse of the order of
On Wed, 5 Apr 2017 00:38:36 -0400
al davis <ad...@freeelectron.net> wrote:
> I have an idea, but I will need you to test it.
Try commenting out lines 54 and 55 of l_dispatcher.h .
~DISPATCHER_BASE() {
#if !defined(NDEBUG)
for (typename std::map<std::string, CKT_BASE
On Tue, 4 Apr 2017 21:44:11 -0600
alan somers wrote:
> @@#
> @@@unreachable:../../include/l_dispatcher.h:41:DISPATCHER_BASE
> build error: link order: constructing dispatcher that already has contents
>
> gmake[1]: *** [Makefile:129: d_mos1.cc] Segmentation fault
> gmake[1]:
On Sun, 2 Apr 2017 23:01:54 -0600
alan somers wrote:
> The gmake issue isn't too bad. Lots of software needs gmake when
> built on FreeBSD. The bigger problem is that gnucap requires GCC.
It shouldn't.
The default compiler in the configure scripts should be c++. I will
On Tue, 13 Sep 2016 14:37:52 +0200
Felix Salfelder wrote:
> On Tue, Sep 13, 2016 at 10:03:51PM +1000, Richard Gipps wrote:
> > VCC 10 0 PULSE(0 8)
>
> there seems to be a problem with the time zero value of that pulse
> try "VCC 10 0 PULSE(0 8 1p)" instead. maybe "(0 8 0
On Tue, 13 Sep 2016 22:03:51 +1000
Richard Gipps wrote:
> Gnucap 2009.12.07 RCS 26.136
> zero time step
> newtime=1.00e-12 rejectedtime=1.00e-12 oldtime=0.00e+00
> non-recoverable user requested
> newtime=1.00e-12 rejectedtime=2.00e-12
On Mon, 05 Sep 2016 15:01:29 +0200
Orestes Mas wrote:
> Is there any simple way to find the voltage between two arbitrary nodes?
The easiest way is to put a component in the circuit, and ask for its
voltage. Or .. there is probably one there already.
Iprobe (4 5) 0
For more info on how measures work, see the manual ..
http://gnucap.org/dokuwiki/doku.php?id=gnucap:manual:commands:measure
On Tue, 23 Aug 2016 13:31:21 -0500
John Griessen wrote:
> How do you print x if it is not a function of time? If it is just a single
> number,
>
On Fri, 22 Jul 2016 17:07:51 -0500
John Griessen wrote:
> and gnucap says, "non-recoverable convergence failure, reducing (itl4)
> newtime=3.30e-05 rejectedtime=3.30e-05
> oldtime=3.30e-05 using=3.30e-05 tried everything, still
> doesn't work, giving up"
On Saturday 20 June 2015, wikitronic wrote:
I'm trying to compile with the default plugins staticly
linked.I keep getting the error:
build error: link order: dispatcher not yet constructed
It has to do with the order of running static constructors.
Static constructors are run in the order
On Monday 15 June 2015, d...@eefficiencysolutions.com wrote:
That is the instance name XD is used twice for two different
instances. The whole circuit works well despite what I think
is an error.
Is this intended behaviour or should this fail to compile?
Intended behaviour.
Just curious
On Monday 16 March 2015, Orestes Mas wrote:
I'm trying to adapt a PSpice macromodel of AD8541 OpAmp.
Luckily enough, I've been able to translate nearly every
POLY controlled source into a form suitable for GnuCap,
mainly by splitting the POLY source into several normal
sources as the
On Sunday 26 May 2013, Orestes Mas wrote:
I must confess I'm a bit lost here, due to the fact I'm not
aware of some simulator internals.
One practical use of UIC is for circuits that have several
metastable states, preventing convergence.
I know that to do transient simulations one must
On Saturday 25 May 2013, Orestes Mas wrote:
All elements are in series, so clearly I(Vg)=-I(L1)
But instead, the first output value of I(Vg) is -900kA, and
should be zero. Current through the inductor is OK.
This does not happen if UIC is removed from TRAN command.
Why? Are voltage
On Wednesday 22 May 2013, Orestes Mas wrote:
I'm obtaining unexpected results (NaN) when simulating a
simple circuit:
Try adding a line .
/* */
void DEV_RESISTANCE::precalc_last()
{
ELEMENT::precalc_last();
_y[0].f1 = (value() != 0.)
On Wednesday 22 May 2013, Orestes Mas wrote:
If soo, why not do an OP analysis automatically before every
AC one? If I remember correctly, this is precisely what
spice does...
In this case .. there is a bug that causes a divide by zero on a
zero-ohm resistor, with a simple fix. (Does this
On Thursday 25 April 2013, Felix Salfelder wrote:
On Thu, Apr 25, 2013 at 08:03:20PM -0400, al davis wrote:
didn't work for me.
What didn't work?
g++ -DUNIX -O2 -DNDEBUG -I. -I../include -I../../include -W mg_main.o
mg_error.o mg_in.o mg_out_h.o mg_out_dump.o mg_out_common.o
On Thursday 25 April 2013, Felix Salfelder wrote:
Installation (still make install) installs the parts as
expected. It also installs the header files in
$PREFIX/include/gnucap, to build plugins.
didn't work for me.
What didn't work?
Although it does not use autoconf, the
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2013-04-23.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2013-04-23-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2013-04-23-models-jspice3-2.5.tar.gz
On Sunday 07 April 2013, Karl Hammar wrote:
I get different volt calculated vs. measured in node 2 of
simulation below. Can anyone point to where my mistake is?
It should be 0.5 V for 50 Ohm input impedance but only
measures to less than 200 mV. Replacing circuit 50 Ohm BNC
terminator gives
On Monday 07 January 2013, Romain GAILLETON wrote:
95% of the computing times seem to come from the LU operation
according to the status command.
I am running Gnucap on Windows using the last available
version (2009) So I tried to run it on Linux using the 0.35
version but the improvement
,
I'll ponder it further.) On Feb 7, 2012 6:11 PM, al davis
ad...@freeelectron.net wrote:
It's not the number of nodes, but rather how they are ordered.
In this case, the ideal ordering would produce a tridiagonal
matrix, which can be solved in linear time. Gnucap's solver
does solve
On Sunday 15 January 2012, Paul Reichl wrote:
I am fairly new to gnucap and spice and I have a question
regarding the use of subcircuits and the solution times
when using them. I have a circuit network with about 500 or
so sets of either; R and L, R, L and C, or R, L, C and
I, elements in
On Friday 22 July 2011, Ramiro Aceves wrote:
On gnucap: 0.719 seconds
Same circuit on QUCS: 65 seconds.
I do not understand why there is such tremendous time
difference. Same stop time, same step size. Gnucap goodness
or Qucs badness
I knew Qucs was slow on large circuits, but that
On Wednesday 20 July 2011, Ramiro Aceves wrote:
I have made it work following your guidelines. I have done
the following, not sure if it is the right way to compile
only the modules required, not the full set of modules:
Compile only the modules required.
That's the point of plugins.
If you
On Tuesday 19 July 2011, Ramiro Aceves wrote:
I have a convergence problem:
Quick answer, based on experience, so I can give you an
immediate response ..
Convergence problems are often tied to the model used.
You are using the old modelgen BJT model, which will be phased
out.
Try instead to
On Thursday 10 February 2011, Orestes Mas wrote:
I'm facing a weird result when I simulate a simple inverter
amplifier built around an operational amplifier. Basically
I'm trying to obtain the input- output transfer
characteristic (for educational purposes), but if the number
of points in
On Wednesday 22 September 2010, Jasper wrote:
Thanks for both of your suggestions for trying NGspice. I did
but so far it has not been a success. Under OSX the PZ
analysis segfaults. Under my Ubuntu Virtualbox it works
somewhat. I can obtain the correct pole-zero values for up
to 3 RL element
On Friday 30 July 2010, al davis wrote:
On Friday 30 July 2010, Stefan Dröge wrote:
Hi, I just tried to set the value of an VCVS by using an
expression, but can't get it to work.
Here I what I want to do:
If Input voltage Vin -5mV then Vout := 0V
If Vin 5mV then Vout := 5V
On Friday 30 July 2010, Stefan Dröge wrote:
Hi, I just tried to set the value of an VCVS by using an
expression, but can't get it to work.
Here I what I want to do:
If Input voltage Vin -5mV then Vout := 0V
If Vin 5mV then Vout := 5V
else (Vin between -5mV and 5mV) linear interpolated
On Wednesday 14 July 2010, Felix Salfelder wrote:
in gnucap netlists its possible to hand bm_* expressions to
elements, like for example
gvcr out 0 vcr in 0 poly( 1, 2, 3 ).
i'm having trouble adding such devices into a .model file.
for now i'm copying code from bm_poly.cc to the eval
Sorry about the delay .. At first I was travelling, then had a
pile of stuff waiting .. and the answer to this one isn't
simple. I will try to address the issues one at a time,
hopefully in a manner that is useful.
1. Geda / gschem / gnetlist.
This combo really doesn't work as well as it
On Wednesday 30 June 2010, Philipp Klaus Krause wrote:
I'm rather new to gnucap, so this could be a user error, but:
I've seen the following problem three times:
gnucap just outputs lots of
@@@unreachable:u_limit.h:110:fet_limit_vgs messages (and a
R1.X1: RTEMP: effective length is negative
On Wednesday 30 June 2010, Josef Vukovic wrote:
I have a question reagrdig my gnucap simulation of a pure
inductance.
Here is my gnucap code:
Pure Inductance:
V 1 0 sin(0 220 50)
L 1 0 100m ic=0V
.print tran v(1) i(L)
.tran .001 .02 AcXl.dat uic
.end
When I plot the
On Monday 08 February 2010, Mike wrote:
I am trying to get a simple circuit working that incorporates
a JJ, but I cannot get the simulation to produce a simple IV
curve. Is there some documentation on how to implement the
JJ? Is it the same as the Jspice JJ? Could someone please
send me an
On Monday 01 March 2010, Rubén Gómez Antolí wrote:
Sorry about repeat topic, but I'd fall in a nightmare with
this circuit and his evolution.
If is possible that there are a fail in design because I
haven't correct output of buck chopper (1.5 V instead 1V,
Ngspice runs circuit :-/ ),
On Friday 05 February 2010, Rubén Gómez Antolí wrote:
1· Problems with params:
gnucap param periodo=50us
gnucap param llano=0.7*periodo
param llano=0.7*periodo
^ ? syntax error
According to wiki page (0) are correct, but fails.
For now, put it in quotes, as Hspice
On Sunday 13 December 2009, Ivan Reche wrote:
I know its kinda off, but I don't have anywhere else to ask:
Is it possible to use gwave with gnucap? I've tried here,
but gwave wouldn't display correctly the waveforms. For now,
I'm using gnuplot, but it is not convenient.
With gwave, I get
On Friday 11 December 2009, Thiago de Paiva wrote:
I want to put, at same place, current and voltage graph.
Current is much smaller then voltage, then I want to
multiply the value of current by 50, because this way I can
see both as well as. Is there a manner to do it directly
from gnucap
On Wednesday 02 December 2009, Rubén Gómez Antolí wrote:
I think that I miss something using measure command.
I follow Gnucap's wiki manual:
http://gnucap.org/dokuwiki/doku.php?id=gnucap:manual:commands:measure
I want to get the RMS value of a signal in a circuit, for it
I do:
gnucap
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-11-10.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2009-11-10-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2009-11-10-models-jspice3-2.5.tar.gz
On Saturday 17 October 2009, Rubén Gómez Antolí wrote:
I need to specify different phases in sources in this way:
I1 phase=-10 freq=60
I2 phase=150 freq=180
I3 phase=-56 freq=300
SIN sources not admit phase option.
I try with generator function:
.gen ampl=10 phase=-10 freq=60
I1 n1
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-09-28.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2009-09-28-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2009-09-28-models-jspice3-2.5.tar.gz
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-09-22.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2009-09-22-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2009-09-22-models-jspice3-2.5.tar.gz
On Friday 11 September 2009, asom...@gmail.com wrote:
It says that in section 1.4: Command Structure. On my
system, it's at:
file:///usr/share/doc/gnucap/html/gnucap-man006.html#htoc5
That's the old manual, for the old stable version. (0.35??)
There are a lot of changes in the
On Thursday 10 September 2009, asom...@gmail.com wrote:
I'm having a little trouble getting inline comments to work.
According to the manual, Anything on any line following a
quote is ignored.. But the manual doesn't say whether to
use single or double quotes.
Where does it say that?
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-09-09.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2009-09-09-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2009-09-09-models-jspice3-2.5.tar.gz
On Sunday 23 August 2009, vsrk sarma wrote:
I did have gcc installed:gcc (Ubuntu 4.3.3-5ubuntu4) 4.3.3
I tried to configure with latest snapshot version dated
2009-08-19. problem continues still.
config.log file is attached.
Gnucap needs a C++ compiler, not C.
sudo apt-get install g++
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-08-22.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2009-08-22-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2009-08-22-models-jspice3-2.5.tar.gz
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-08-19.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2009-08-19-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2009-08-19-models-jspice3-2.5.tar.gz
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-08-13.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2009-08-13-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2009-08-13-models-jspice3-2.5.tar.gz
Minor revision control error .. try again.
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-07-23.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2009-07-23-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2009-07-23-models-jspice3-2.5.tar.gz
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-07-21.tar.gz
Optional plugin files:
http://gnucap.org/devel/gnucap-2009-07-21-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2009-07-21-models-jspice3-2.5.tar.gz
On Saturday 18 July 2009, cliffnotes wrote:
It would be nice to support 1 non-alphanumeric character to
allow us to allow us a hook for our tool to do some advanced
things. It can be an @ or | or whatever, but # is a
character that I believe I have seen in the past used legally
in several
On Friday 17 July 2009, ram342 wrote:
Does gnucap support using hash symbol (#) in variable name.
Hspice supports such an usage .does a similar thing exist in
gnucap?
I never thought about it. From a quick check, apparently it
works in node names and device names, but there is a problem in
On Thursday 16 July 2009, John Griessen wrote:
fall = last specifies only the first swing and not the
swings after that.
No, in this case, last just means last one in program
execution order, not in the time scale.
Last does mean last in time.
cross finds a crossing .. If there are many,
On Wednesday 15 July 2009, Seshadri V wrote:
I would like to know if there is some way to measure settling
time of an underdamped system( ringing output) in gnucap.
AFAIK, there is no direct way measuring the number of ringing
before the output reaches a steady state output. Because the
On Thursday 02 July 2009, Leandro Marsó wrote:
can anyone give me a hint about how could I make a testbench
to attack a circuit with a sequence of bits?
Can you explain?
PWL source?
___
Help-gnucap mailing list
Help-gnucap@gnu.org
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-06-11.tar.gz
Optional plugin files:
No source changes, so you can use the old source,
but you do need to recompile
http://gnucap.org/devel/gnucap-2009-06-11-models-bsim.tar.gz
On Thursday 19 March 2009, Thomas Ibbotson wrote:
The voltage controlled switch represents the electrical
breakdown above a voltage of 5KV. This circuit works quite
well in reproducing what we see experimentally. However,
there are artifacts caused by the fact that the switch
changes
On Wednesday 04 March 2009, Aurelio Cano wrote:
Well, I want to build a current controlled resistor using the
voltage controlled resistor circuit.
First I establish a linear relationship between the input
voltage and the resistor through a table (1V-1k,
2V-2k,...).
Then, I put a current
On Monday 09 February 2009, John Griessen wrote:
So, next I'm going to try spice mode to enter a vsource.
Is that the way to do it now? If so, should I keep in spice
mode and follow an example of spice simulation to do a run?
As you know, there is incomplete work there.
If you need something
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2009-02-02.tar.gz
Optional plugin files:
No source changes, so you can use the old source,
but you do need to recompile
http://gnucap.org/devel/gnucap-2009-02-02-models-bsim.tar.gz
On Tuesday 27 January 2009, John Griessen wrote:
I am attempting to follow
http://wiki.gnucap.org/dokuwiki/doku.php?id=gnucap:languages:
verilog
I make a file with contents of the illustrated netlist and
top level instances:
The I input it to gnucap 2008.12.03 RCS 26.105
On Tuesday 27 January 2009, John Griessen wrote:
What would it be like to change the verilog-ams input
parsing? What kind of version control methods do you use for
dealing with volunteer code patches? Will you point me to
the place to look in the code?
The verilog code is in lang_verilog*.
Look here:
http://wiki.gnucap.org/dokuwiki/doku.php?id=gnucap:languages:verilog
On Monday 26 January 2009, John Griessen wrote:
module verilog_io (GND ,OUT ,IN );
capacitor #(.c(1250e-9) ) C1 ( .p(B), .n(GND));
inductor #(.l(.001) ) L1 ( .n(OUT), .p(B));
resistor #(.r(1000) ) R1
On Sunday 25 January 2009, John Griessen wrote:
How do I connect a gnucap internal capacitor model to this
netlist generated by gnetlist -g verilog?
some things don't work yet.
/* structural Verilog generated by gnetlist */
/* WARNING: This is a generated file, edits */
/* made here
On Sunday 25 January 2009, John Griessen wrote:
Thanks Al,
Is there a way to alias other names to a built in model?
Such as alias cap to capacitor?
The manual says, 3.2.1 Syntax
Device
.capacitor label n+ n– expression
Where do you use this? Is label for a name you give it?
What can
On Sunday 25 January 2009, John Griessen wrote:
.
/* Package instantiations */
cap #(.value(1250e-9) ) C1 ( .p(B), .n(GND));
In the verilog-ams the pos and neg terminals can be out of
order.
That's what names are for. If you name the terminals, you can
put them in any order.
What are
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2008-12-12.tar.gz
Optional plugin files:
There are some changes, so get these too:
http://gnucap.org/devel/gnucap-2008-12-12-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2008-12-12-models-jspice3-2.5.tar.gz
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2008-12-03.tar.gz
Optional plugin files:
There are some changes, so get these too:
http://gnucap.org/devel/gnucap-2008-12-03-models-bsim.tar.gz
http://gnucap.org/devel/gnucap-2008-12-03-models-jspice3-2.5.tar.gz
On Monday 20 October 2008, a r wrote:
Is it possible to postprocess AC simulation results? I'd like
to be able to write something like:
.print ac db20(v(node1)/v(node2)) phase(v(node1)/v(node2))
.ac dec 20 1 1G ac.out
This is not just AC specific question but AC analysis makes
it slightly
On Thursday 28 August 2008, Jesus Genicio wrote:
Vcc ( 1 0 ) DC 5.
Vin ( 5 0 ) PULSE iv= 0. pv= 5. delay= 1. rise= 0. fall= 0.
width= 2. period= 4.
Rc ( 1 8 ) 122.
Rb ( 5 2 ) 12.K
Rled ( 8 3 ) 121.
Q1 ( 3 2 0 ) Q2N2219A area= 1.
The result is correct:
gnucap tran 0 2 0.1
#Time
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2008-07-23.tar.gz
Optional plugin files are not changed except for version number
but here's a set with consistent numbering.
http://gnucap.org/devel/gnucap-2008-07-23-models-bsim.tar.gz
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2008-07-10.tar.gz
Optional plugin files are not changed except for version number
but here's a set with consistent numbering.
http://gnucap.org/devel/gnucap-2008-07-10-models-bsim.tar.gz
On Tuesday 08 July 2008, Johannes Bauer wrote:
What am I doing wrong?
I don't know.
What commands did you use?
___
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Help-gnucap@gnu.org
http://lists.gnu.org/mailman/listinfo/help-gnucap
On Wednesday 09 July 2008, Johannes Bauer wrote:
Now I wanted to use a diode, for example. However I have to
specify a model as a value - now one really silly question
is: How do I find out what models are available for diodes? I
tried some standard values like 1N4001 and 1N914 none of
which
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2008-07-07.tar.gz
Optional plugin files are not changed except for version number
but here's a set with consistent numbering.
http://gnucap.org/devel/gnucap-2008-07-07-models-bsim.tar.gz
There is a new development snapshot available ...
http://gnucap.org/devel/gnucap-2008-06-19.tar.gz
Optional plugin files are not changed except for version number
but here's a set with consistent numbering.
http://gnucap.org/devel/gnucap-2008-06-19-models-bsim.tar.gz
On Tuesday 11 March 2008, Rubén Gómez Antolí wrote:
In other machine with a new gnucap snapshot installation:
[EMAIL PROTECTED]:~/Fuentes/gnucap-2008-02-11$ gnucap -a
models-ngspice17/asrc/asrc.so prueba.ckt
Gnucap 2008.02.10 RCS 26.71
The Gnu Circuit Analysis Package
Never trust any
On Tuesday 11 March 2008, Rubén Gómez Antolí wrote:
Hello all,
I have a question and a problem around attach model.
There are some known bugs.
Plugin attachment is not in its final form. It will change
before the stable release. There is some question of
how it should work. Your comments
On Friday 22 February 2008 12:43, Mark Beal wrote:
When I use numerical values for PD and PS on the gnucap BSIM
transistor models, I get a reasonable result. When I use parameters,
I also get the same results, except for the PD and PS parameters.
I've attached a simple inverter test case to
On Tuesday 19 February 2008, a r wrote:
On Feb 19, 2008 6:19 AM, al davis [EMAIL PROTECTED]
wrote:
If there are no storage elements, there is no truncation
error, but there is still activity, and step control is
still needed.
I agree it doesn't work well in every case but for most
On Tuesday 19 February 2008, a r wrote:
I have different experiences - a realistic circuit model
usually makes the simulation easier. This is especially
visible in extracted simulations. It's not that I am so big
fan of LTE. If you can come up with something better - that's
great. But for the
On Tuesday 19 February 2008, a r wrote:
gnucap: ../Gnucap/e_elemnt.h:150: double
ELEMENT::dampdiff(double*, const double): Assertion `*v0 ==
*v0' failed.
probably a numeric overflow or divide by zero.
On Tuesday 19 February 2008, a r wrote:
in code:
.subckt inv vdd vss out in
.parameter
On Tuesday 19 February 2008, a r wrote:
One more feature request. Any chance of getting default
subcircuit parameters working? These are pretty ubiquitous,
at least in my designs.
List them as params ,,
.subckt ..
.param .
What you pass in will override.
Or, where is the
On Monday 18 February 2008, a r wrote:
What I expect from good time step control is (conceptually)
simple:
1. Adjust time step so that local truncation error is
constant (slightly less than specified value),
2. Limit time step to such value that numerical instability
will not occur.
In
On Monday 18 February 2008, a r wrote:
On Feb 18, 2008 8:58 PM, al davis [EMAIL PROTECTED]
wrote:
Truncation error step control for Euler always gives very
small steps, significantly smaller than the steps used for
trap.
Sure, truncation errors will be larger (that's Euler after
all
On Saturday 16 February 2008, a r wrote:
bm_pulse still generates a distorted waveform. On 3/12/2007
I've posted a corrected version of the tr_eval function that
does not suffer from this problem. To be honest, it's a bit
disappointing - I understand you may have a problem testing
all the
There is a new snapshot available ...
http://www.gnucap.org/devel/gnucap-2008-02-11.tar.gz
Models (optional) have also been updated, only to change a
directory name:
http://www.gnucap.org/devel/gnucap-2008-02-11-models-bsim.tar.gz
On Monday 03 December 2007, a r wrote:
I have a feeling that M parameter does not work for neither
bsim devices (attached) nor subcircuits.
This is only based on observations - I haven't yet looked
into the code.
It works for some devices, not the Spice models, unless they did
it. The
On Thursday 29 November 2007, Chinasaur wrote:
At the moment the only analyses I need to run are operating
points. The task is, given a network of cells with resistive
connections between them, get the operating points under a
series of stationary, stochastic input currents.
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