Hi
We would like to categorize the channels as in the Mainframe Concept book
(http://publib.boulder.ibm.com/infocenter/zos/basics/index.jsp?topic=/com.ibm.zos.znetwork/znetwork_74.htm)
CCW channel or Coupling channel or QDIO/OSA.
Can I make this from the channel type codes ?
Miklos Szigetvari pisze:
Hi
We would like to categorize the channels as in the Mainframe Concept book
(http://publib.boulder.ibm.com/infocenter/zos/basics/index.jsp?topic=/com.ibm.zos.znetwork/znetwork_74.htm)
CCW channel or Coupling channel or QDIO/OSA.
Can I make this from the
On 9/15/2010 10:57 AM, R.S. wrote:
Miklos Szigetvari pisze:
Hi
We would like to categorize the channels as in the Mainframe Concept
book
(http://publib.boulder.ibm.com/infocenter/zos/basics/index.jsp?topic=/com.ibm.zos.znetwork/znetwork_74.htm)
CCW channel or Coupling channel or
Miklos,
By the disk I assume you mean the volume. How can you figure out how busy
a volume is?
RMF does not report how busy a FICON channel is, only the FICON Channel MP.
What is the tool that reports FCP Channel busy and LUN busy on other
platforms.
Ron
-Original Message-
From:
Mike,
The volumes you are referring to would have to have a different size (3390-9
or larger) for MSR to make a difference, and the CU/DASD in the storage
formatted as RAMAC (3390-3R) for availability to make a difference. If these
things are not different then columns 3 to 7 will not make a
Hi
On 9/15/2010 12:24 PM, Ron Hawkins wrote:
Miklos,
By the disk I assume you mean the volume. How can you figure out how busy
a volume is?
Not a volume, the complete system, all the DISK channel's
(if we can figure out this)
RMF does not report how busy a FICON channel is, only the
On Tue, 14 Sep 2010 09:35:51 -0700, Charles Mills charl...@mcn.org
wrote:
I can't get it to work, sadly. You had me real encouraged.
//FOO PROC M=''
// SET Q=
// SET P=Q.M.Q
//STEP1 EXEC PGM=IEFBR14,PARM=Q.P.Q
...
//STEP2 EXEC FOO,M='Life isn''t fair'
Gives me a JCL error IEFC629I
Tobias,
The reason you are not seeing the expected savings is that the IDCAMS REPRO
has already set and used the optimal number of data buffers regardless of
the DATACLAS change (so, no change has actually taken place; optimal
buffering was used for both before and after runs).
You should see
This thread has gone on and on in the usual way, with posters talking at cross
purposes.
I do not wish to trivialize Peter Relson's comment, but one interpretation of
what he said that seems to me to be at once reasonable, helpful, and consistent
with his words is just that
1) an amode(24)
In 3fd1837f9564834ab2063f30e2b2c...@mail.cenhud.com, on 09/14/2010
at 03:56 PM, Tim Brown tbr...@cenhud.com said:
Now we are seeing it for DD statements for output files. These had
been grandfathered since many programmers always replicated someone
elses JCL, and so on and so on... (Dont touch
In
6b34aedeeb35274e81437a445900b2d7934...@hdqsrvexcvs.ssfcuad.ssfcu.org,
on 09/14/2010
at 05:22 PM, Ward, Mike S mw...@ssfcu.org said:
Hello all, I have a question. I was talking with someone that said
you don't need OSA's to run tcpip under z/os and use it to
communicate with the outside
At 14:22 -0400 on 09/14/2010, George Henke wrote about Re: z/OS V1.12
differences and z196 (the new mainframe) imp:
Which compromises the entire purpose of the SAVE/RESTORE Register Convention
which has been held sacred since the beginning of S/360, PCP, and/or S
cubed.
If the 64-bit
Mike,
Ron is correct about the broken vtoc index messing up the free space info
that SMS tracks and changing MSR will not have any effect. If you have
an automation tool, I recommend having it issue a v sms command to
put the volume in disable for new allocations whenever a vtoc disabled
message
Has anyone converted from Quick Index back to regular IDCAMS
processing? We only have about 12 jobs actually using QI and would like
to eliminate it.
Thanks.
Doug Fuerst
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Ah. VQI. Makes me yearn for the old days at Softworks. A great company
with some great people! I did very little work on VQI during my long tenure
a Softworks, but I am very familiar with it. When IDCAMS was updated to use
the internal house sort (back in 91, 92 ??), the need for VQI really
Technically true, I suppose, but what's the point? OSA's come pretty much as
standard equipment these days.
-Original Message-
From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of
Ward, Mike S
Sent: Tuesday, September 14, 2010 5:22 PM
To:
So if I had OMEGAMON and OMEGAVIEW in the same CSI with different TZONEs and
DZONEs and specified XZGROUP and XZREQ parms, the PTF that went on OMEGAMON
would have also been applied to OMEGAVIEW and I would have avoided the
ensuing OC4 and having to apply it twice.
I have no specific knowledge
On Wed, 15 Sep 2010 08:00:07 -0400, Robert A. Rosenberg wrote:
If the 64-bit program calling the 24/31 bit program wants to insure
the integrity of the high end of the registers, it is ITS
responsibility to save them around the call.
That is incorrect. As clearly documented in the Assembler
On Wed, 15 Sep 2010 08:00:07 -0400 Robert A. Rosenberg hal9...@panix.com
wrote:
:At 14:22 -0400 on 09/14/2010, George Henke wrote about Re: z/OS V1.12
:differences and z196 (the new mainframe) imp:
:Which compromises the entire purpose of the SAVE/RESTORE Register Convention
:which has been
On Tue, 14 Sep 2010 13:38:15 -0500, Mike Schwab wrote:
On Tue, Sep 14, 2010 at 12:15 PM, Tony Harminc wrote:
deleted
Well, we had this discussion at great length a few years ago... The
pre-existing 24- or 31-bit program that's been running for many years
now gets called by a 64-bit program,
Some years ago, in pursuit of Headcount reduction, a decision was made to
suppress the
display of WTORs that weren't recognized by automation (OPS/MVS) as important.
This
had the desired effect, and headcount reduction proceeded. In the years since
then,
the remaining operators have learned
I think we need to know what the real issue with the question is in regard to
OSA's TCP, etc.
There are several ways to 'skin the cat' to do external TCPIP networking,
OSA's
and CISCO CIPS are the ones that I thnk folks are familiar with nowdays.
So Mike to answer thwe question you dont need
In listserv%201009141022331100.0...@bama.ua.edu, on 09/14/2010
at 10:22 AM, Paul Gilmartin paulgboul...@aim.com said:
Ah, semantics! Can a program run in AMODE(24/31) in OS/390 (in a
supported configuration) and use grande registers?
Yes. You might want to ask a different question.
--
In 1284416005.6627.39.ca...@mckown5.johnmckown.net, on 09/13/2010
at 05:13 PM, John McKown joa...@swbell.net said:
Is that like OS/360 PCP?
The original options in OS/360 were option 1, SSS, opption 2, MSS and
option 4, MPS. SSS became PCP, MSS became MFT and MPS became VMS[1],
then MVT. MFT
On Tue, 14 Sep 2010 15:00:23 -0400, Sabo, Frank
frank.s...@gianteagle.com wrote:
Good afternoon everyone,
Question does any one out there have an EMC DLM box?
I have been trying to get one up and functional for a while now.
I have genned the box to both HCD and SMS the problem that I am having
Ron,
I was expecting results similiar to the ones I saw in VSAM Demystified.
Instead of using Repro, I'll write something to do my testing. We will be
using
Dataset Striping and I am interested in putting them together.
Tob
Yifat,
Without any other specification, such as BUFSP at define or BFND on the
REPRO, IDCAMS without SMB used to default to BUFND of two, and only read one
CI at a time.
Are you saying the default changed, or changed for Extended Format?
I suggested it would not make huge difference for REPRO
I like it, reminds me of an old Python sketch:
Option 3: There is NOOO option 3!
-Original Message-
From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On
Behalf Of Shmuel Metz (Seymour J.)
Sent: September 14, 2010 2:02 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Issuing
kopplin wrote:
Some years ago, in pursuit of Headcount reduction, a decision was made to
suppress the display of WTORs that weren't recognized by automation
(OPS/MVS) as important. This had the desired effect, and headcount
reduction proceeded. In the years since then, the remaining operators
Ron,
The defaults have changed;
This is not the best pointer, but it's all I could find with a quick search
http://www-01.ibm.com/support/docview.wss?uid=isg1OA01898: With OW51451,
REPRO uses AMDCIPCA (CI per CA) value for BUFND when SHROPT is not 4.
Such buffering (BUFND=CI/CA) will make a
Miklos,
Figuring out how busy all the channel processors are on the Host is easy. It
is reported in the Type 73 RMF record for the LPAR and the CEC. This does
not tell you how busy the channel is. A FICON Express Four channel maxes out
at approx 14,000 normal IOPS, but the FICON channel itself
Yeah, but just think of the money saved by the head reduction. Isn't that
wonderful.
-Original Message-
From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On Behalf Of
kopplin
Sent: Wednesday, September 15, 2010 11:04 AM
To: IBM-MAIN@bama.ua.edu
Subject: A most curious
Tobias,
I'm a great fan of RAID-0 datasets (dataset striping) and the benefits of
LSR buffering.
They are two very different things though, and if you would like to
understand the benefit of each technique you may want to measure them
separately.
Data Set striping does two things. It flattens
Where do the general register values (reported under CPU STATUS in
IPCS) come from when a SLIP IF with ACTION=SVCD takes a dump? I have
had no reason to distrust these values in the past, but now I have
such a dump where some of the values are impossible for the PSW
address, while others are
You could try a 2216. I may have one in my garage holding up some other
junk g. OSA is really the way to go these days. In addition to TCPIP
communications, with the proper OSA card and configuration, you can even use
then for console support and eliminate those incredibly expensive OS/2
At 09:46 -0500 on 09/15/2010, Tom Marchant wrote about Re: z/OS V1.12
differences and z196 (the new mainframe) imp:
On Wed, 15 Sep 2010 08:00:07 -0400, Robert A. Rosenberg wrote:
If the 64-bit program calling the 24/31 bit program wants to insure
the integrity of the high end of the
On Tue, Sep 14, 2010 at 10:23 PM, John McKown joa...@swbell.net wrote:
Is there some magic to make LE dump the full 64 bit general registers
when CALL'ing CEE3DMP from an Enterprise COBOL 3.2 program? Yes, I know
COBOL doesn't use the high fullword of the regs. Something, somewhere,
is
-Original Message-
From: IBM Mainframe Discussion List
[mailto:ibm-m...@bama.ua.edu] On Behalf Of zMan
Sent: Wednesday, September 15, 2010 11:47 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: LE dump - CEE3DMP of 64 bit registers
On Tue, Sep 14, 2010 at 10:23 PM, John McKown
Yifat,
Thanks for that info.
So it was OW51451 that changed the default for REPRO, and it was a long time
ago. I need to get out in the real world more...
For a load on small to medium sized files I still don't think it will make
much of a difference for elapsed time or CPU, unless you have
Tony,
I don't have a dump in front of me to check this for sure, but I believe
field CVTSDBF points to an area where the contents of the registers at the time
of dump are formatted. I know there is a pointer in the CVT to such and area,
as I had the same problem some time back. I should
On Wed, 15 Sep 2010 13:28:19 -0400, Tony Harminc t...@harminc.net
wrote:
Where do the general register values (reported under CPU STATUS in
IPCS) come from when a SLIP IF with ACTION=SVCD takes a dump?
Hi Tony,
Not answering your actual question but I assume you want the active regs at
the
Where do the general register values (reported under CPU STATUS in
IPCS) come from when a SLIP IF with ACTION=SVCD takes a dump? I have
had no reason to distrust these values in the past, but now I have
such a dump where some of the values are impossible for the PSW
address, while others are
On 9/15/2010 10:46 AM, zMan wrote:
On Tue, Sep 14, 2010 at 10:23 PM, John McKownjoa...@swbell.net wrote:
Is there some magic to make LE dump the full 64 bit general registers
when CALL'ing CEE3DMP from an Enterprise COBOL 3.2 program? Yes, I know
COBOL doesn't use the high fullword of the
On 9/15/2010 10:59 AM, McKown, John wrote:
-Original Message-
From: IBM Mainframe Discussion List
[mailto:ibm-m...@bama.ua.edu] On Behalf Of zMan
Sent: Wednesday, September 15, 2010 11:47 AM
To: IBM-MAIN@bama.ua.edu
Subject: Re: LE dump - CEE3DMP of 64 bit registers
On Tue, Sep 14, 2010
This is where I was getting an S0C4-38 in ICEF64A. I think that have found the
problem. However, I cannot do anything about it due to the fact that it is, I
believe, in a OEM product which we have a perpetual license for, and so did not
renew maintenance on it. I.e. we are unsupported. It
Yes, I know CEE3DMP does continue after dumping. Now, back to my original
question. How to get CEE3DMP to dump the 64-bit registers?!? It doesn't matter
anyway, I wrote a smallish HLASM program to dump them using WTO. I was too lazy
to OPEN, SNAPX, CLOSE to put the data out to a DD.
--
John
W dniu 2010-09-15 19:35, Stan Weyman pisze:
You could try a 2216. I may have one in my garage holding up some other
junkg. OSA is really the way to go these days.
Agreed. While OSA alternatives are still available none of them is
reasonable.
In addition to TCPIP communications, with
One has to wonder how you are managing to hose your VTOC index datasets often
enough for you to raise the issue here.
On the other had, since indexing is a requirement for an SMS volume, how is it
that SMS is even considering an index-disabled volume for a new allocation?
-Original
Is there any reason why you shouldn't have alot of initiators defined, but have
alot of them drained. Is there any performance considerations?
Thanks
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-Original Message-
From: IBM Mainframe Discussion List
[mailto:ibm-m...@bama.ua.edu] On Behalf Of gsg
Sent: Wednesday, September 15, 2010 2:56 PM
To: IBM-MAIN@bama.ua.edu
Subject: Initiators
Is there any reason why you shouldn't have alot of initiators
defined, but have
alot
On Wed, 15 Sep 2010 13:10:37 -0400, Robert A. Rosenberg wrote:
At 09:46 -0500 on 09/15/2010, Tom Marchant wrote about Re: z/OS V1.12
differences and z196 (the new mainframe) imp:
On Wed, 15 Sep 2010 08:00:07 -0400, Robert A. Rosenberg wrote:
If the 64-bit program calling the 24/31 bit program
-Original Message-
From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On
Behalf Of gsg
Sent: Wednesday, September 15, 2010 2:56 PM
To: IBM-MAIN@bama.ua.edu
Subject: Initiators
Is there any reason why you shouldn't have alot of initiators defined,
but have
alot of them
This is just a follow on to another thread.
For information on LE dumps and 64-bit registers. See:
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/CEEA11B0/CHANGES.
1
which documents the enhancement,
Language Environment can now display the contents of high registers, if
Wouldn't you be better served by putting the initiators under WLM control? Then
you would have as many initiators as you need without over committing CPU.
Thank You,
Dave O'Brien
NIH Contractor
From: McKown, John [john.mck...@healthmarkets.com]
Sent:
Why not just put them under WLM control, and then the system controls
how many you use (up to your set limits)? This is much easier than
manually stopping and starting initiators, and it takes the control away
from operators who usually do not understand the impact starting too
many initiators
On Wed, 15 Sep 2010 16:06:55 -0400, Thompson, Steve wrote:
Each initiator, drained or running, takes up room in the SQA for ASCBs
and such.
An address space is created when the initiator is started. When the
initiator is drained the address space ends. There is no ASCB for a
drained
Thanks everyone for your replies. We haven't started using WLM YET, but I'll
look into it.
Thanks again.
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-Original Message-
From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On
Behalf Of Tom Marchant
Sent: Wednesday, September 15, 2010 3:42 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: Initiators
On Wed, 15 Sep 2010 16:06:55 -0400, Thompson, Steve wrote:
Each initiator, drained
On 9/9/2010 4:35 PM, Chris Craddock wrote:
yeah I know, I just didn't feel like going off on one of my normal rants
about integrity exposures. It seems like nobody listens anyway.
Some of us do... :-)
--
Edward E Jaffe
Phoenix Software International, Inc
831 Parkview Drive North
El Segundo,
Is it my imagination or have a number of B2xx opcodes been deleted from
the latest PoPs instruction tables?
I use those tables to keep my own personnal disassembler up-to-date.
Rick
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On 9/9/2010 4:35 PM, Chris Craddock wrote:
yeah I know, I just didn't feel like going off on one of my normal
rants
about integrity exposures. It seems like nobody listens anyway.
and on 9/15/2010 Ed Jaffe wrote:
Some of us do... :-)
Yep. When Chris speaks I listen. Usually it is
On 15 September 2010 14:51, Jim Mulder d10j...@us.ibm.com wrote:
For a SLIP dump, STATUS CPU REGS obtains the registers and PSW
from the SLIP section in the dump header record.
Well...
These should be
the registers and PSW from the event (in your case, a PER IF event)
which caused the
-Original Message-
From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On
Behalf Of Rick Fochtman
Sent: Wednesday, September 15, 2010 5:57 PM
To: IBM-MAIN@bama.ua.edu
Subject: PoPs
Is it my imagination or have a number of B2xx opcodes been deleted from
the latest
Wouldn't you be better served by putting the initiators under WLM control?
Then you would have as many initiators as you need without over committing CPU.
1: WLM managed inits are not a panacea.
2: Undisciplined operators can still wreak havoc.
-
I'm a SuperHero with neither powers, nor
Why not just put them under WLM control, and then the system controls
how many you use (up to your set limits)? This is much easier than manually
stopping and starting initiators, and it takes the control away
from operators who usually do not understand the impact starting too many
initiators
On Wed, 2010-09-15 at 14:21 -0500, McKown, John wrote:
Yes, I know CEE3DMP does continue after dumping. Now, back to my original
question. How to get CEE3DMP to dump the 64-bit registers?!? It doesn't
matter anyway, I wrote a smallish HLASM program to dump them using WTO. I was
too lazy to
Jim Mulder z/OS System Test IBM Corp. Poughkeepsie, NY
IBM Mainframe Discussion List IBM-MAIN@bama.ua.edu wrote on 09/15/2010
06:44:22 PM:
For a SLIP dump, STATUS CPU REGS obtains the registers and PSW
from the SLIP section in the dump header record.
Well...
These should be
While I do recommend WLM-inits for many types of work, I don't recommend it
for all
types. While you can use JES commands to limit the max number of inits by
Jobclass,
WLM-inits work well for similar types of workloads. You can certainly have
multiple Service
Classes defined for WLM-inits, but
We have a customer that uses the same DSNs on two different systems in
the same sysplex, in different catalogs on different volumes. So
their DSNs are not ENQed across the sysplex causing problems on the
test system that shares volumes with another system.
On Wed, Sep 15, 2010 at 2:28 PM,
Hi Tobias,
Have you tried coding the ACCBIAS option on the DD that points to the output
file. Whether you specify System or SO, VSAM will use the Create Optimization
process (only on Repros). If you also include MSG=SMBBIAS you will see the
IEC161I 001(CO) -... in the Job Log
Then you will
2216s were used before, but as stated OSA now comes pretty much standard
Colin Pearce
-Original Message-
From: IBM Mainframe Discussion List [mailto:ibm-m...@bama.ua.edu] On
Behalf Of Hal Merritt
Sent: Wednesday, September 15, 2010 9:47 PM
To: IBM-MAIN@bama.ua.edu
Subject: Re: z/OS,
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