[Intel-gfx] [PATCH igt v2] igt/gem_ctx_switch: Exercise all engines at once

Just a small variant to apply a continuous context-switch load to all engines. v2: Adapt to for_each_physical_engine() and sane gem_context_create() Signed-off-by: Chris Wilson Cc: Antonio Argenziano --- tests/gem_ctx_switch.c | 79

Re: [Intel-gfx] [PATCH v2] drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array

On Wed, 28 Feb 2018, Manasi Navare wrote: > dp_rates[] array is a superset of all the link rates supported > by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate > to the set of link rates supported by sink. This patch adds this rate > to dp_rates[] array

Re: [Intel-gfx] [igt-dev] [PATCH igt 1/5] lib/dummyload: Avoid assertions in lowlevel spin constructor

On 02/28/2018 05:51 PM, Chris Wilson wrote: > __igt_spin_batch_new() may be used inside a background helper which is > competing against the GPU being reset. As such, we cannot even assert > that the spin->handle is busy immediately after submission as it may > have already been reset by another

Re: [Intel-gfx] [PATCH] drm/i915: Wedged engine mask makes more sense in hex

Quoting Tvrtko Ursulin (2018-02-28 17:18:44) > From: Tvrtko Ursulin > > In decimal its just a weird big number, while in hex can actually log > which engines were requested to be wedged. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris

Re: [Intel-gfx] [igt-dev] [PATCH igt 5/5] igt/gem_exec_fence: Exercise merging fences

Quoting Antonio Argenziano (2018-02-28 22:44:31) > On 28/02/18 07:51, Chris Wilson wrote: > > + igt_assert(!gem_bo_busy(fd, obj.handle)); > > + igt_assert_eq(sync_fence_status(all), > > + flags & HANG ? -EIO : SYNC_FENCE_OK); > > Do you get -EIO also if only one engine

Re: [Intel-gfx] [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

On 2/28/2018 11:29 PM, Oscar Mateo wrote: On 2/26/2018 9:49 PM, Sagar Arun Kamble wrote: On 2/27/2018 4:34 AM, Oscar Mateo wrote: On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote: On 2/23/2018 4:35 AM, Oscar Mateo wrote: + * We might have detected that some engines are fused off

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array

== Series Details == Series: drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array URL : https://patchwork.freedesktop.org/series/39165/ State : warning == Summary == Possible new issues: Test kms_chv_cursor_fail: Subgroup pipe-b-128x128-left-edge: pass

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915: Add an option to disable SAGV

== Series Details == Series: drm/i915: Add an option to disable SAGV URL : https://patchwork.freedesktop.org/series/39161/ State : warning == Summary == Possible new issues: Test kms_chv_cursor_fail: Subgroup pipe-b-256x256-bottom-edge: pass -> DMESG-WARN

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v11,1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

== Series Details == Series: series starting with [v11,1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset URL : https://patchwork.freedesktop.org/series/39176/ State : failure == Summary == Series 39176v1 series starting with [v11,1/6] drm/i915/guc: Rename guc_ggtt_offset to

[Intel-gfx] [PATCH] sna/uxa: Fix colormap handling at screen depth 30.

The various clut handling functions like a setup consistent with the x-screen color depth. Otherwise we observe improper sampling in the gamma tables at depth 30. Therefore replace hard-coded bitsPerRGB = 8 by actual bits per channel scrn->rgbBits. Also use this for call to xf86HandleColormaps().

[Intel-gfx] [PULL] drm-intel-fixes

Hi Dave, I have these same patches stashed since last week, but last week I wasn't confident that CI was happy with these ones so I decided to hold on. Now after running multiple times with and without the patches applied I see that it was only a fix on test case, which is now catching old bugs

[Intel-gfx] [PATCH v11 1/6] drm/i915/guc: Rename guc_ggtt_offset to intel_guc_ggtt_offset

GuC related exported functions should start with "intel_guc_" prefix and pass intel_guc as the first parameter since its GuC related. Current guc_ggtt_offset() failed to follow this code convention and this is a problem for future patches that needs to access intel_guc data to verify the GGTT

[Intel-gfx] [PATCH v11 5/6] drm/i915/guc: Check the locking status of GuC WOPCM registers

GuC WOPCM registers are write-once registers. Current driver code accesses these registers without checking the accessibility to these registers which will lead to unpredictable driver behaviors if these registers were touch by other components (such as faulty BIOS code). This patch moves the GuC

[Intel-gfx] [PATCH v11 4/6] drm/i915: Add HuC firmware size related restriction for Gen9 and CNL A0

On CNL A0 and Gen9, there's a hardware restriction that requires the available GuC WOPCM size to be larger than or equal to HuC firmware size. This patch adds new verification code to ensure the available GuC WOPCM size to be larger than or equal to HuC firmware size on both Gen9 and CNL A0. v6:

[Intel-gfx] [PATCH v11 2/6] drm/i915: Implement dynamic GuC WOPCM offset and size calculation

Hardware may have specific restrictions on GuC WOPCM offset and size. On Gen9, the value of the GuC WOPCM size register needs to be larger than the value of GuC WOPCM offset register + a Gen9 specific offset (144KB) for reserved GuC WOPCM. Fail to enforce such a restriction on GuC WOPCM size will

[Intel-gfx] [PATCH v11 3/6] drm/i915: Add support to return CNL specific reserved WOPCM size

CNL has its specific reserved GuC WOPCM size for RC6 and other hardware contexts. This patch updates the code to return CNL specific reserved GuC WOPCM size for RC6 and other hardware contexts so that the GuC WOPCM size can be calculated correctly for CNL. v9: - Created a new patch for these

[Intel-gfx] [PATCH v11 6/6] HAX Enable GuC Submission for CI

Signed-off-by: Jackie Li --- drivers/gpu/drm/i915/i915_params.c | 2 +- drivers/gpu/drm/i915/i915_params.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 08108ce..b49ae20

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Removed unused GuC parameters.

== Series Details == Series: drm/i915/guc: Removed unused GuC parameters. URL : https://patchwork.freedesktop.org/series/39154/ State : failure == Summary == Possible new issues: Test drv_missed_irq: pass -> SKIP (shard-apl) Test drv_selftest:

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Add and enable DP AUX CH mutex

On Wed, 2018-02-28 at 13:09 +0200, Ville Syrjälä wrote: > On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote: > > On Tue, 2018-02-27 at 23:34 +0200, Ville Syrjälä wrote: > > > On Tue, Feb 27, 2018 at 01:23:59PM -0800, José Roberto de Souza > > > wrote: > > > > When PSR/PSR2/GTC is enabled

Re: [Intel-gfx] [PATCH 4/5] drm/i915/frontbuffer: Remove early frontbuffer flush in prepare_plane_fb()

On Wed, 2018-02-28 at 22:38 +0200, Ville Syrjälä wrote: > On Wed, Feb 28, 2018 at 10:28:13PM +0200, Ville Syrjälä wrote: > > On Sat, Feb 24, 2018 at 03:24:55AM +, Pandiyan, Dhinakaran wrote: > > > > > > > > > > > > On Mon, 2018-02-19 at 10:07 +0100, Maarten Lankhorst wrote: > > > > Op

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array

== Series Details == Series: drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array URL : https://patchwork.freedesktop.org/series/39165/ State : success == Summary == Series 39165v1 drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array

Re: [Intel-gfx] [igt-dev] [PATCH igt 5/5] igt/gem_exec_fence: Exercise merging fences

On 28/02/18 07:51, Chris Wilson wrote: Execute the same batch on each engine and check that the composite fence across all engines completes only after the batch is completed on every engine. Signed-off-by: Chris Wilson LGTM. Reviewed-by: Antonio Argenziano

[Intel-gfx] [PATCH v2] drm/i915/dp: Add HBR3 rate (8.1 Gbps) to dp_rates array

dp_rates[] array is a superset of all the link rates supported by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate to the set of link rates supported by sink. This patch adds this rate to dp_rates[] array that gets used to populate the sink_rates[] array limited by max rate

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Wedged engine mask makes more sense in hex

== Series Details == Series: drm/i915: Wedged engine mask makes more sense in hex URL : https://patchwork.freedesktop.org/series/39147/ State : failure == Summary == Possible new issues: Test kms_draw_crc: Subgroup draw-method-xrgb-mmap-cpu-xtiled: skip

Re: [Intel-gfx] [PATCH] drm/i915/guc: Removed unused GuC parameters.

On 28/02/18 12:26, Michel Thierry wrote: On 28/02/18 10:42, Piotr Piórkowski wrote: In the i915 driver, there is a function, intel_guc_init_params(), which initializes the GuC parameter block which is passed into the GuC. There is parameter GUC_CTL_DEVICE_INFO with values GfxGtType and

Re: [Intel-gfx] [RFC] drm/i915/dp: move link rate arrays where they're used

On Wed, 28 Feb 2018, Manasi Navare wrote: > On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote: >> Localize link rate arrays by moving them to the functions where they're >> used. Further clarify the distinction between source and sink >> capabilities. Split

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add an option to disable SAGV

== Series Details == Series: drm/i915: Add an option to disable SAGV URL : https://patchwork.freedesktop.org/series/39161/ State : success == Summary == Series 39161v1 drm/i915: Add an option to disable SAGV https://patchwork.freedesktop.org/api/1.0/series/39161/revisions/1/mbox/

Re: [Intel-gfx] [RFC] drm/i915/dp: move link rate arrays where they're used

On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote: > Localize link rate arrays by moving them to the functions where they're > used. Further clarify the distinction between source and sink > capabilities. Split pre and post Haswell arrays, and get rid of the > array size arithmetics. Use

Re: [Intel-gfx] [RFC][PATCH 04/11] drm: Split the display info into static and dynamic parts

On Tue, Feb 27, 2018 at 7:56 AM, Ville Syrjala wrote: > From: Ville Syrjälä > > Currently we have a mix of static and dynamic information stored in > the display info structure. That makes it rather difficult to repopulate > the

Re: [Intel-gfx] [RFC] drm/i915/dp: move link rate arrays where they're used

On Tue, Feb 27, 2018 at 12:59:11PM +0200, Jani Nikula wrote: > Localize link rate arrays by moving them to the functions where they're > used. Further clarify the distinction between source and sink > capabilities. Split pre and post Haswell arrays, and get rid of the > array size arithmetics. Use

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Fix plane YCbCr->RGB conversion for GLK

On Wed, Feb 14, 2018 at 09:23:24PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > On GLK the plane CSC controls moved into the COLOR_CTL register. > Update the code to progam the YCbCr->RGB CSC mode correctly when > faced with an YCbCr framebuffer. > > The

[Intel-gfx] [PATCH v2] drm/i915: Add an option to disable SAGV

On Gen9 systems, with SAGV enabled, we have seen display corruption(screenshots attached in the bug) which eventually lead to a system hang. This happens when we have overlay plane and on enabling and disabling the overlay plane. When the system hangs, we do not have enough logs or information to

Re: [Intel-gfx] [PATCH 4/5] drm/i915/frontbuffer: Remove early frontbuffer flush in prepare_plane_fb()

On Wed, Feb 28, 2018 at 10:28:13PM +0200, Ville Syrjälä wrote: > On Sat, Feb 24, 2018 at 03:24:55AM +, Pandiyan, Dhinakaran wrote: > > > > > > > > On Mon, 2018-02-19 at 10:07 +0100, Maarten Lankhorst wrote: > > > Op 16-02-18 om 20:27 schreef Pandiyan, Dhinakaran: > > > > On Fri, 2018-02-16

[Intel-gfx] [PULL] drm-misc-next

Hi Dave, Here's this weeks pull, relatively small when you pull out the trivial fixes. drm-misc-next-2018-02-28: drm-misc-next for 4.17: UAPI Changes: Fix drm_color_ctm matrix docs to match usage and change the type to __u64 make it obvious (Ville) Core Changes: Check modifier with format

Re: [Intel-gfx] [PATCH 4/5] drm/i915/frontbuffer: Remove early frontbuffer flush in prepare_plane_fb()

On Sat, Feb 24, 2018 at 03:24:55AM +, Pandiyan, Dhinakaran wrote: > > > > On Mon, 2018-02-19 at 10:07 +0100, Maarten Lankhorst wrote: > > Op 16-02-18 om 20:27 schreef Pandiyan, Dhinakaran: > > > On Fri, 2018-02-16 at 08:55 +, Chris Wilson wrote: > > >> Quoting Dhinakaran Pandiyan

Re: [Intel-gfx] [PATCH] drm/i915/guc: Removed unused GuC parameters.

On 28/02/18 10:42, Piotr Piórkowski wrote: In the i915 driver, there is a function, intel_guc_init_params(), which initializes the GuC parameter block which is passed into the GuC. There is parameter GUC_CTL_DEVICE_INFO with values GfxGtType and GfxCoreFamily unused by GuC. This patch remove

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Move SST DP link retraining into the ->post_hotplug() hook

On Wed, 2018-02-28 at 11:57 -0800, Manasi Navare wrote: > On Wed, Feb 28, 2018 at 02:41:06PM -0500, Lyude Paul wrote: > > On Wed, 2018-02-28 at 11:27 -0800, Manasi Navare wrote: > > > On Wed, Feb 28, 2018 at 02:07:34PM -0500, Lyude Paul wrote: > > > > > > > > On Tue, 2018-02-27 at 23:17 -0800,

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Nuke intel_dp->channel_eq_status

On Thu, Jan 18, 2018 at 10:59:04PM -0800, Rodrigo Vivi wrote: > On Wed, Jan 17, 2018 at 07:21:48PM +, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > intel_dp->channel_eq_status is used in exactly one function, and we > > don't need it to persist between

Re: [Intel-gfx] [PATCH 04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers

On Thu, Feb 22, 2018 at 12:55:06AM -0300, Paulo Zanoni wrote: > Just use the hardcoded tables provided by our spec. > > v2: Rebase. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 86 > ++- > 1 file

Re: [Intel-gfx] [PATCH v3 05/10] pwm: add PWM mode to pwm_config()

On Wed, 28 Feb 2018, Thierry Reding wrote: > Anyone that needs something other than normal mode should use the new > atomic PWM API. At the risk of revealing my true ignorance, what is the new atomic PWM API? Where? Examples of how one would convert old code over to the

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Track whether the DP link is trained or not

On Wed, Jan 17, 2018 at 09:21:49PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > LSPCON likes to throw short HPDs during the enable seqeunce prior to the > link being trained. These obviously result in the channel CR/EQ check > failing and thus we schedule

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset

== Series Details == Series: drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset URL : https://patchwork.freedesktop.org/series/39129/ State : warning == Summary == Possible new issues: Test kms_chv_cursor_fail: Subgroup pipe-b-256x256-bottom-edge:

Re: [Intel-gfx] [PATCH 03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers

On Thu, Feb 22, 2018 at 12:55:05AM -0300, Paulo Zanoni wrote: > HDMI mode DPLL programming on ICL is the same as CNL, so just reuse > the CNL code. > > v2: > - Properly detect HDMI crtcs. > - Rebase after changes to the cnl function (clock * 1000). > > Signed-off-by: Paulo Zanoni

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Move SST DP link retraining into the ->post_hotplug() hook

On Wed, Feb 28, 2018 at 02:41:06PM -0500, Lyude Paul wrote: > On Wed, 2018-02-28 at 11:27 -0800, Manasi Navare wrote: > > On Wed, Feb 28, 2018 at 02:07:34PM -0500, Lyude Paul wrote: > > > > > > On Tue, 2018-02-27 at 23:17 -0800, Manasi Navare wrote: > > > > Ville, thanks for the patch and > > >

Re: [Intel-gfx] [PATCH v3 05/10] pwm: add PWM mode to pwm_config()

On Thu, Feb 22, 2018 at 02:01:16PM +0200, Claudiu Beznea wrote: > Add PWM mode to pwm_config() function. The drivers which uses pwm_config() > were adapted to this change. > > Signed-off-by: Claudiu Beznea > --- > arch/arm/mach-s3c24xx/mach-rx1950.c | 11

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Move SST DP link retraining into the ->post_hotplug() hook

On Wed, 2018-02-28 at 11:27 -0800, Manasi Navare wrote: > On Wed, Feb 28, 2018 at 02:07:34PM -0500, Lyude Paul wrote: > > > > On Tue, 2018-02-27 at 23:17 -0800, Manasi Navare wrote: > > > Ville, thanks for the patch and > > > Sorry for not being able to review this earlier. > > > Please find

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Move SST DP link retraining into the ->post_hotplug() hook

On Wed, Feb 28, 2018 at 02:07:34PM -0500, Lyude Paul wrote: > > On Tue, 2018-02-27 at 23:17 -0800, Manasi Navare wrote: > > Ville, thanks for the patch and > > Sorry for not being able to review this earlier. > > Please find some comments below: > > > > On Wed, Jan 31, 2018 at 03:27:10PM +0200,

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Removed unused GuC parameters.

== Series Details == Series: drm/i915/guc: Removed unused GuC parameters. URL : https://patchwork.freedesktop.org/series/39154/ State : success == Summary == Series 39154v1 drm/i915/guc: Removed unused GuC parameters. https://patchwork.freedesktop.org/api/1.0/series/39154/revisions/1/mbox/

Re: [Intel-gfx] [igt-dev] [PATCH igt 3/5] igt/gem_ctx_switch: Exercise all engines at once

On 28/02/18 07:51, Chris Wilson wrote: Just a small variant to apply a continuous context-switch load to all engines. --- tests/gem_ctx_switch.c | 83 ++ 1 file changed, 83 insertions(+) diff --git a/tests/gem_ctx_switch.c

Re: [Intel-gfx] [PATCH v2 3/5] drm/i915: Move SST DP link retraining into the ->post_hotplug() hook

On Tue, 2018-02-27 at 23:17 -0800, Manasi Navare wrote: > Ville, thanks for the patch and > Sorry for not being able to review this earlier. > Please find some comments below: > > On Wed, Jan 31, 2018 at 03:27:10PM +0200, Ville Syrjälä wrote: > > On Tue, Jan 30, 2018 at 06:16:59PM -0500, Lyude

Re: [Intel-gfx] [PATCH] drm/i915: Wedged engine mask makes more sense in hex

On 28/02/18 09:18, Tvrtko Ursulin wrote: From: Tvrtko Ursulin In decimal its just a weird big number, while in hex can actually log which engines were requested to be wedged. And IGT is not reading the hang reason in this case, so Reviewed-by: Michel Thierry

[Intel-gfx] [PATCH] drm/i915/guc: Removed unused GuC parameters.

In the i915 driver, there is a function, intel_guc_init_params(), which initializes the GuC parameter block which is passed into the GuC. There is parameter GUC_CTL_DEVICE_INFO with values GfxGtType and GfxCoreFamily unused by GuC. This patch remove GUC_CTL_DEVICE_INFO with GfxGtType and

Re: [Intel-gfx] [PATCH] drm/i915/dp: Add HBR3 rate (8.1 Gbps) to default rates array

On Wed, 28 Feb 2018, Manasi Navare wrote: > On Wed, Feb 28, 2018 at 11:05:24AM +0200, Jani Nikula wrote: >> On Tue, 27 Feb 2018, Manasi Navare wrote: >> > default_rates[] array is a superset of all the link rates supported >> > by sink

Re: [Intel-gfx] [PATCH] drm/i915/perf: fix perf stream opening lock

On 28 February 2018 at 11:45, Lionel Landwerlin wrote: > We're seeing on CI that some contexts don't have the programmed OA > period timer that directs the OA unit on how often to write reports. > > The issue is that we're not holding the drm lock from when we edit

Re: [Intel-gfx] [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

On 2/26/2018 9:49 PM, Sagar Arun Kamble wrote: On 2/27/2018 4:34 AM, Oscar Mateo wrote: On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote: On 2/23/2018 4:35 AM, Oscar Mateo wrote: + * We might have detected that some engines are fused off after we initialized + * the forcewake

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Wedged engine mask makes more sense in hex

== Series Details == Series: drm/i915: Wedged engine mask makes more sense in hex URL : https://patchwork.freedesktop.org/series/39147/ State : success == Summary == Series 39147v1 drm/i915: Wedged engine mask makes more sense in hex

Re: [Intel-gfx] [PATCH] drm/i915/dp: Add HBR3 rate (8.1 Gbps) to default rates array

On Wed, Feb 28, 2018 at 11:05:24AM +0200, Jani Nikula wrote: > On Tue, 27 Feb 2018, Manasi Navare wrote: > > default_rates[] array is a superset of all the link rates supported > > by sink devices. DP 1.3 specification adds HBR3 (8.1Gbps) link rate > > to the set of

[Intel-gfx] [PATCH] drm/i915: Wedged engine mask makes more sense in hex

From: Tvrtko Ursulin In decimal its just a weird big number, while in hex can actually log which engines were requested to be wedged. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_debugfs.c | 3 ++- 1 file changed, 2

[Intel-gfx] [PATCH i-g-t v2] tests/perf_pmu: Test busyness reporting in face of GPU hangs

From: Tvrtko Ursulin Verify that the reported busyness is in line with what would we expect from a batch which causes a hang and gets kicked out from the engine. v2: Change to explicit igt_force_gpu_reset instead of guessing when a spin batch will hang. (Chris

Re: [Intel-gfx] [PATCH] drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset

On Wed, Feb 28, 2018 at 06:05:11PM +0200, Ville Syrjälä wrote: > On Wed, Feb 28, 2018 at 05:36:56PM +0200, Imre Deak wrote: > > Enabling FBC on a plane having a Y-offset that isn't dividable by 4 may > > cause pipe FIFO underruns and flickers, so disable FBC on such a config. > > > > I tried to

Re: [Intel-gfx] [PATCH 5/8] drm/i915: Consult aux_ch instead of port in ->get_aux_clock_divider()

On Thu, Feb 22, 2018 at 08:10:33PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > While it seems totally unlikely that any system would mix a cpu/north > aux channel with a pch/south port (or vice versa) we should still > consult intel_dp->aux_ch rather than

Re: [Intel-gfx] [PATCH 06/43] misc/mei/hdcp: Add KBuild for mei hdcp driver

> On Wednesday 14 February 2018 08:24 PM, Winkler, Tomas wrote: > >> Signed-off-by: Ramalingam C > >> --- > >> drivers/misc/mei/Kconfig | 6 ++ > >> drivers/misc/mei/Makefile | 2 ++ > >> 2 files changed, 8 insertions(+) > >> > >> diff --git

Re: [Intel-gfx] [PATCH] drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset

On Wed, Feb 28, 2018 at 05:36:56PM +0200, Imre Deak wrote: > Enabling FBC on a plane having a Y-offset that isn't dividable by 4 may > cause pipe FIFO underruns and flickers, so disable FBC on such a config. > > I tried to the followings to work around the issue: > - enable each HW work around in

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset

== Series Details == Series: drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset URL : https://patchwork.freedesktop.org/series/39129/ State : success == Summary == Series 39129v1 drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset

[Intel-gfx] [PATCH igt 4/5] igt/gem_exec_capture: Exercise readback of userptr

EXEC_OBJECT_CAPTURE extends the type of buffers we may read during error capture. Previously we knew that we would only see batch buffers (which limited the objects to being from gem_create()), but now we need to check that any buffer the user can create can be read. The first alternate buffer

[Intel-gfx] [PATCH igt 5/5] igt/gem_exec_fence: Exercise merging fences

Execute the same batch on each engine and check that the composite fence across all engines completes only after the batch is completed on every engine. Signed-off-by: Chris Wilson --- tests/gem_exec_fence.c | 127 + 1

[Intel-gfx] [PATCH igt 3/5] igt/gem_ctx_switch: Exercise all engines at once

Just a small variant to apply a continuous context-switch load to all engines. --- tests/gem_ctx_switch.c | 83 ++ 1 file changed, 83 insertions(+) diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c index 79b1d74b..4c7c5391 100644 ---

[Intel-gfx] [PATCH igt 1/5] lib/dummyload: Avoid assertions in lowlevel spin constructor

__igt_spin_batch_new() may be used inside a background helper which is competing against the GPU being reset. As such, we cannot even assert that the spin->handle is busy immediately after submission as it may have already been reset by another client writing to i915_wedged. Signed-off-by: Chris

[Intel-gfx] [PATCH igt 2/5] igt/gem_spin_batch: Avoid waiting when running concurrently

If we do a global wait while trying to execute spinners in parallel, it ends badly with a GPU hang. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104352 Signed-off-by: Chris Wilson --- tests/gem_spin_batch.c | 16 +--- 1 file changed, 9

Re: [Intel-gfx] [PATCH 06/43] misc/mei/hdcp: Add KBuild for mei hdcp driver

On Wednesday 14 February 2018 08:24 PM, Winkler, Tomas wrote: Signed-off-by: Ramalingam C --- drivers/misc/mei/Kconfig | 6 ++ drivers/misc/mei/Makefile | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig

[Intel-gfx] [PULL] drm-misc-fixes

Hi Dave, A few more fixes for 4.16, including 2 regression fixes. Please pull. Thanks, Gustavo drm-misc-fixes-2018-02-28: Two regression fixes here: a fb format regression on nouveau and a 4.16-rc1 regression with on LVDS with one sun4i device. Plus a sun4i and a virtio-gpu fixes. The

[Intel-gfx] [PATCH] drm/i915/gen9: Disable FBC on planes with a misaligned Y-offset

Enabling FBC on a plane having a Y-offset that isn't dividable by 4 may cause pipe FIFO underruns and flickers, so disable FBC on such a config. I tried to the followings to work around the issue: - enable each HW work around in ILK_DPFC_CHICKEN - disable each compression algorithm in

[Intel-gfx] [PATCH i-g-t v2] lib/igt_pm: Restore runtime pm state on test exit

From: Tvrtko Ursulin Some tests (the ones which call igt_setup_runtime_pm and igt_pm_enable_audio_runtime_pm) change default system configuration and never restore it. The configured runtime suspend is aggressive and may influence behaviour of subsequent tests, so it

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/perf: fix perf stream opening lock

== Series Details == Series: drm/i915/perf: fix perf stream opening lock URL : https://patchwork.freedesktop.org/series/39112/ State : success == Summary == Possible new issues: Test kms_rotation_crc: Subgroup primary-rotation-270: fail -> PASS

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Don't deref request->ctx inside unlocked print_request()

== Series Details == Series: drm/i915: Don't deref request->ctx inside unlocked print_request() URL : https://patchwork.freedesktop.org/series/39098/ State : success == Summary == Possible new issues: Test kms_rotation_crc: Subgroup primary-rotation-270: fail

Re: [Intel-gfx] [PATCH i-g-t] lib/igt_pm: Restore runtime pm state on test exit

On 28/02/2018 12:27, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-28 11:38:01) On 28/02/2018 11:12, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-28 11:08:29) From: Tvrtko Ursulin Some tests (the ones which call igt_setup_runtime_pm and

Re: [Intel-gfx] [PATCH i-g-t] lib/igt_pm: Restore runtime pm state on test exit

Quoting Tvrtko Ursulin (2018-02-28 11:08:29) > From: Tvrtko Ursulin > > Some tests (the ones which call igt_setup_runtime_pm and > igt_pm_enable_audio_runtime_pm) change default system configuration and > never restore it. > > The configured runtime suspend is

Re: [Intel-gfx] [PATCH] drm/i915: Don't deref request->ctx inside unlocked print_request()

Quoting Mika Kuoppala (2018-02-28 12:49:00) > Chris Wilson writes: > > > Although we protect the request itself, we don't lock inside > > intel_engine_dump() and so the request maybe retired as we peek into it. > > One consequence is that the request->ctx may be freed

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't mangle the CTM on pre-HSW

On Wed, Feb 28, 2018 at 01:11:12PM +, Shankar, Uma wrote: > > > >-Original Message- > >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > >Sent: Friday, February 23, 2018 7:23 PM > >To: Shankar, Uma > >Cc: intel-gfx@lists.freedesktop.org; Lin,

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Don't mangle the CTM on pre-HSW

>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Friday, February 23, 2018 7:23 PM >To: Shankar, Uma >Cc: intel-gfx@lists.freedesktop.org; Lin, Johnson ; >Sharma, Shashank

Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings

Patchwork writes: > == Series Details == > > Series: series starting with [CI,1/2] drm/i915/icl: Prepare for more rings > URL : https://patchwork.freedesktop.org/series/39102/ > State : warning > > == Summary == > > Series 39102v1 series starting with [CI,1/2]

Re: [Intel-gfx] [PATCH 3/4] drm/i915: Rename pipe CSC to use ilk_ prefix

On Fri, Feb 23, 2018 at 01:05:25PM +, Shankar, Uma wrote: > > > >-Original Message- > >From: Ville Syrjala [mailto:ville.syrj...@linux.intel.com] > >Sent: Friday, February 23, 2018 3:13 AM > >To: intel-gfx@lists.freedesktop.org > >Cc: Lin, Johnson ; Shankar,

Re: [Intel-gfx] [PATCH 1/4] drm/uapi: The ctm matrix uses sign-magnitude representation

On Fri, Feb 23, 2018 at 04:04:10PM +0200, Ville Syrjälä wrote: > On Fri, Feb 23, 2018 at 01:52:22PM +, Brian Starkey wrote: > > Hi Ville, > > > > On Thu, Feb 22, 2018 at 11:42:29PM +0200, Ville Syrjala wrote: > > >From: Ville Syrjälä > > > > > >The

Re: [Intel-gfx] [PATCH] drm/i915: Don't deref request->ctx inside unlocked print_request()

Chris Wilson writes: > Although we protect the request itself, we don't lock inside > intel_engine_dump() and so the request maybe retired as we peek into it. > One consequence is that the request->ctx may be freed before we > dereference it, leading to a

Re: [Intel-gfx] [PATCH] drm/i915: Don't deref request->ctx inside unlocked print_request()

Quoting Mika Kuoppala (2018-02-28 12:32:40) > Chris Wilson writes: > > > Although we protect the request itself, we don't lock inside > > intel_engine_dump() and so the request maybe retired as we peek into it. > > One consequence is that the request->ctx may be freed

Re: [Intel-gfx] [PATCH] drm/i915: Don't deref request->ctx inside unlocked print_request()

Chris Wilson writes: > Although we protect the request itself, we don't lock inside > intel_engine_dump() and so the request maybe retired as we peek into it. > One consequence is that the request->ctx may be freed before we > dereference it, leading to a

Re: [Intel-gfx] [PATCH i-g-t] lib/igt_pm: Restore runtime pm state on test exit

Quoting Tvrtko Ursulin (2018-02-28 11:38:01) > > On 28/02/2018 11:12, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-02-28 11:08:29) > >> From: Tvrtko Ursulin > >> > >> Some tests (the ones which call igt_setup_runtime_pm and > >> igt_pm_enable_audio_runtime_pm)

Re: [Intel-gfx] [PATCH igt v2] tests: Add a random load generator

Quoting Arkadiusz Hiler (2018-02-28 12:11:41) > On Mon, Jan 22, 2018 at 11:14:01AM +0200, Chris Wilson wrote: > > Apply a random load to one or all engines in order to apply stress to > > RPS as it tries to constantly adjust the GPU frequency to meet the > > changing workload. > > Doing some IGT

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: fix perf stream opening lock

== Series Details == Series: drm/i915/perf: fix perf stream opening lock URL : https://patchwork.freedesktop.org/series/39112/ State : success == Summary == Series 39112v1 drm/i915/perf: fix perf stream opening lock https://patchwork.freedesktop.org/api/1.0/series/39112/revisions/1/mbox/

Re: [Intel-gfx] [PATCH igt v2] tests: Add a random load generator

On Mon, Jan 22, 2018 at 11:14:01AM +0200, Chris Wilson wrote: > Apply a random load to one or all engines in order to apply stress to > RPS as it tries to constantly adjust the GPU frequency to meet the > changing workload. Doing some IGT archeology here. Seems like both 'all' and 'pulse'

[Intel-gfx] [PATCH] drm/i915/perf: fix perf stream opening lock

We're seeing on CI that some contexts don't have the programmed OA period timer that directs the OA unit on how often to write reports. The issue is that we're not holding the drm lock from when we edit the context images down to when we set the exclusive_stream variable. This leaves a window for

Re: [Intel-gfx] [PATCH i-g-t] lib/igt_pm: Restore runtime pm state on test exit

On 28/02/2018 11:12, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-02-28 11:08:29) From: Tvrtko Ursulin Some tests (the ones which call igt_setup_runtime_pm and igt_pm_enable_audio_runtime_pm) change default system configuration and never restore it. The

[Intel-gfx] ✗ Fi.CI.BAT: warning for series starting with [CI,1/2] drm/i915/icl: Prepare for more rings

== Series Details == Series: series starting with [CI,1/2] drm/i915/icl: Prepare for more rings URL : https://patchwork.freedesktop.org/series/39102/ State : warning == Summary == Series 39102v1 series starting with [CI,1/2] drm/i915/icl: Prepare for more rings

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Don't deref request->ctx inside unlocked print_request()

== Series Details == Series: drm/i915: Don't deref request->ctx inside unlocked print_request() URL : https://patchwork.freedesktop.org/series/39098/ State : success == Summary == Series 39098v1 drm/i915: Don't deref request->ctx inside unlocked print_request()

Re: [Intel-gfx] [PATCH i-g-t] lib/igt_pm: Restore runtime pm state on test exit

Quoting Tvrtko Ursulin (2018-02-28 11:08:29) > From: Tvrtko Ursulin > > Some tests (the ones which call igt_setup_runtime_pm and > igt_pm_enable_audio_runtime_pm) change default system configuration and > never restore it. > > The configured runtime suspend is

Re: [Intel-gfx] [PATCH] drm/i915/skl+: Add and enable DP AUX CH mutex

On Wed, Feb 28, 2018 at 12:57:07AM +, Souza, Jose wrote: > On Tue, 2018-02-27 at 23:34 +0200, Ville Syrjälä wrote: > > On Tue, Feb 27, 2018 at 01:23:59PM -0800, José Roberto de Souza > > wrote: > > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it > > > self, so lets use

[Intel-gfx] [PATCH i-g-t] lib/igt_pm: Restore runtime pm state on test exit

From: Tvrtko Ursulin Some tests (the ones which call igt_setup_runtime_pm and igt_pm_enable_audio_runtime_pm) change default system configuration and never restore it. The configured runtime suspend is aggressive and may influence behaviour of subsequent tests, so it

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/i915/dp: move link rate arrays where they're used

== Series Details == Series: drm/i915/dp: move link rate arrays where they're used URL : https://patchwork.freedesktop.org/series/39032/ State : warning == Summary == Possible new issues: Test kms_frontbuffer_tracking: Subgroup fbc-2p-scndscrn-indfb-msflip-blt:

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 1/2] tests/kms_frontbuffer_tracking: Fix build warning

Quoting Tvrtko Ursulin (2018-02-28 10:07:59) > From: Tvrtko Ursulin > > Mark drrs_set as static to avoid a build warning. > > Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson -Chris

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 2/2] tests/perf: Fix build warning

Reviewed-by: Lionel Landwerlin On 28/02/18 10:08, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Move variable declaration to top of scope to avoid C90 build warning. Signed-off-by: Tvrtko Ursulin ---

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