== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm
URL : https://patchwork.freedesktop.org/series/67927/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7067_full -> Patchwork_14772_full
== Series Details ==
Series: drm/i915: coffeelake supports hdcp2.2
URL : https://patchwork.freedesktop.org/series/67925/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7067_full -> Patchwork_14771_full
Summary
---
== Series Details ==
Series: drm/i915: Add an rcu_barrier option to i915_drop_caches
URL : https://patchwork.freedesktop.org/series/67922/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7065_full -> Patchwork_14770_full
On Wed, Sep 25, 2019 at 03:17:37PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst
> Just use Cc. We want all replies to go to the list(s) as well.
Sorry, I wasn't sure and wanted to err on the side of not spamming the
wrong people.
> Oct 10 12:53:30 scorpion kernel: RIP:
0010:dma_fence_signal_locked+0x30/0xe0
>
> Looks like it could be
>
== Series Details ==
Series: drm/i915: Favor last VBT child device with conflicting AUX ch/DDC pin
URL : https://patchwork.freedesktop.org/series/67931/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14775
== Series Details ==
Series: drm/i915: Some cleanup near the SKL wm/ddb area
URL : https://patchwork.freedesktop.org/series/67930/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
== Series Details ==
Series: drm/i915/selftests: Serialise write to scratch with its vma binding
URL : https://patchwork.freedesktop.org/series/67928/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14773
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm
URL : https://patchwork.freedesktop.org/series/67927/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14772
From: Ville Syrjälä
The first come first served apporoach to handling the VBT
child device AUX ch conflicts has backfired. We have machines
in the wild where the VBT specifies both port A eDP and
port E DP (in that order) with port E being the real one.
So let's try to flip the preference
From: Ville Syrjälä
The dirty_pipes bitmask is now unused. Get rid of it.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/intel_pm.c | 35 +
2 files changed, 1 insertion(+), 35 deletions(-)
diff --git
From: Ville Syrjälä
skl_commit_modeset_enables() is a bit of mess. Let's streamline
it by simply tracking which pipes still need to be updated.
As a bonus we get rid of the state->wm_results.dirty_pipes usage.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 39
From: Ville Syrjälä
Made the mistake of looking at some skl+ wm/ddb stuff,
and then proceeded to throw out a bunch of useless things.
I stopped when I saw struct skl_ddb_allocation and decided
that maybe that starts to cut a bit too close to the dbuf
slice stuff.
Ville Syrjälä (8):
drm/i915:
From: Ville Syrjälä
Let's store the normal and IPS linetime watermarks individually,
and while at it we'll pimp the register definitions as well.
Signed-off-by: Ville Syrjälä
---
.../drm/i915/display/intel_display_types.h| 3 +-
drivers/gpu/drm/i915/i915_reg.h | 14 ++--
From: Ville Syrjälä
The linetime watermarks really have very little in common with the
plane watermarks. It looks to be cleaner to simply track them in
the crtc_state and program them from the normal modeset/fastset
paths.
The only dark cloud comes from the fact that the register is
still
From: Ville Syrjälä
skl_commit_modeset_enables() straight up compares dirty_pipes
with a bitmask of already committed pipes. If we set bits in
dirty_pipes for non-existent pipes that comparison will never
work right. So let's limit ourselves to bits that exist.
And we'll do the same for the
From: Ville Syrjälä
changed==true just means we have some crtcs in the state. All the
stuff following this only operates on crtcs in the state anyway so
there is no point in having this bool.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 30 --
From: Ville Syrjälä
The 'realloc_pipes' bitmask is pointless. It is either:
a) the set of pipes which are already part of the state,
in which case adding them again is entirely redundant
b) the set of all pipes which we then add to the state
Also the fact that 'realloc_pipes' uses the crtc
From: Ville Syrjälä
Despite the its name dirty_pipes refers to crtc indexes. Let's
change its behaviout to match the name.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
drivers/gpu/drm/i915/intel_pm.c | 13 ++---
2 files
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm
URL : https://patchwork.freedesktop.org/series/67927/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9446e81d2ad5 drm/i915/perf: Replace global wakeref
== Series Details ==
Series: drm/i915: coffeelake supports hdcp2.2
URL : https://patchwork.freedesktop.org/series/67925/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14771
Summary
---
**SUCCESS**
On Fri, 11 Oct 2019 at 20:36, Chris Wilson wrote:
>
> Add the missing serialisation on the request for a write into a vma to
> wait until that vma is bound before being executed by the GPU.
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
Reviewed-by: Matthew Auld
Add the missing serialisation on the request for a write into a vma to
wait until that vma is bound before being executed by the GPU.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gt/selftest_workarounds.c | 8
1 file changed, 8 insertions(+)
diff --git
On Thu, Oct 10, 2019 at 04:35:56PM +0300, Jani Nikula wrote:
> On Thu, 10 Oct 2019, Hans de Goede wrote:
> > Hi Jani,
> >
> > During plumbers I had some discussions with Daniel about supporting
> > OLED screens. Userspace may need to know that a panel is OLED for 2
> > reasons:
> >
> > 1) To
On Fri, 2019-10-11 at 10:16 +0300, Martin Peres wrote:
> On 10/10/2019 23:18, Patchwork wrote:
> > == Series Details ==
> >
> > Series: series starting with [1/4] drm/i915/display: Handle fused
> > off display correctly
> > URL : https://patchwork.freedesktop.org/series/67872/
> > State :
As we now have a specific engine to use OA on, exchange the top-level
runtime-pm wakeref with the engine-pm. This still results in the same
top-level runtime-pm, but with more nuances to keep the engine and its
gt awake.
Signed-off-by: Chris Wilson
Reviewed-by: Lionel Landwerlin
---
From: Lionel Landwerlin
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
Signed-off-by: Chris Wilson
---
From: Lionel Landwerlin
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content
We set out-of-bound parameters inside the i915_requests.flags field,
such as disabling preemption or marking the end-of-context. We should
not coalesce consecutive requests if they have differing instructions
as we only inspect the last active request in a context. Thus if we
allow a later request
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA context to reconfigure the stream asynchronously on
the GPU in between
From: Lionel Landwerlin
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not
From: Lionel Landwerlin
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as
From: Lionel Landwerlin
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
From: Lionel Landwerlin
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace
On Fri, 11 Oct 2019 at 19:37, Chris Wilson wrote:
>
> Corresponding kernel commit 54895010a893 ("drm/i915: Add an rcu_barrier
> option to i915_drop_caches")
>
> Signed-off-by: Chris Wilson
> Cc: Matthew Auld
Reviewed-by: Matthew Auld
___
Intel-gfx
Corresponding kernel commit 54895010a893 ("drm/i915: Add an rcu_barrier
option to i915_drop_caches")
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
lib/igt_debugfs.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h
index 36b638177..a56f09dd2
== Series Details ==
Series: drm/i915: Add an rcu_barrier option to i915_drop_caches
URL : https://patchwork.freedesktop.org/series/67922/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7065 -> Patchwork_14770
Summary
Quoting Mika Kuoppala (2019-10-11 14:39:11)
> In order to ensure constant caches are invalidated
> properly with a0, we need extra hdc flush after invalidation.
>
> References: HSDES#1604544889
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++
>
This includes other platforms that utilize the same gen graphics as
CFL: AML, WHL and CML.
Signed-off-by: Juston Li
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
Quoting Mika Kuoppala (2019-10-11 14:39:10)
> Add hdc pipeline flush to ensure memory state is coherent
> in L3 when we are done.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> 2 files changed,
Quoting Mika Kuoppala (2019-10-11 14:39:09)
> Aim for completeness and invalidate also the ro parts
> in l3 cache. This might allow to get rid of the preparser
> disable/enable workaround on invalidation path.
>
> Cc: Chris Wilson
> Signed-off-by: Mika Kuoppala
> ---
>
Quoting Mika Kuoppala (2019-10-11 14:39:10)
> Add hdc pipeline flush to ensure memory state is coherent
> in L3 when we are done.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> 2 files changed,
On Fri, 11 Oct 2019 at 18:38, Chris Wilson wrote:
>
> Sometimes a test has to wait for RCU to complete a grace period and
> perform its callbacks, for example waiting for a close(fd) to actually
> perform the fput(filp) and so trigger all the callbacks such as closing
> GEM contexts. There is no
Reviewed-by: José Roberto de Souza
On Thu, 2019-10-10 at 18:09 -0700, Lucas De Marchi wrote:
> Fixes: 83fa9842afe7 ("drm/dp-mst: Drop connection_mutex check")
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/drm_dp_mst_topology.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git
On Thu, 2019-10-10 at 18:09 -0700, Lucas De Marchi wrote:
> Instead of the ever growing switch, just compute the ddi io power
> domain
> based on the port number.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 43
On Thu, 2019-10-10 at 17:26 -0700, Vivek Kasireddy wrote:
> On some platforms that have the MCC PCH, Port C's hotplug interrupt
Some?
> bits are mapped to TC1 bits.
>
> Suggested-by: Matt Roper
> Signed-off-by: Vivek Kasireddy
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
>
+dri, +Daniel
On Thu, Oct 10, 2019 at 06:09:07PM -0700, Lucas De Marchi wrote:
Fixes: 83fa9842afe7 ("drm/dp-mst: Drop connection_mutex check")
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/drm_dp_mst_topology.c | 2 --
1 file changed, 2 deletions(-)
diff --git
== Series Details ==
Series: mdev based hardware virtio offloading support (rev4)
URL : https://patchwork.freedesktop.org/series/66989/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7061_full -> Patchwork_14764_full
Sometimes a test has to wait for RCU to complete a grace period and
perform its callbacks, for example waiting for a close(fd) to actually
perform the fput(filp) and so trigger all the callbacks such as closing
GEM contexts. There is no trivial means of triggering an RCU barrier
from userspace, so
On Fri, Oct 11, 2019 at 08:14:32PM +0300, Ville Syrjälä wrote:
On Fri, Oct 11, 2019 at 10:08:32AM -0700, Lucas De Marchi wrote:
On Fri, Oct 11, 2019 at 03:08:50PM +0300, Ville Syrjälä wrote:
>On Thu, Oct 10, 2019 at 06:09:06PM -0700, Lucas De Marchi wrote:
>> s/?/:/ so it's get correctly
On Fri, Oct 11, 2019 at 10:08:32AM -0700, Lucas De Marchi wrote:
> On Fri, Oct 11, 2019 at 03:08:50PM +0300, Ville Syrjälä wrote:
> >On Thu, Oct 10, 2019 at 06:09:06PM -0700, Lucas De Marchi wrote:
> >> s/?/:/ so it's get correctly colored by dmesg.
> >
> >What do you mean correctly?
> >
> >The
On Fri, Oct 11, 2019 at 03:08:50PM +0300, Ville Syrjälä wrote:
On Thu, Oct 10, 2019 at 06:09:06PM -0700, Lucas De Marchi wrote:
s/?/:/ so it's get correctly colored by dmesg.
What do you mean correctly?
The debug message was asking the question "(is) MST supported?"
After this it just
On Wed, Oct 09, 2019 at 02:27:41PM -0700, Matt Roper wrote:
> On Wed, Oct 09, 2019 at 05:01:20PM -0400, Daniele Castagna wrote:
> > On Wed, Oct 9, 2019 at 1:34 PM Matt Roper wrote:
> > >
> > > The previous version of this series was posted in February here:
> > >
> > >
== Series Details ==
Series: series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to
invalidate
URL : https://patchwork.freedesktop.org/series/67912/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7064 -> Patchwork_14769
Quoting Chris Wilson (2019-10-11 15:22:17)
> Quoting Tvrtko Ursulin (2019-10-11 14:55:00)
> >
> > On 10/10/2019 08:14, Chris Wilson wrote:
> > > + if (engine)
> > > + active |= engine->mask;
> > > +
> > > + dma_fence_put(fence);
> > > + }
> > > +
>
== Series Details ==
Series: series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to
invalidate
URL : https://patchwork.freedesktop.org/series/67912/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9438571a7abe drm/i915/tgl: Include ro parts of l3 to invalidate
-:21:
Quoting Summers, Stuart (2019-10-11 16:14:07)
> On Fri, 2019-10-11 at 12:36 +0100, Chris Wilson wrote:
> > +void intel_engines_add_sysfs(struct drm_i915_private *i915)
> > +{
> > + static const struct attribute *files[] = {
> > + _attr.attr,
> > + _attr.attr,
> > +
On Fri, 2019-10-11 at 12:36 +0100, Chris Wilson wrote:
> Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
> that we can expose properties on each engine to the sysadmin.
>
> To start with we have basic analogues of the i915_query ioctl so that
> we
> can pretty print engine
Quoting Tvrtko Ursulin (2019-10-11 15:56:35)
>
> On 10/10/2019 08:14, Chris Wilson wrote:
> > If we do find ourselves with an idle barrier inside our active while
> > waiting, attempt to flush it by emitting a pulse using the kernel
> > context.
>
> The point of this one completely escapes me at
Quoting Tvrtko Ursulin (2019-10-11 15:24:21)
>
> On 10/10/2019 08:14, Chris Wilson wrote:
> > +config DRM_I915_HEARTBEAT_INTERVAL
> > + int "Interval between heartbeat pulses (ms)"
> > + default 2500 # milliseconds
> > + help
> > + While active the driver uses a periodic
On Fri, 2019-10-11 at 15:25 +0300, Ville Syrjälä wrote:
> On Thu, Oct 10, 2019 at 12:32:38PM -0700, José Roberto de Souza
> wrote:
> > If all pipes are fused off it means that display is disabled,
> > similar
> > like we handle for GEN 7 and 8 right above.
> >
> > On GEN 9 the bit 31 is "Internal
On 10/10/2019 08:14, Chris Wilson wrote:
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
The point of this one completely escapes me at the moment. Idle barriers
are kept in there to be consumed
== Series Details ==
Series: Small fixes before fixing MST
URL : https://patchwork.freedesktop.org/series/67883/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7060_full -> Patchwork_14763_full
Summary
---
On 10/10/2019 08:14, Chris Wilson wrote:
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
The
Quoting Tvrtko Ursulin (2019-10-11 14:55:00)
>
> On 10/10/2019 08:14, Chris Wilson wrote:
> > Normally, we rely on our hangcheck to prevent persistent batches from
> > hogging the GPU. However, if the user disables hangcheck, this mechanism
> > breaks down. Despite our insistence that this is
Quoting Tvrtko Ursulin (2019-10-11 14:10:21)
>
> On 11/10/2019 12:16, Chris Wilson wrote:
> > On schedule-out (CS completion) of a banned context, scrub the context
> > image so that we do not replay the active payload. The intent is that we
> > skip banned payloads on request submission so that
On 10/10/2019 08:14, Chris Wilson wrote:
Normally, we rely on our hangcheck to prevent persistent batches from
hogging the GPU. However, if the user disables hangcheck, this mechanism
breaks down. Despite our insistence that this is unsafe, the users are
equally insistent that they want to use
== Series Details ==
Series: drm/i915/ehl: Port C's hotplug interrupt is associated with TC1 bits
URL : https://patchwork.freedesktop.org/series/67881/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7060_full -> Patchwork_14762_full
Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
2 files changed, 2 insertions(+)
diff --git
In order to ensure constant caches are invalidated
properly with a0, we need extra hdc flush after invalidation.
References: HSDES#1604544889
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++
1 file changed, 18 insertions(+)
diff --git
Aim for completeness and invalidate also the ro parts
in l3 cache. This might allow to get rid of the preparser
disable/enable workaround on invalidation path.
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
Quoting Chris Wilson (2019-10-10 14:48:49)
> Check the user's flags on the struct file before deciding whether or not
> to stall before submitting a request. This allows us to reasonably
> cheaply honour O_NONBLOCK without checking at more critical phases
> during request submission.
>
>
On 11/10/2019 00:23, Chris Wilson wrote:
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA context to reconfigure the
On 11/10/2019 13:31, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-11 13:16:33)
[snip]
Looks fine in principle.
I am tempted to go with some of the engine->flags from the start but I
don't have an use case apart from saying that it sounds like it makes sense.
The problem I saw with
On 11/10/2019 13:43, Chris Wilson wrote:
We already check that debugfs do not cause spam (and they tend to be
more heavyhanded and so more likely to break), but that does not excuse
not checking our sysfs directory!
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/debugfs_test.c |
On 11/10/2019 12:16, Chris Wilson wrote:
On schedule-out (CS completion) of a banned context, scrub the context
image so that we do not replay the active payload. The intent is that we
skip banned payloads on request submission so that the timeline
advancement continues on in the background.
We already check that debugfs do not cause spam (and they tend to be
more heavyhanded and so more likely to break), but that does not excuse
not checking our sysfs directory!
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/debugfs_test.c | 8 ++--
1 file changed, 6 insertions(+),
Quoting Tvrtko Ursulin (2019-10-11 13:16:33)
>
> On 11/10/2019 12:36, Chris Wilson wrote:
> > Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
> > that we can expose properties on each engine to the sysadmin.
> >
> > To start with we have basic analogues of the i915_query
On Thu, Oct 10, 2019 at 08:45:42PM +, Souza, Jose wrote:
> I messed up on this patch, please ignore this one.
> Will send the fixed version soon.
The whole thing is wrong according to the spec:
"This field is unused on BXT. Any CD clock frequency limitation must be
done in software."
>
>
On Thu, Oct 10, 2019 at 12:32:41PM -0700, José Roberto de Souza wrote:
> Those features could be fused off on GEN9 non-low power and newer
> GENs.
Should probably be two patches.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>
On Thu, Oct 10, 2019 at 12:32:39PM -0700, José Roberto de Souza wrote:
> HDCP could be fused off, so not all GEN9+ platforms will support it.
>
> Signed-off-by: José Roberto de Souza
> ---
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
>
On Thu, Oct 10, 2019 at 12:32:38PM -0700, José Roberto de Souza wrote:
> If all pipes are fused off it means that display is disabled, similar
> like we handle for GEN 7 and 8 right above.
>
> On GEN 9 the bit 31 is "Internal Graphics Disable" and on newer GENs
> it has another function, probably
On Thu, Oct 10, 2019 at 02:01:32PM -0700, Manasi Navare wrote:
> We no longer use the connection mutex and hence no need to
> define drm_device *dev, it causes a unused variable build warning
>
> Fixes: 83fa9842afe7 ("drm/dp-mst: Drop connection_mutex check")
> Cc: Sean Paul
Reviewed-by: Sean
On 11/10/2019 12:36, Chris Wilson wrote:
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell,
On Thu, Oct 10, 2019 at 06:09:06PM -0700, Lucas De Marchi wrote:
> s/?/:/ so it's get correctly colored by dmesg.
What do you mean correctly?
The debug message was asking the question "(is) MST supported?"
After this it just declares that MST is not supported. I guess no real
difference so I
On Thu, Oct 10, 2019 at 06:09:05PM -0700, Lucas De Marchi wrote:
> This way it's easier to figure out what didn't match when we have
> multiple pipes enabled.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 33 +++-
> 1 file changed, 18
== Series Details ==
Series: drm/i915: Expose engine properties via sysfs (rev3)
URL : https://patchwork.freedesktop.org/series/66849/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7061 -> Patchwork_14768
Summary
---
On Thu, Oct 10, 2019 at 06:09:04PM -0700, Lucas De Marchi wrote:
> The new line is already added by pipe_config_mismatch(), so the callers
> shouldn't add it.
I guess fallout from commit 48c38154d539 ("drm/i915: use DRM_DEBUG_KMS()
instead of drm_dbg(DRM_UT_KMS, ...)") ?
Looks correct to me.
On Thu, Oct 10, 2019 at 06:09:03PM -0700, Lucas De Marchi wrote:
> Both Ice Lake and Elkhart Lake (gen 11) support MST on all external
> connections except DDI A. Tiger Lake (gen 12) supports on all external
> connections.
>
> Move the check to happen inside intel_dp_mst_encoder_init() and add
>
On 11/10/2019 11:33, Chris Wilson wrote:
Only the requests that have not completed do we want to change the
status of to signal the -EIO when cancelling the inflight set of requests
upon wedging.
Reported-by: Tvrtko Ursulin
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Quoting Dan Carpenter (2019-10-11 12:42:09)
> Hello Chris Wilson,
>
> This is a semi-automatic email about new static checker warnings.
>
> The patch 50d16d44cce4: "drm/i915/selftests: Exercise context
> switching in parallel" from Sep 30, 2019, leads to the following
> Smatch complaint:
>
>
On Thu, Oct 10, 2019 at 06:09:02PM -0700, Lucas De Marchi wrote:
> Those init functions mark their success in the intel_dig_port
> struct, the return values are not really used.
>
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +--
>
== Series Details ==
Series: drm/i915: Expose engine properties via sysfs (rev3)
URL : https://patchwork.freedesktop.org/series/66849/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Expose engine properties via sysfs
-
== Series Details ==
Series: drm/i915: Expose engine properties via sysfs (rev3)
URL : https://patchwork.freedesktop.org/series/66849/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
379c8db3d036 drm/i915: Expose engine properties via sysfs
-:66: WARNING:FILE_PATH_CHANGES:
Hello Chris Wilson,
This is a semi-automatic email about new static checker warnings.
The patch 50d16d44cce4: "drm/i915/selftests: Exercise context
switching in parallel" from Sep 30, 2019, leads to the following
Smatch complaint:
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c:349
== Series Details ==
Series: series starting with [01/10] drm/i915: Note the addition of timeslicing
to the pretend scheduler (rev3)
URL : https://patchwork.freedesktop.org/series/67827/
State : failure
== Summary ==
Applying: drm/i915: Note the addition of timeslicing to the pretend
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure.
On schedule-out (CS completion) of a banned context, scrub the context
image so that we do not replay the active payload. The intent is that we
skip banned payloads on request submission so that the timeline
advancement continues on in the background. However, if we are returning
to a preempted
== Series Details ==
Series: drm/i915/execlists: Only mark incomplete requests as -EIO on cancelling
URL : https://patchwork.freedesktop.org/series/67904/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7061 -> Patchwork_14766
== Series Details ==
Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref
tracking with engine-pm (rev4)
URL : https://patchwork.freedesktop.org/series/67874/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7058_full -> Patchwork_14761_full
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