op of the function.
So change the BUG_ON into a gen check (alternately we could move the
BUG_ON until later, since we shouldn't have a pll struct here either,
but this seems clearer to read).
This fixes a crash on load on my x200s platform.
Signed-off-by: Jesse Barnes
---
drivers/gp
On 07/07/2015 02:15 AM, Tvrtko Ursulin wrote:
>
> On 07/06/2015 01:58 PM, John Harrison wrote:
>> On 06/07/2015 10:29, Daniel Vetter wrote:
>>> On Fri, Jul 03, 2015 at 12:17:33PM +0100, Tvrtko Ursulin wrote:
On 07/02/2015 04:55 PM, Chris Wilson wrote:
> It would be nice if we could reuse
On 07/01/2015 06:56 AM, Daniel Vetter wrote:
> On Tue, Jun 30, 2015 at 01:30:27PM -0700, Jesse Barnes wrote:
>> On 06/30/2015 07:36 AM, Chris Wilson wrote:
>>> On Tue, Jun 30, 2015 at 11:26:11AM -0300, Paulo Zanoni wrote:
>>>> 2015-06-30 11:15 GMT-03:00 Chris Wilson :
On 07/01/2015 06:53 AM, Peter Antoine wrote:
> On Wed, 1 Jul 2015, Francisco Jerez wrote:
>
>> Peter Antoine writes:
>>
>>> On Tue, 30 Jun 2015, Francisco Jerez wrote:
>>>
Francisco Jerez writes:
> Peter Antoine writes:
>
>> On Mon, 29 Jun 2015, Peter Antoine wrote:
>>
On 06/30/2015 07:36 AM, Chris Wilson wrote:
> On Tue, Jun 30, 2015 at 11:26:11AM -0300, Paulo Zanoni wrote:
>> 2015-06-30 11:15 GMT-03:00 Chris Wilson :
>>> On Tue, Jun 30, 2015 at 10:53:10AM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni
Let's make sure the future Paulos don't forge
On 06/25/2015 12:33 AM, Daniel Vetter wrote:
>> In the specific case of bitfields it seems like it would be sufficient
>> > to mark the local variables as volatile? Or maybe just use open coded
>> > compiler barrier() functions instead, with accompanying documentation.
>> >
>> > Documentation/mem
On 06/22/2015 11:53 PM, Daniel Vetter wrote:
> On Mon, Jun 22, 2015 at 02:19:51PM -0700, Jesse Barnes wrote:
>> On 06/17/2015 08:10 AM, Daniel Vetter wrote:
>>> On Wed, Jun 17, 2015 at 05:28:20PM +0300, Jani Nikula wrote:
>>>> On Wed, 17 Jun 2015, Chris Wilson wrot
On 06/17/2015 08:10 AM, Daniel Vetter wrote:
> On Wed, Jun 17, 2015 at 05:28:20PM +0300, Jani Nikula wrote:
>> On Wed, 17 Jun 2015, Chris Wilson wrote:
>>> Here's an idea I want to float to see if anyone has a better idea.
>>
>> I'll give it some thought, but it pains me that things like this make
On 06/16/2015 05:26 AM, Paulo Zanoni wrote:
> 2015-06-16 9:23 GMT-03:00 Paulo Zanoni :
>> 2015-06-16 5:34 GMT-03:00 Daniel Vetter :
>>> Can I get an ack on this please? The audio folks already move ahead
>>>
>>> http://permalink.gmane.org/gmane.linux.alsa.devel/139831
>>>
>>> Would be embarassing i
On 06/10/2015 08:26 AM, Imre Deak wrote:
> On ke, 2015-06-10 at 08:10 -0700, Jesse Barnes wrote:
>> On 06/10/2015 03:59 AM, Imre Deak wrote:
>>> I think the discussion here is about two separate things:
>>> 1. Possible ordering issue between the seqno store and the com
On 06/10/2015 03:59 AM, Imre Deak wrote:
> I think the discussion here is about two separate things:
> 1. Possible ordering issue between the seqno store and the completion
> interrupt
> 2. Coherency issue that leaves the CPU with a stale view of the seqno
> indefinitely, which this patch works aro
On 05/28/2015 02:20 PM, Chris Wilson wrote:
> On Thu, May 28, 2015 at 01:02:51PM -0700, Jesse Barnes wrote:
>> John, Tomas, where are we with this series? I believe this is a
>> prerequisite for the request->fence conversion, and also the native sync
>> work, both of whi
John, Tomas, where are we with this series? I believe this is a
prerequisite for the request->fence conversion, and also the native sync
work, both of which I need for some stuff I'm doing.
Thanks,
Jesse
On 03/19/2015 05:30 AM, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> The dri
On 05/21/2015 11:10 PM, Daniel Vetter wrote:
> On Thu, May 21, 2015 at 01:18:44PM -0700, Jesse Barnes wrote:
>> On 05/19/2015 10:32 AM, ville.syrj...@linux.intel.com wrote:
>>> From: Ville Syrjälä
>>>
>>> GTT caching was disabled by default on gen8 due to
On 05/21/2015 06:00 AM, Chris Wilson wrote:
> On Tue, May 19, 2015 at 03:41:48PM +0100, Chris Wilson wrote:
>> On Mon, May 11, 2015 at 04:25:52PM +0100, Chris Wilson wrote:
>>> On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson
; + * are ever enabled GTT cache may need to be disabled.
> + */
> + I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
> }
>
> static void g4x_init_clock_gating(struct drm_device *dev)
>
Looks ok to me; I guess testing will be the real review here.
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9b96ed7..50cdd67 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -853,9 +853,6 @@ static int bdw_init_workarounds(struct intel_engine_cs
> *ring)
> GEN6_WIZ_HASHING_MASK,
>
0);
> - I915_WRITE(WM2_LP_ILK, 0);
> - I915_WRITE(WM1_LP_ILK, 0);
> + ilk_init_lp_watermarks(dev);
>
> /* WaSwitchSolVfFArbitrationPriority:bdw */
> I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>
Reviewed-by: Jesse Barnes
___
tel_disable_hdmi;
> + if (HAS_PCH_SPLIT(dev)) {
> + intel_encoder->disable = pch_disable_hdmi;
> + intel_encoder->post_disable = pch_post_disable_hdmi;
> + } else {
> + intel_encoder->disable = g4x_disable_hdmi;
> + }
>
);
> -
> - /* Transcoder selection bits only update
> - * effectively on vblank. */
> - if (crtc)
> -
> intel_wait_for_vblank(encoder->base.dev, pipe);
> -
if (HAS_PCH_IBX(dev)) {
> + I915_WRITE(intel_sdvo->sdvo_reg, val);
> + POSTING_READ(intel_sdvo->sdvo_reg);
> + }
> return;
> }
>
>
This must be the missing fix to all our SDVO problems. (One can hope.)
Reviewed-by: Jesse B
DDI(dev)) {
> + crt->base.disable = pch_disable_crt;
> + crt->base.post_disable = pch_post_disable_crt;
> + } else {
> + crt->base.disable = intel_disable_crt;
> + }
> crt->base.enable = intel_enable_crt;
> if (I915
er)
> if (encoder->post_disable)
> encoder->post_disable(encoder);
>
> if (intel_crtc->config->has_pch_encoder) {
> - ironlake_fdi_disable(crtc);
> -
> ironlake_di
= intel_enable_sdvo;
> intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
>
Commit should probably have something about the hw workaround block
being superceded (assuming that block was intentional in this patch),
but either way:
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_ENH_FRAMING;
> + I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
> } else {
> if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
> intel_dp->DP |= intel_dp->color_range;
>
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ntel_dp_set_link_train(struct intel_dp *intel_dp,
> }
> I915_WRITE(DP_TP_CTL(port), temp);
>
> - } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
> + } else if ((IS_GEN7(dev) && port == PORT_A) ||
> +
- if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
> - *pipe = i;
> + for_each_pipe(dev_priv, p) {
> + u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
> + if (TRANS_DP_PIPE_TO_PORT(trans_dp) == po
mi->hdmi_reg, temp);
> - POSTING_READ(intel_hdmi->hdmi_reg);
> - }
> -
> if (IS_CHERRYVIEW(dev))
> chv_powergate_phy_lanes(encoder, 0xf);
>
>
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p & ~SDVO_ENABLE);
> - POSTING_READ(intel_hdmi->hdmi_reg);
> - }
> -
> temp &= ~enable_bits;
>
> I915_WRITE(intel_hdmi->hdmi_reg, temp);
>
Testing wins.
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[Cc'ing Chris, not sure if he saw the updated version to give his r-b]
On 05/06/2015 03:15 AM, ankitprasad.r.sha...@intel.com wrote:
> From: Ankitprasad Sharma
>
> This patch series adds support for creating/using Stolen memory backed
> objects.
>
> Despite being a unified memory architecture
On 05/04/2015 07:16 AM, Daniel Vetter wrote:
> On Thu, Apr 30, 2015 at 12:22:56PM +0100, Chris Wilson wrote:
>> On Thu, Apr 30, 2015 at 01:28:46PM +0300, Joonas Lahtinen wrote:
>>> On ma, 2015-04-27 at 20:43 +0100, Chris Wilson wrote:
On Mon, Apr 27, 2015 at 06:35:54PM +0100, Thomas Wood wrote
On 05/08/2015 11:51 AM, Daniel Vetter wrote:
> Like with every other feature that's not enabled by default we break
> runtime pm support way too often by accident because the overall test
> coverage isn't great. And it's been almost 2 years since we enabled
> the power well code by default
>
> com
On 05/06/2015 07:48 AM, Patrik Jakobsson wrote:
> This patch set aims to make strace more useful when tracing i915 ioctls.
> The ioctl type is first checked for being drm and then the driver
> backing the opened device is identified by looking at sysfs. Other
> drivers than i915 can easily be added
On 04/29/2015 05:30 AM, Jani Nikula wrote:
> Add port check for ibx similar to vlv in
>
> commit 535afa2e9e3c1867460d6981d879b04d8b2b9ab3
> Author: Jesse Barnes
> Date: Wed Apr 15 16:52:29 2015 -0700
>
> drm/i915/vlv: check port in infoframe_enabled v2
>
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75244
> suggested-by: Jesse Barnes
> Signed-off-by: Deepak S
> ---
> drivers/gpu/drm/i915/intel_pm.c | 20
> 1 file changed, 4 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
On 04/11/2015 01:41 AM, Chris Wilson wrote:
> Bug reports are still coming in for late 4.0-rcX that indicate that
> execlists causes GPU hangs following resume.
>
> Fixes regression from
> commit d7f621e50704306c348ccb192f17047f1499f9bc
> Author: Oscar Mateo
> Date: Thu Jul 24 17:04:49 2014 +01
On 04/02/2015 11:42 AM, Ville Syrjälä wrote:
> On Thu, Apr 02, 2015 at 11:18:49AM -0700, Jesse Barnes wrote:
>> I guess this is a lie for 8xx, but newer stuff takes care of this for
>> us.
>>
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
>
I guess this is a lie for 8xx, but newer stuff takes care of this for
us.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89792
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
k in the PM code to
warn us if something is still amiss.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i91
(see
85250ddff7a603dfe0ec0503a9e6395f79424f61 and
8d4eee9cd7a170342dc6fbc2ee19ae77031a8cd5) and doesn't seem to be
required, so let's just drop it.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89611
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/i915_drv.c | 14 ---
On 04/01/2015 05:28 AM, Chris Wilson wrote:
> On Wed, Apr 01, 2015 at 02:20:53PM +0200, Daniel Vetter wrote:
>> On Wed, Apr 01, 2015 at 10:53:45AM +0100, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin
>>>
>>> Makes it easier for userspace to start supporting Y tiled display,
>>> for at least the l
On 03/04/2015 06:41 AM, Neil Roberts wrote:
> Adds a parameter which can be used with DRM_I915_GETPARAM to query the
> GPU revision. The intention is to use this in Mesa to implement the
> WaDisableSIMD16On3SrcInstr workaround on Skylake but only for
> revision 2.
>
> Signed-off-by: Neil Roberts
TL_I915_SET_SPRITE_COLORKEY ioctl.
>>>
>>> Signed-off-by: Tommi Rantala
>>
>> Whoa. Broken since its introduction in
>>
>> commit 8ea30864229e54b01ac0e9fe88c4b733a940ec4e
>> Author: Jesse Barnes
>> Date: Tue Jan 3 08:05:39 2012 -0800
>>
>
>
> Whoa. Broken since its introduction in
>
> commit 8ea30864229e54b01ac0e9fe88c4b733a940ec4e
> Author: Jesse Barnes
> Date: Tue Jan 3 08:05:39 2012 -0800
>
> drm/i915: add color key support v4
>
> Cc: sta...@vger.kernel.org
>
> BR,
> Jani.
>
&
On 03/26/2015 06:22 AM, Daniel Vetter wrote:
> On Mon, Mar 23, 2015 at 12:13:56PM +, John Harrison wrote:
>> On 23/03/2015 09:22, Daniel Vetter wrote:
>>> On Fri, Mar 20, 2015 at 09:11:35PM +, Chris Wilson wrote:
On Fri, Mar 20, 2015 at 05:48:36PM +, john.c.harri...@intel.com wrote
On 03/25/2015 06:28 AM, Daniel Vetter wrote:
> On Tue, Mar 24, 2015 at 10:19:59AM +0200, Jani Nikula wrote:
>> On Mon, 23 Mar 2015, Jesse Barnes wrote:
>>> Or users can just spam the log all they want.
>>>
>>> References: https://bugs.freedesktop.org/show_bug.c
On 03/24/2015 04:23 AM, Tvrtko Ursulin wrote:
>
> On 03/23/2015 07:43 PM, Jesse Barnes wrote:
>> Or users can just spam the log all they want.
>>
>> References: https://bugs.freedesktop.org/show_bug.cgi?id=89628
>> Signed-off-by: Jesse Barnes
>> ---
>>
Or users can just spam the log all they want.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89628
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b
5 init time on my BSW to almost half:
> - initcall i915_init+0x0/0xa8 [i915] returned 0 after 419977 usecs
> + initcall i915_init+0x0/0xa8 [i915] returned 0 after 238419 usecs
>
> Note that I didn't perform any other benchmarks on this so far.
>
> Cc: Jesse Barnes
> Sig
On 03/20/2015 10:14 AM, shuang...@intel.com wrote:
> Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
> shuang...@intel.com)
> Task id: 6016
> -Summary-
> Platform Delta drm-intel-nightly
On 03/20/2015 03:16 AM, Daniel Vetter wrote:
> On Thu, Mar 19, 2015 at 11:06:14AM -0700, Jesse Barnes wrote:
>> On 03/19/2015 10:44 AM, Daniel Vetter wrote:
>>> On Wed, Mar 18, 2015 at 11:41:48AM -0700, Jesse Barnes wrote:
>>>> This updates my old patch for this, bu
On 03/19/2015 01:57 PM, Imre Deak wrote:
> On Thu, 2015-03-19 at 13:53 -0700, Jesse Barnes wrote:
>> On 03/17/2015 02:40 AM, Imre Deak wrote:
>>> The checks for PLL enabled state on CPU ports are valid only on GMCH
>>> platforms but atm we'd also call them on non-
On 03/19/2015 01:55 PM, Imre Deak wrote:
> On Thu, 2015-03-19 at 13:34 -0700, Jesse Barnes wrote:
>> On 03/17/2015 02:40 AM, Imre Deak wrote:
>>> Prepare chv_find_best_dpll to be used for BXT too, where we want to
>>> consider the error between target and calculated freq
On 03/17/2015 02:40 AM, Imre Deak wrote:
> The checks for PLL enabled state on CPU ports are valid only on GMCH
> platforms but atm we'd also call them on non-PCH-split/non-GMCH
> platforms like BXT, triggering false warnings. Until the proper check is
> implented for these platforms simply disable
found:
>
> if (IS_SKYLAKE(dev) && is_edp(intel_dp))
> skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
> + else if (IS_BROXTON(dev))
> + /* handled in ddi */;
> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
struct intel_crtc_state *pipe_config)
> @@ -8530,6 +8552,8 @@ static void haswell_get_ddi_port_state(struct
> intel_crtc *crtc,
>
> if (IS_SKYLAKE(dev))
> skylake_get_ddi_pll(dev_priv, port, pipe_config);
> + else if (I
drivers/gpu/drm/i915/intel_drv.h
> @@ -991,6 +991,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
> bool state);
> #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, f
> * Tries to find a *shared* PLL for the CRTC and store it in
> * intel_crtc->ddi_pll_sel.
> @@ -1222,6 +1348,9 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
> if (IS_SKYLAKE(dev))
> return skl_ddi_pll_select(intel_crtc, crtc_state,
>
ntel_drv.h
> @@ -1033,6 +1033,8 @@ int intel_dotclock_calculate(int link_freq, const
> struct intel_link_m_n *m_n);
> void
> ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
> int dotclock);
> +bool bxt_find_best_dpll(st
error_ppm))
> + continue;
> +
> + *best_clock = clock;
> + best_error_ppm = error_ppm;
> + found = true;
> }
> }
>
>
Looking at it again, maybe vlv_PLL_is_bette
unsigned int *error_ppm)
> {
> + if (WARN_ON_ONCE(!target_freq))
> + return false;
> +
> *error_ppm = div_u64(100ULL *
> abs(target_freq - calculated_clock->dot),
>target_freq);
gt;= 10 && ppm < bestppm -
> 10) {
> - bestppm = ppm;
> - *best_clock = clock;
> - found = true;
> -
ality so it can be added later.
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On 03/19/2015 11:53 AM, Ville Syrjälä wrote:
> On Thu, Mar 19, 2015 at 11:40:15AM -0700, Jesse Barnes wrote:
>> On 03/19/2015 11:00 AM, Jesse Barnes wrote:
>>> On 03/19/2015 10:42 AM, Daniel Vetter wrote:
>>>> On Wed, Mar 18, 2015 at 11:41:48AM -0700, Jesse Barnes wr
On 03/19/2015 11:00 AM, Jesse Barnes wrote:
> On 03/19/2015 10:42 AM, Daniel Vetter wrote:
>> On Wed, Mar 18, 2015 at 11:41:48AM -0700, Jesse Barnes wrote:
>>> This updates my old patch for this, but w/o fixing the locking issue
>>> Ville mentioned. In looking at it, i
On 03/19/2015 10:44 AM, Daniel Vetter wrote:
> On Wed, Mar 18, 2015 at 11:41:48AM -0700, Jesse Barnes wrote:
>> This updates my old patch for this, but w/o fixing the locking issue
>> Ville mentioned. In looking at it, it seems like the sync point should
>> be at a highe
On 03/19/2015 10:42 AM, Daniel Vetter wrote:
> On Wed, Mar 18, 2015 at 11:41:48AM -0700, Jesse Barnes wrote:
>> This updates my old patch for this, but w/o fixing the locking issue
>> Ville mentioned. In looking at it, it seems like the sync point should
>> be at a highe
This helps speed up driver init time, and puts off the eDP stuff until
we actually need it.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_dp.c | 103 ++-
drivers/gpu/drm/i915/intel_drv.h | 3 ++
2 files changed, 73 insertions(+), 33 deletions
This updates my old patch for this, but w/o fixing the locking issue
Ville mentioned. In looking at it, it seems like the sync point should
be at a higher level, maybe at the level of the atomic mode setting async
serialization points? Another possibility would be to make it a lazy
init type func
>>> Yeah we'll rebind if needed. We can make this an execbuf or context
>>> flag, in either case anything that gets executed by ocl will be moved
>>> around if it accidentally ended up at the wrong place. The only
>>> exception is if a buffer is pinned already, i.e. if you're doing
>>> direct rende
On 03/16/2015 01:52 AM, Daniel Vetter wrote:
> On Mon, Mar 16, 2015 at 02:29:24AM +, Song, Ruiling wrote:
>>
>>
>>> -Original Message-
>>> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
>>> Vetter
>>> Sent: Saturday, March 14, 2015 1:14 AM
>>> To: Chris Wilson;
On 03/16/2015 01:52 AM, Daniel Vetter wrote:
> On Mon, Mar 16, 2015 at 02:29:24AM +, Song, Ruiling wrote:
>>
>>
>>> -Original Message-
>>> From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
>>> Vetter
>>> Sent: Saturday, March 14, 2015 1:14 AM
>>> To: Chris Wilson;
On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
> From: Akash Goel
>
> This patch series add the missing changes, required for proper
> functioning of the Turbo feature on SKL. Most of the changes are
> mainly due to the fact that on SKL, the frequency has to be programmed
> in units of 16.66
On 03/12/2015 11:36 AM, Jani Nikula wrote:
> On Thu, 12 Mar 2015, Jesse Barnes wrote:
>> On 02/11/2015 09:43 AM, Damien Lespiau wrote:
>>> v2: Use the recently introduced INTEL_REVID() and SKL_REVID defines
>>> (Nick Hoath)
>>>
>>> Signed-off-by:
/* WaDisableHBR2:skl */
> + max_link_bw = DP_LINK_BW_2_7;
> + else if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
>INTEL_INFO(dev)->gen >= 8) &&
> intel_dp->dpcd[DP_DPCD_REV] >
On 03/11/2015 12:46 PM, Chris Wilson wrote:
> On Wed, Mar 11, 2015 at 12:27:59PM -0700, Jesse Barnes wrote:
>> On 03/05/2015 09:37 PM, akash.g...@intel.com wrote:
>>> + /* Leaning on the below call to gen6_set_rps to program/setup the
>>> +* Up/Down EI & thre
& DSPFW_SPRITEC_HI_MASK) |
> -(((wm->pipe[PIPE_B].primary >> 8) <<
> DSPFW_PLANEB_HI_SHIFT) & DSPFW_PLANEB_HI_MASK) |
> -(((wm->pipe[PIPE_A].sprite[1] >> 8) <<
> DSPFW_SPRITEB_HI_SH
;state->crtc_w != state->base.crtc_w)
> intel_crtc->atomic.update_wm = true;
>
> intel_crtc->atomic.fb_bits |=
>
At least it looks like we'll always get the right plane obj here. :)
Reviewed-by: Jesse Barnes
__
INFO(dev)->gen < 9)
> - gen6_enable_rps_interrupts(dev);
> + gen6_enable_rps_interrupts(dev);
>
> mutex_unlock(&dev_priv->rps.hw_lock);
>
>
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_priv->rps.min_freq_softlimit);
>
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> }
>
I'm assuming these match the latest SKL PM bits, but either way can be
updated later based on tuning.
Reviewed-by: Jesse Barnes
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spin_lock(&dev_priv->irq_lock);
> gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
>
Reviewed-by: Jesse Barnes
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On 03/09/2015 02:04 PM, Ville Syrjälä wrote:
> On Mon, Mar 09, 2015 at 12:07:31PM -0700, Jesse Barnes wrote:
>> On 03/09/2015 10:29 AM, Daniel Vetter wrote:
>>> On Mon, Mar 09, 2015 at 08:34:49AM -0700, Jesse Barnes wrote:
>>>> On 03/06/2015 08:34 AM, Daniel Vett
On 03/11/2015 09:14 AM, Daniel Vetter wrote:
> On Wed, Mar 11, 2015 at 02:53:39PM +, John Harrison wrote:
>> On 05/03/2015 14:49, Daniel Vetter wrote:
>>> On Thu, Mar 05, 2015 at 01:57:31PM +, john.c.harri...@intel.com wrote:
From: John Harrison
The LRC submission code requi
-(8 << DSPFW_PLANEA_SHIFT));
> - I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) |
> -(8 << DSPFW_PLANEC_SHIFT_OLD));
> + I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
> +FW_WM(8, CURSORB) |
> +FW_WM(8
ry_plane(struct
> drm_crtc *crtc,
>
> I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
>
> - DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
> - i915_gem_obj_ggtt_offset(obj),
> - x, y, fb->width, fb->height,
> -
On 03/09/2015 10:29 AM, Daniel Vetter wrote:
> On Mon, Mar 09, 2015 at 08:34:49AM -0700, Jesse Barnes wrote:
>> On 03/06/2015 08:34 AM, Daniel Vetter wrote:
>>> On Thu, Mar 05, 2015 at 11:22:19AM -0700, Todd Previte wrote:
>>>> + } else {
>>>> +
On 03/09/2015 08:46 AM, Jesse Barnes wrote:
> On 03/05/2015 01:07 PM, Chris Wilson wrote:
>> On Thu, Mar 05, 2015 at 04:27:59PM +0100, Daniel Vetter wrote:
>>> I recommended exposing the PIN_BIAS since that will work without full
>>> ppgtt too. And yeah for full ppgtt
On 03/05/2015 01:07 PM, Chris Wilson wrote:
> On Thu, Mar 05, 2015 at 04:27:59PM +0100, Daniel Vetter wrote:
>> I recommended exposing the PIN_BIAS since that will work without full
>> ppgtt too. And yeah for full ppgtt we could just use svm where userspace
>> controls the address, but since that's
On 03/06/2015 08:34 AM, Daniel Vetter wrote:
> On Thu, Mar 05, 2015 at 11:22:19AM -0700, Todd Previte wrote:
>> Update the hot plug function to handle the SST case. Instead of placing
>> the SST case within the long/short pulse block, it is now handled after
>> determining that MST mode is not in u
On 03/06/2015 07:06 AM, Chris Wilson wrote:
> When we idle, we set the GPU frequency to the hardware minimum (not user
> minimum). We introduce a new variable to distinguish between the
> different roles, and to allow easy tuning of the idle frequency without
> impacting over aspects of RPS. Settin
On 03/09/2015 02:03 AM, Daniel Vetter wrote:
> On Sat, Mar 07, 2015 at 12:09:08AM +, Damien Lespiau wrote:
>> On Fri, Mar 06, 2015 at 03:53:32PM -0800, Jesse Barnes wrote:
>>> So try to enumerate eDP unconditionally in those cases.
>>>
>>> Signe
So try to enumerate eDP unconditionally in those cases.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 597c10b
On 03/06/2015 10:14 AM, Ville Syrjälä wrote:
> On Fri, Mar 06, 2015 at 09:31:20AM -0800, Jesse Barnes wrote:
>> On 03/05/2015 11:19 AM, ville.syrj...@linux.intel.com wrote:
>>> From: Ville Syrjälä
>> I wonder if we should be warning if the wm values we end up with exce
nabled)
> intel_set_memory_cxsr(dev_priv, true);
> @@ -1002,17 +995,44 @@ static void valleyview_update_sprite_wm(struct
> drm_plane *plane,
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum pipe pipe = intel_crtc->pipe;
> int sprite = to
>
> + /*
> + * FIXME DDR DVFS introduces massive memory latencies which
> + * are not known to system agent so any deadline specified
> + * by the display may not be respected. To support DDR DVFS
> + * the watermark code needs to be r
On 03/04/2015 02:40 PM, Jesse Barnes wrote:
> I need this on my machine or eDP doesn't come up.
>
> Signed-off-by: Jesse Barnes
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/
I need this on my machine or eDP doesn't come up.
Signed-off-by: Jesse Barnes
---
drivers/gpu/drm/i915/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 480dd79..74
On 03/04/2015 12:56 AM, Chris Wilson wrote:
> On Tue, Mar 03, 2015 at 04:27:47PM -0800, Jesse Barnes wrote:
>> My "rant du jour" still is. mlock() is a good solution for some things,
>> but for the simple task of testing kernel swap out code, just running
>> that c
On 03/03/2015 04:06 PM, Daniel Vetter wrote:
> On Tue, Mar 3, 2015 at 10:15 PM, Chris Wilson
> wrote:
>> On Tue, Mar 03, 2015 at 11:23:53AM -0800, Jesse Barnes wrote:
>>> On 03/03/2015 09:03 AM, Daniel Vetter wrote:
>>>> This is useful for writing igts
On 03/03/2015 09:03 AM, Daniel Vetter wrote:
> This is useful for writing igts to make sure we don't break this,
> without being forced to own a one of these dinosaurs.
>
> Suggested-by: Jesse Barnes
> Cc: Matt Roper
> Signed-off-by: Daniel Vetter
> ---
> dr
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