On Tue, 2020-04-14 at 14:11 -0700, Matt Roper wrote:
> Even though the bspec is missing gen12 register details for the MCR
> selector register (0xFDC), this is confirmed by hardware folks to be
> a
> mistake; the register does exist and we do indeed need to steer
> multicast register reads to an
On Tue, 2020-04-14 at 14:11 -0700, Matt Roper wrote:
> Media decompression support should not be advertised on any display
> planes for steppings A0-C0.
Reviewed-by: José Roberto de Souza
>
> Bspec: 53273
> Fixes: 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress
> surfaces compressed
On Tue, 2020-04-14 at 14:11 -0700, Matt Roper wrote:
> Cc: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>
Reviewed-by: José Roberto de Souza
On Tue, 2020-04-14 at 14:11 -0700, Matt Roper wrote:
> Cc: Matt Atwood
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Tue, 2020-04-14 at 21:29 +0300, Imre Deak wrote:
> On Mon, Apr 13, 2020 at 09:45:15AM -0700, José Roberto de Souza
> wrote:
> > The intel_display_power_put_async() used in TC cold sequences made
> > easy to hit the missing deinitialization of driver in case of load
> > failure as seen in the
On Tue, 2020-04-14 at 20:47 +0300, Imre Deak wrote:
> On Mon, Apr 13, 2020 at 09:45:14AM -0700, José Roberto de Souza
> wrote:
> > This is a expected timeout of static TC ports not conneceted, so
> > not throwing warnings that would taint CI.
> >
> > v3:
> > - moved checks to
On Tue, 2020-04-14 at 20:39 +0300, Imre Deak wrote:
> On Mon, Apr 13, 2020 at 09:45:12AM -0700, José Roberto de Souza
> wrote:
> > TC ports can enter in TCCOLD to save power and is required to
> > request
> > to PCODE to exit this state before use or read to TC registers.
> >
> > For TGL there is
On Fri, 2020-04-10 at 15:43 +0100, Chris Wilson wrote:
> Flush the async power domain work after aborting the module probe:
>
> <3> [307.785552] ODEBUG: free active (active state 0) object type:
> timer_list hint: intel_display_power_put_async_work+0x0/0xf0 [i915]
>
> Closes:
On Wed, 2020-04-08 at 01:03 +0300, Imre Deak wrote:
> On Tue, Apr 07, 2020 at 02:39:56PM -0700, José Roberto de Souza
> wrote:
> > This is required for legacy/static TC ports as IOM is not aware of
> > the connection and will not trigger the TC cold exit.
> >
> > Just request PCODE to exit TCCOLD
On Tue, 2020-04-07 at 10:28 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/8] drm/i915/display: Move out code
> to return the digital_port of the aux ch
> URL : https://patchwork.freedesktop.org/series/75576/
> State : failure
>
> == Summary ==
>
> CI
On Tue, 2020-04-07 at 19:02 +0300, Imre Deak wrote:
> On Mon, Apr 06, 2020 at 06:11:55PM -0700, José Roberto de Souza
> wrote:
> > TC ports can enter in TCCOLD to save power and is required to
> > request
> > to PCODE to exit this state before use or read to TC registers.
> >
> > For TGL there is
On Tue, 2020-04-07 at 18:42 +0300, Imre Deak wrote:
> On Mon, Apr 06, 2020 at 06:11:53PM -0700, José Roberto de Souza
> wrote:
> > This is required for legacy/static TC ports as IOM is not aware of
> > the connection and will not trigger the TC cold exit.
> >
> > Just request PCODE to exit TCCOLD
/tree/drm-tip/Trybot_5784/bat-all.html
Thanks
On Thu, 2020-04-02 at 04:02 +0300, Imre Deak wrote:
> On Thu, Apr 02, 2020 at 01:35:30AM +0300, Souza, Jose wrote:
> > On Wed, 2020-04-01 at 15:43 +0300, Imre Deak wrote:
> > > On Tue, Mar 31, 2020 at 05:41:19PM -0700, José Roberto de
On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Move the final DP_TP_CTL frobbing of port sync to the master
> encoder's enable hook. Now neatly out of sight from the high level
> modeset code.
>
> And thus we've eliminated all the special casing of port sync
>
On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently only port sync pipes do the sequence such that
> we first do the modeset part for every pipe and then do
> the plane/etc. updates. Let's follow that apporach for
> all pipes in skl+ so that we can
On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Don't assume there is just one port sync slave. We might have
> several.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 98 ++--
>
> 1 file changed, 49
On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Remove the copy pasted port sync crtc enable functions and instead
> just split the normal function into the two parts we need.
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Ville Syrjälä
> ---
>
On Fri, 2020-03-13 at 18:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're going to want access to the atomic state for iterating
> the slave crtcs when enabling the port sync master crtc. Pass
> the atomic state all the way down.
>
> The alternative would be yet another encoder
On Wed, 2020-03-18 at 19:02 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We have a bunch of code that would like to know which
> CPU transcoders are actually present in the hardware. Rather than
> use various ad-hoc methods let's just include a full bitmask in
> the device info,
On Wed, 2020-04-01 at 15:55 +0300, Imre Deak wrote:
> On Tue, Mar 31, 2020 at 05:41:20PM -0700, José Roberto de Souza
> wrote:
> > TC ports can enter in TCCOLD to save power and is required to
> > request
> > to PCODE to exit this state before use or read to TC registers.
> >
> > For TGL there is
On Wed, 2020-04-01 at 15:43 +0300, Imre Deak wrote:
> On Tue, Mar 31, 2020 at 05:41:19PM -0700, José Roberto de Souza
> wrote:
> > This is required for legacy/static TC ports as IOM is not aware of
> > the connection and will not trigger the TC cold exit.
> >
> > Just request PCODE to exit TCCOLD
On Wed, 2020-04-01 at 15:18 +0800, You-Sheng Yang wrote:
> On 2020-04-01 08:41, José Roberto de Souza wrote:
> > Moving the code to return the digital port of the aux channel also
> > removing the intel_phy_is_tc() to make it generic.
> > digital_port will be needed in
On Tue, 2020-03-31 at 10:41 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/3] drm/i915/dp: Return the right
> vswing tables
> URL : https://patchwork.freedesktop.org/series/75268/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from
On Sat, 2020-03-28 at 12:26 +0200, Imre Deak wrote:
> On Tue, Mar 24, 2020 at 01:14:29PM -0700, José Roberto de Souza
> wrote:
> > As now the cost to lock and use a TC port is higher due the
> > implementation of the TCCOLD sequences it is worty to hold a
> > reference
> > of the TC port to avoid
On Sat, 2020-03-28 at 11:57 +0200, Imre Deak wrote:
> Hi José,
>
> On Tue, Mar 24, 2020 at 01:14:24PM -0700, José Roberto de Souza
> wrote:
> > TC ports can enter in TCCOLD to save power and is required to
> > request
> > to PCODE to exit this state before use or read to TC registers.
> >
> >
On Mon, 2020-03-30 at 17:50 +0300, Ville Syrjälä wrote:
> On Fri, Mar 27, 2020 at 02:34:11PM -0700, José Roberto de Souza
> wrote:
> > DDI ports have its encoders initialized with INTEL_OUTPUT_DDI type
> > and
> > later eDP ports that have the type changed to INTEL_OUTPUT_EDP.
> > But for all
On Mon, 2020-03-30 at 12:54 +0300, Imre Deak wrote:
> On TypeC ports if a sink deasserts/reasserts its HPD signal,
> generating
> a hotplug interrupt without the sink getting unplugged/replugged from
> the connector, there can be an up to 3 seconds delay until the AUX
> channel gets functional. To
On Mon, 2020-03-30 at 18:22 +0300, Imre Deak wrote:
> The DDI IO power well must not be enabled for a TypeC port in TBT
> mode,
> ensure this during driver loading/system resume.
>
> This gets rid of error messages like
> [drm] *ERROR* power well DDI E TC2 IO state mismatch (refcount
> 1/enabled
On Tue, 2020-03-24 at 20:28 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v3,1/6] drm/i915/tc/tgl: Implement
> TCCOLD sequences
> URL : https://patchwork.freedesktop.org/series/75034/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
>
Never mind, read the code again it will work.
Reviewed-by: José Roberto de Souza
On Fri, 2020-03-20 at 23:37 +, Souza, Jose wrote:
> This will not work for MST, here a example
>
> Previous state:
> MST master pipe A
> MST slave pipe B
>
> New state:
&g
This will not work for MST, here a example
Previous state:
MST master pipe A
MST slave pipe B
New state:
Pipe A being disabled
On drm_atomic_helper_check_modeset() both intel_crtc_states will be
added to the state with crtc_state->uapi.mode_changed=true.
Then on the regular
On Fri, 2020-03-20 at 20:07 +, Souza, Jose wrote:
> On Fri, 2020-03-20 at 00:20 +, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/display/fbc: Make fences a nice-to-have for GEN9+
> > URL : https://patchwork.freedesktop.org/series
On Fri, 2020-03-20 at 00:20 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display/fbc: Make fences a nice-to-have for GEN9+
> URL : https://patchwork.freedesktop.org/series/74890/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8160_full ->
On Fri, 2020-03-20 at 16:11 +0300, Dan Carpenter wrote:
> Hi "José,
>
> Thank you for the patch! Perhaps something to improve:
>
> url:
> https://github.com/0day-ci/linux/commits/Jos-Roberto-de-Souza/drm-i915-tc-tgl-Implement-TCCOLD-sequences/20200319-080253
> base:
On Wed, 2020-03-18 at 14:44 +0200, Ville Syrjälä wrote:
> On Thu, Mar 12, 2020 at 12:35:56AM +0000, Souza, Jose wrote:
> > On Thu, 2020-03-05 at 17:33 -0800, José Roberto de Souza wrote:
> > > On Thu, 2020-02-20 at 19:26 +0200, Ville Syrjälä wrote:
> > > > On Tue, Fe
On Wed, 2020-03-18 at 15:30 +0200, Ville Syrjälä wrote:
> On Fri, Mar 06, 2020 at 01:32:12AM +0000, Souza, Jose wrote:
> > On Thu, 2020-02-20 at 19:26 +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 18, 2020 at 05:42:30PM -0800, José Roberto de Souza
> > > wrote:
> &
On Wed, 2020-03-18 at 17:00 +0530, Uma Shankar wrote:
> If external monitors are connected during boot up, driver
> uses the same mode programmed by BIOS and avoids a full modeset.
> This results in display audio codec left uninitialized and
> display audio fails to work till user triggers a
Hi
Please test with drm-tip and file a bug attaching more information
and logs:
https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs
On Tue, 2020-03-17 at 18:56 +, Damian Hischier wrote:
> Hello
>
> I installed opensuse Tumbleweed linux on a brand new Dell XPS-13-
> 7390.
On Thu, 2020-02-20 at 19:03 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Remove require_force_probe protection
> URL : https://patchwork.freedesktop.org/series/73613/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7963_full ->
On Wed, 2020-03-11 at 09:22 -0700, Matt Roper wrote:
> The bspec description for this workaround tells us to program
> 0x_ into both FBC_RT_BASE_ADDR_REGISTER_* registers, but
> we've
> previously found that this leads to failures in CI. Our suspicion is
> that the failures are caused by
On Thu, 2020-03-12 at 15:08 -0700, José Roberto de Souza wrote:
> On Wed, 2020-03-11 at 09:22 -0700, Matt Roper wrote:
> > v2:
> > - Move to context workarounds. ROW_CHICKEN4 is part of the
> > context
> >image on gen11 (although it isn't on gen12).
> >
> > Signed-off-by: Matt Roper
> >
On Thu, 2020-03-12 at 15:07 -0700, Lucas De Marchi wrote:
> On Wed, Mar 04, 2020 at 05:04:52PM -0800, Lucas De Marchi wrote:
> > On Wed, Mar 4, 2020 at 2:33 PM Caz Yokoyama > > wrote:
> > > This reverts commit 36a6b5d964d995b536b1925ec42052ee40ba92c4.
> > > Fixes: 36a6b5d964d9 ("drm/i915/tgl: Add
On Wed, 2020-03-11 at 09:22 -0700, Matt Roper wrote:
> v2:
> - Move to context workarounds. ROW_CHICKEN4 is part of the context
>image on gen11 (although it isn't on gen12).
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
>
On Wed, 2020-03-11 at 09:22 -0700, Matt Roper wrote:
> On gen11 the XY_FAST_COPY_BLT command has some size restrictions on
> its
> usage. Although this instruction is mainly used by userspace, i915
> also
> uses it to copy object contents during some selftests, so let's
> ensure
> the
On Thu, 2020-03-05 at 17:33 -0800, José Roberto de Souza wrote:
> On Thu, 2020-02-20 at 19:26 +0200, Ville Syrjälä wrote:
> > On Tue, Feb 18, 2020 at 05:42:30PM -0800, José Roberto de Souza
> > wrote:
> > > dGFX have local memory so it do not have aperture and do not
> > > support
> > > CPU fences
On Tue, 2020-03-10 at 17:30 +, Patchwork wrote:
> == Series Details ==
>
> Series: Gen11 workarounds
> URL : https://patchwork.freedesktop.org/series/74475/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8106 -> Patchwork_16900
>
On Tue, 2020-03-10 at 22:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Not sure why this thing is trying to avoid declaring the proper
> type for these pointers. But since these are used only once let's
> just get rid of the local variable entirely.
Reviewed-by: José Roberto de Souza
On Tue, 2020-03-10 at 18:13 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v2,1/2] drm/i915/display: Deactive FBC
> in fastsets when disabled by parameter (rev2)
> URL : https://patchwork.freedesktop.org/series/74401/
> State : success
>
> == Summary ==
>
>
On Fri, 2020-03-06 at 20:03 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Make wa_1606700617 permanent (rev2)
> URL : https://patchwork.freedesktop.org/series/74240/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8073_full ->
On Fri, 2020-03-06 at 03:01 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/hotplug: Use phy to get the hpd_pin instead of the
> port (rev6)
> URL : https://patchwork.freedesktop.org/series/72747/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from
On Thu, 2020-03-05 at 10:12 -0800, Swathi Dhanavanthri wrote:
> This workaround is to disable FF DOP Clock gating. The fix
> in B0 was backed out due to timing reasons and decided to
> be made permanent.
> Bspec: 52890
Reviewed-by: José Roberto de Souza
>
> Signed-off-by: Swathi Dhanavanthri
On Thu, 2020-02-20 at 19:26 +0200, Ville Syrjälä wrote:
> On Tue, Feb 18, 2020 at 05:42:30PM -0800, José Roberto de Souza
> wrote:
> > dGFX have local memory so it do not have aperture and do not
> > support
> > CPU fences but even for iGFX it have a small number of fences.
> >
> > As replacement
On Wed, 2020-02-19 at 20:52 +0200, Ville Syrjälä wrote:
> On Wed, Feb 19, 2020 at 06:37:27PM +0000, Souza, Jose wrote:
> > On Wed, 2020-02-19 at 15:37 +0200, Ville Syrjälä wrote:
> > > On Tue, Feb 18, 2020 at 05:42:28PM -0800, José Roberto de Souza
> &g
On Thu, 2020-03-05 at 12:24 -0800, Matt Roper wrote:
> The UNSLICE_UNIT_LEVEL_CLKGATE and UNSLICE_UNIT_LEVEL_CLKGATE2
> registers
> that we update in a few engine workarounds are not masked registers
> (i.e., we don't have to write a mask bit in the top 16 bits when
> updating one of the lower 16
On Wed, 2020-03-04 at 17:09 +0200, Imre Deak wrote:
> Fix the following kerneldoc warning and while at it also the doc for
> the
> corresponding vfunc hook.
>
> $ make htmldocs 2>&1 > /dev/null | grep i915
> ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning:
> Function parameter or
On Tue, 2020-03-03 at 09:20 +, Chris Wilson wrote:
> Update locations for
>
> ./drivers/gpu/drm/i915/i915_vma.h:1: warning: 'Virtual Memory
> Address' not found
> ./drivers/gpu/drm/i915/i915_gem_gtt.c:1: warning: 'Global GTT views'
> not found
Reviewed-by: José Roberto de Souza
>
>
On Wed, 2020-03-04 at 13:46 +0200, Ville Syrjälä wrote:
> On Wed, Mar 04, 2020 at 12:21:01AM +0000, Souza, Jose wrote:
> > On Fri, 2020-02-28 at 22:35 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Currently we're comparing the watermarks
The change look good, it is just missing some commit description. I
know that there is no much to talk about but it is kind of a rule to
always have a description on kernel patches, something like will do:
Previously the issue that Wa_1606700617 was fixing would be fixed in B0
hardware but
On Fri, 2020-02-28 at 22:35 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we're comparing the watermarks between the old and new
> states
> before we've fully computed the new watermarks. In particular
> skl_build_pipe_wm() will not account for the amount of ddb space
> we'll
>
On Fri, 2020-02-28 at 22:35 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The hardware never sees the uv_wm values (apart from
> uv_wm.min_ddb_alloc affecting the ddb allocation). Thus there
> is no point in comparing uv_wm to determine if we need to
> reprogram the watermark registers.
On Tue, 2020-03-03 at 12:21 -0800, Matt Roper wrote:
> On Mon, Mar 02, 2020 at 03:14:21PM -0800, José Roberto de Souza
> wrote:
> > Following the changes in the previous patch
> > "drm/i915/gen11: Moving WAs to rcs_engine_wa_init()" also moving
> > TGL
> > Wa_1408615072 to rcs_engine_wa_init()
On Tue, 2020-03-03 at 12:39 -0800, Rodrigo Vivi wrote:
> On Tue, Mar 03, 2020 at 12:26:34PM -0800, Lucas De Marchi wrote:
> > On Tue, Feb 18, 2020 at 3:07 PM José Roberto de Souza
> > wrote:
> > > We have a few TGL machines in our CI and it is mostly green with
> > > failures in tests that will
On Sat, 2020-02-29 at 12:07 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [v3,01/11] drm/i915/tgl: Implement
> Wa_1409804808
> URL : https://patchwork.freedesktop.org/series/74044/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
On Mon, 2020-03-02 at 11:49 +0200, Arkadiusz Hiler wrote:
> On Fri, Feb 28, 2020 at 06:52:01PM +0000, Souza, Jose wrote:
> > On Fri, 2020-02-28 at 12:21 +0200, Petri Latvala wrote:
> > > On Thu, Feb 27, 2020 at 11:42:03PM +, Souza, Jose wrote:
> > > > The
On Fri, 2020-02-28 at 16:29 -0800, Matt Roper wrote:
> On Fri, Feb 28, 2020 at 04:04:17PM -0800, Souza, Jose wrote:
> > On Fri, 2020-02-28 at 13:25 -0800, Matt Roper wrote:
> > > On Thu, Feb 27, 2020 at 02:00:59PM -0800, José Roberto de Souza
> > > wrote:
> &g
On Fri, 2020-02-28 at 13:25 -0800, Matt Roper wrote:
> On Thu, Feb 27, 2020 at 02:00:59PM -0800, José Roberto de Souza
> wrote:
> > It is fixed in B0 stepping.
> >
> > Signed-off-by: José Roberto de Souza
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> > 1 file changed, 3
Can you guys help in this one? Check Matt comment bellow.
On Fri, 2020-02-28 at 14:07 -0800, Matt Roper wrote:
> On Thu, Feb 27, 2020 at 02:01:01PM -0800, José Roberto de Souza
> wrote:
> > This will fix a memory coherence issue.
> >
> > v3: using whitespace to make easy to read WA (Chris)
> >
On Fri, 2020-02-28 at 12:21 +0200, Petri Latvala wrote:
> On Thu, Feb 27, 2020 at 11:42:03PM +0000, Souza, Jose wrote:
> > The following changes since commit
> > efcfa03ae6100dfe523ebf612e03c3a90fc4c794:
> >
> > linux-firmware: Update firmware file for Intel Bluetooth
On Thu, 2020-02-27 at 14:44 -0800, Daniele Ceraolo Spurio wrote:
> Update to the latest available TGL HuC, which includes changes
> required
> by the media team.
>
Reviewed-by: José Roberto de Souza
> Requested-by: Tony Ye
> Signed-off-by: Daniele Ceraolo Spurio <
>
The following changes since commit
efcfa03ae6100dfe523ebf612e03c3a90fc4c794:
linux-firmware: Update firmware file for Intel Bluetooth AX201 (2020-
02-24 07:43:42 -0500)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-firmware tgl_dmc_2.06
for you to fetch
On Wed, 2020-02-26 at 16:02 -0800, Lucas De Marchi wrote:
> On Tue, Feb 25, 2020 at 5:45 PM José Roberto de Souza
> wrote:
> > Spliting GT and display revisions id to correctly apply workarounds
> > because we have some issues that were fixed in display B0 but no
> > hardware was made with B0
On Wed, 2020-02-26 at 18:30 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Looks like the pipe rounding mode bit has moved from PIPE_CHICKEN to
> PIPE_MISC on tgl. Frob the new location.
>
> Bspec does still document the old bits as well, so I left the code
> for them as is until we get
Hi Hans
Just commenting in the "[3.309061] [drm:intel_dump_pipe_config
[i915]] MST master transcoder: " message, it is the expected
behaviour for anything older than Tigerlake, from TGL+ this will be set
in MST mode.
On Wed, 2020-02-26 at 18:52 +0100, Hans de Goede wrote:
> Hi,
>
> On
On Mon, 2020-02-24 at 14:36 -0800, Matt Roper wrote:
> From: Matt Atwood
>
> On Tiger Lake we do not support source keying in the pixel formats
> P010,
> P012, P016.
>
> v2: Move WA to end of function. Create helper function for format
> check. Less verbose debugging messaging.
>
> v3:
On Thu, 2020-02-20 at 15:18 -0800, Matt Roper wrote:
> On gen12, we no longer need to disable DC5/DC6 when when PG2 is in
> use
> (which translates to cases where we're using VDSC on pipe A).
>
> Bspec: 49193
Reviewed-by: José Roberto de Souza
> Cc: Lucas De Marchi
> Cc: José Roberto de Souza
Ouch! Thanks fixed
On Sat, 2020-02-22 at 08:53 +, Chris Wilson wrote:
> Quoting José Roberto de Souza (2020-02-22 02:08:10)
> > This will whitelist the HIZ_CHICKEN register so mesa can disable
> > the
> > optimizations and void hang when using D16_UNORM.
>
> But it's not added to the
On Mon, 2020-02-24 at 08:08 -0800, Matt Roper wrote:
> On Fri, Feb 21, 2020 at 06:08:08PM -0800, José Roberto de Souza
> wrote:
> > This workaround is only fixed in C0 stepping to extend it to B0
> > too.
> >
> > BSpec: 52890
> > Cc: Radhakrishna Sripada
> > Signed-off-by: José Roberto de Souza
On Mon, 2020-02-24 at 15:02 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/psr: Force PSR probe only after full initialization
> (rev7)
> URL : https://patchwork.freedesktop.org/series/73436/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from
+ CCing people involved in the patch fixed.
On Fri, 2020-02-21 at 16:28 -0800, Lucas De Marchi wrote:
> Wa_1608008084 is an additional WA that applies to writes on FF_MODE2
> register. We can't read it back either from CPU or GPU. Since the
> other
> bits should be 0, recommendation to handle
On Fri, 2020-02-21 at 20:04 +, Mun, Gwan-gyeong wrote:
> On Thu, 2020-02-20 at 15:15 -0800, José Roberto de Souza wrote:
> > Commit 60c6a14b489b ("drm/i915/display: Force the state compute
> > phase
> > once to enable PSR") was forcing the state compute too earlier
> > causing errors because
On Fri, 2020-02-21 at 15:46 +, Mun, Gwan-gyeong wrote:
> On Thu, 2020-02-20 at 12:55 -0800, Souza, Jose wrote:
> > On Thu, 2020-02-20 at 12:39 +, Mun, Gwan-gyeong wrote:
> > > On Tue, 2020-02-18 at 12:39 -0800, José Roberto de Souza wrote:
> > > > Commit 6
We have a fix for this issue, still going through review.
https://gitlab.freedesktop.org/drm/intel/issues/1151
On Fri, 2020-02-21 at 11:38 +1000, Dave Airlie wrote:
> looping in intel-gfx + Jani.
>
> On Tue, 18 Feb 2020 at 05:20, sinisa wrote:
> >
> > On 2020-02-16 22:32, Linus Torvalds
On Thu, 2020-02-20 at 09:41 +0530, Anshuman Gupta wrote:
> On 2020-02-18 at 23:53:28 +0530, José Roberto de Souza wrote:
> > Commit 60c6a14b489b ("drm/i915/display: Force the state compute
> > phase
> > once to enable PSR") was forcing the state compute too earlier
> > causing errors because not
On Thu, 2020-02-20 at 12:39 +, Mun, Gwan-gyeong wrote:
> On Tue, 2020-02-18 at 12:39 -0800, José Roberto de Souza wrote:
> > Commit 60c6a14b489b ("drm/i915/display: Force the state compute
> > phase
> > once to enable PSR") was forcing the state compute too earlier
> > causing errors because
On Wed, 2020-02-19 at 13:56 -0800, Matt Roper wrote:
> We need to explicitly set the TLB Request Timer initial value in the
> BW_BUDDY registers to 0x8 rather than relying on the hardware
> default.
>
> v2: Apply missing REG_FIELD_PREP to ensure 0x8 is placed in the
> correct
> bits during
On Mon, 2020-02-10 at 12:28 -0800, Matt Roper wrote:
> We need to explicitly set the TLB Request Timer initial value in the
> BW_BUDDY registers to 0x8 rather than relying on the hardware
> default.
>
> Bspec: 52890
> Bspec: 50044
> Cc: Stanislav Lisovskiy
> Signed-off-by: Matt Roper
> ---
>
On Wed, 2020-02-19 at 15:37 +0200, Ville Syrjälä wrote:
> On Tue, Feb 18, 2020 at 05:42:28PM -0800, José Roberto de Souza
> wrote:
> > Most of the kms_frontbuffer_tracking tests disables the feature
> > being
> > tested, draw, get the CRC then enable the feature, draw again, get
> > the
> > CRC
On Tue, 2020-02-11 at 18:12 +0200, Jani Nikula wrote:
> On Mon, 10 Feb 2020, Jani Nikula wrote:
> > On Mon, 10 Feb 2020, José Roberto de Souza
> > wrote:
> > > Commit 1c9d2eb24153 ("drm/i915: move intel_dp_set_m_n() to
> > > encoder for
> > > DDI platforms") moved the intel_dp_set_m_n() from
> >
On Sat, 2020-02-08 at 12:22 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dc3co: Add description of how it works
> URL : https://patchwork.freedesktop.org/series/73058/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7871_full ->
On Sat, 2020-02-08 at 11:25 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display/ehl: Add HBR2 and HBR3 voltage swing table
> URL : https://patchwork.freedesktop.org/series/73055/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7871_full ->
On Thu, 2020-02-06 at 15:46 +0200, Ville Syrjälä wrote:
> On Wed, Feb 05, 2020 at 06:08:49PM -0800, José Roberto de Souza
> wrote:
> > dGFX have local memory so it do not have aperture and do not
> > support
> > CPU fences but even for iGFX it have a small number of fences.
> >
> > As replacement
On Thu, 2020-02-06 at 16:14 -0800, Matt Roper wrote:
> A recent bspec update added an extra voltage level that we didn't
> have
> on ICL and new criteria for selecting the level.
Reviewed-by: José Roberto de Souza
>
> Bspec: 49208
> Cc: José Roberto de Souza
> Cc: Anusha Srivatsa
>
On Thu, 2020-02-06 at 16:14 -0800, Matt Roper wrote:
> Voltage level depends not only on the cdclk, but also on the DDI
> clock.
> Last time the bspec voltage level table for EHL was updated, we only
> updated the cdclk requirements, but forgot to account for the new
> port
> clock criteria.
>
On Thu, 2020-02-06 at 19:28 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/display: Set TRANS_DDI_MODE_SELECT to default value
> when clearing DDI select
> URL : https://patchwork.freedesktop.org/series/72943/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes
Hi Ross
I'm unable to reproduce this issue, could you share the complete dmesg?
On Wed, 2020-02-05 at 16:01 -0700, Ross Zwisler wrote:
> On Mon, Jan 06, 2020 at 07:21:28AM -0800, José Roberto de Souza
> wrote:
> > Recent improvements in the state tracking in i915 caused PSR to not
> > be
> >
I guess a better solution would be do the HW state sanitization during
the HW readout(intel_modeset_setup_hw_state())
On Tue, 2020-02-04 at 14:44 -0800, Vivek Kasireddy wrote:
> On Tue, 4 Feb 2020 12:50:25 +0200
> Jani Nikula wrote:
> Hi Jani,
>
> > On Mon, 03 Feb 2020, Vivek Kasireddy
> >
On Tue, 2020-02-04 at 22:26 +0200, Ville Syrjälä wrote:
> On Tue, Feb 04, 2020 at 06:18:09PM +0000, Souza, Jose wrote:
> > On Tue, 2020-02-04 at 17:48 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > s/before/after/ again after accident
On Tue, 2020-02-04 at 17:48 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> s/before/after/ again after accidentally changing it the
> other way in commit 5604e9ceaed5 ("drm/i915: Simplify
> intel_set_cdclk_{pre,post}_plane_update() calling convention")
>
> Cc: José Roberto de Souza
>
On Tue, 2020-02-04 at 15:35 +0200, Ville Syrjälä wrote:
> On Mon, Feb 03, 2020 at 02:55:49PM -0800, José Roberto de Souza
> wrote:
> > TGL is suffering of timeouts and fifo underruns when disabling
> > transcoder in MST mode, this is fixed by set TRANS_DDI_MODE_SELECT
> > to
> > 0(HDMI mode) when
On Wed, 2020-01-29 at 13:42 +0200, Ville Syrjälä wrote:
> On Tue, Jan 28, 2020 at 03:52:41PM -0800, José Roberto de Souza
> wrote:
> > From: Radhakrishna Sripada
> >
> > dgfx platforms do not support CPU fence and FBC host tracking so
> > lets avoid write to removed registers.
> >
> > Cc:
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