Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Tvrtko Ursulin]

Hi,

On 30/11/2016 23:31, Anusha Srivatsa wrote:

The HuC loading process is similar to GuC. The intel_uc_fw_fetch()
is used for both cases.

HuC loading needs to be before GuC loading. The WOPCM setting must
be done early before loading any of them.

v2: rebased on-top of drm-intel-nightly.
removed if(HAS_GUC()) before the guc call. (D.Gordon)
update huc_version number of format.
v3: rebased to drm-intel-nightly, changed the file name format to
match the one in the huc package.
Changed dev->dev_private to to_i915()
v4: moved function back to where it was.
change wait_for_atomic to wait_for.
v5: rebased + comment changes.
v7: rebased.
v8: rebased.
v9: rebased. Changed the year in the copyright message to reflect
the right year.Correct the comments,remove the unwanted WARN message,
replace drm_gem_object_unreference() with i915_gem_object_put().Make the
prototypes in intel_huc.h non-extern.
v10: rebased. Update the file construction done by HuC. It is similar to
GuC.Adopted the approach used in-
https://patchwork.freedesktop.org/patch/104355/ 
v11: Fix warnings remove old declaration
v12: Change dev to dev_priv in macro definition.
Corrected comments.
v13: rebased.
v14: rebased on top of drm-tip


I thought we basically agreed to add i915.enable_huc (default=yes) and 
hide i915.enable_guc_loading, making it automatically turn on if either 
huc or guc submission are enabled?


Regards,

Tvrtko



Cc: Tvrtko Ursulin 
Tested-by: Xiang Haihao 
Signed-off-by: Anusha Srivatsa 
Signed-off-by: Alex Dai 
Signed-off-by: Peter Antoine 
Reviewed-by: Dave Gordon 
---
 drivers/gpu/drm/i915/Makefile   |   1 +
 drivers/gpu/drm/i915/i915_drv.c |   4 +-
 drivers/gpu/drm/i915/i915_drv.h |   4 +-
 drivers/gpu/drm/i915/i915_guc_reg.h |   3 +
 drivers/gpu/drm/i915/intel_guc_loader.c |   6 +-
 drivers/gpu/drm/i915/intel_huc.h|  42 +
 drivers/gpu/drm/i915/intel_huc_loader.c | 267 
 drivers/gpu/drm/i915/intel_uc.h |   2 +
 8 files changed, 324 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_huc.h
 create mode 100644 drivers/gpu/drm/i915/intel_huc_loader.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3c30916..01d4f4b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \
 # general-purpose microcontroller (GuC) support
 i915-y += intel_uc.o \
  intel_guc_loader.o \
+ intel_huc_loader.o \
  i915_guc_submission.o

 # autogenerated null render state
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 8dac298..075d9ce 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -603,6 +603,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;

+   intel_huc_init(dev);
intel_guc_init(dev);

ret = i915_gem_init(dev);
@@ -630,6 +631,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev_priv);
 cleanup_irq:
+   intel_huc_fini(dev);
intel_guc_fini(dev);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev);
@@ -1326,7 +1328,7 @@ void i915_driver_unload(struct drm_device *dev)

/* Flush any outstanding unpin_work. */
drain_workqueue(dev_priv->wq);
-
+   intel_huc_fini(dev);
intel_guc_fini(dev);
i915_gem_fini(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 297ad03..8edfae6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -56,6 +56,7 @@
 #include "intel_bios.h"
 #include "intel_dpll_mgr.h"
 #include "intel_uc.h"
+#include "intel_huc.h"
 #include "intel_lrc.h"
 #include "intel_ringbuffer.h"

@@ -1933,6 +1934,7 @@ struct drm_i915_private {

struct intel_gvt *gvt;

+   struct intel_huc huc;
struct intel_guc guc;

struct intel_csr csr;
@@ -2698,7 +2700,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define HAS_GUC(dev_priv)  ((dev_priv)->info.has_guc)
 #define HAS_GUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 #define HAS_GUC_SCHED(dev_priv)(HAS_GUC(dev_priv))
-
+#define HAS_HUC_UCODE(dev_priv)(HAS_GUC(dev_priv))
 #define HAS_RESOURCE_STREAMER(dev_priv) 
((dev_priv)->info.has_resource_streamer)

 #define HAS_POOLED_EU(dev_priv)((dev_priv)->info.has_pooled_eu)
diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
b/drivers/gpu/drm/i915/i915_guc_reg.h
index 5e638fc..f9829f6 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ 

[Intel-gfx] [PATCH v7 7/8] drm/i915: Decode system memory bandwidth

[Mahesh Kumar]

This patch adds support to decode system memory bandwidth
which will be used for arbitrated display memory percentage
calculation in GEN9 based system.

Changes from v1:
 - Address comments from Paulo
 - implement decode function for SKL/KBL also
Changes from v2:
 - Rewrite the code as per HW team inputs
 - Addresses review comments
Changes from v3:
 - Fix compilation warning

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.c | 173 
 drivers/gpu/drm/i915/i915_drv.h |  12 +++
 drivers/gpu/drm/i915/i915_reg.h |  37 +
 3 files changed, 222 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1c689b6..0ac7122 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -979,6 +979,173 @@ static void intel_sanitize_options(struct 
drm_i915_private *dev_priv)
DRM_DEBUG_DRIVER("use GPU sempahores? %s\n", yesno(i915.semaphores));
 }
 
+static inline enum rank skl_memdev_get_channel_rank(uint32_t val)
+{
+   uint8_t l_rank, s_rank;
+   uint8_t l_size, s_size;
+   enum rank ch_rank = DRAM_RANK_SINGLE;
+
+   l_size = (val >> SKL_DRAM_SIZE_L_SHIFT) & SKL_DRAM_SIZE_MASK;
+   s_size = (val >> SKL_DRAM_SIZE_S_SHIFT) & SKL_DRAM_SIZE_MASK;
+   l_rank = (val >> SKL_DRAM_RANK_L_SHIFT) & SKL_DRAM_RANK_MASK;
+   s_rank = (val >> SKL_DRAM_RANK_S_SHIFT) & SKL_DRAM_RANK_MASK;
+
+   /*
+* If any of the slot has dual rank memory consider
+* dual rank memory channel
+*/
+   if (l_rank == SKL_DRAM_RANK_DUAL || s_rank == SKL_DRAM_RANK_DUAL)
+   ch_rank = DRAM_RANK_DUAL;
+
+   /*
+* If both the slot has single rank memory then configuration
+* is dual rank memory
+*/
+   if ((l_size && l_rank == SKL_DRAM_RANK_SINGLE) &&
+   (s_size && s_rank == SKL_DRAM_RANK_SINGLE))
+   ch_rank = DRAM_RANK_DUAL;
+   return ch_rank;
+}
+
+static int
+skl_get_memdev_info(struct drm_i915_private *dev_priv)
+{
+   struct memdev_info *memdev_info = _priv->memdev_info;
+   uint32_t mem_freq_khz;
+   uint32_t val;
+   enum rank ch0_rank = DRAM_RANK_INVALID, ch1_rank = DRAM_RANK_INVALID;
+
+   val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
+   mem_freq_khz = (val & SKL_REQ_DATA_MASK) *
+   SKL_MEMORY_FREQ_MULTIPLIER_KHZ;
+
+   val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+   if (val != 0x0) {
+   memdev_info->num_channels++;
+   ch0_rank = skl_memdev_get_channel_rank(val);
+   }
+
+   val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
+   if (val != 0x0) {
+   memdev_info->num_channels++;
+   ch1_rank = skl_memdev_get_channel_rank(val);
+   }
+
+   if (memdev_info->num_channels == 0) {
+   DRM_ERROR("Number of mem channels are zero\n");
+   return -EINVAL;
+   }
+
+   memdev_info->bandwidth_kbps = (memdev_info->num_channels *
+   mem_freq_khz * 8);
+
+   if (memdev_info->bandwidth_kbps == 0) {
+   DRM_ERROR("Couldn't get system memory bandwidth\n");
+   return -EINVAL;
+   }
+   memdev_info->valid = true;
+
+   /*
+* If any of channel is single rank channel,
+* consider single rank memory
+*/
+   if (ch0_rank == DRAM_RANK_SINGLE || ch1_rank == DRAM_RANK_SINGLE)
+   memdev_info->rank = DRAM_RANK_SINGLE;
+   else
+   memdev_info->rank = max(ch0_rank, ch1_rank);
+
+   return 0;
+}
+
+static int
+bxt_get_memdev_info(struct drm_i915_private *dev_priv)
+{
+   struct memdev_info *memdev_info = _priv->memdev_info;
+   uint32_t dram_channels;
+   uint32_t mem_freq_khz, val;
+   uint8_t num_active_channels;
+   int i;
+
+   val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
+   mem_freq_khz = ((val & BXT_REQ_DATA_MASK) *
+   BXT_MEMORY_FREQ_MULTIPLIER_KHZ);
+
+   dram_channels = (val >> BXT_DRAM_CHANNEL_ACTIVE_SHIFT) &
+   BXT_DRAM_CHANNEL_ACTIVE_MASK;
+   num_active_channels = hweight32(dram_channels);
+
+   memdev_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
+
+   if (memdev_info->bandwidth_kbps == 0) {
+   DRM_ERROR("Couldn't get system memory bandwidth\n");
+   return -EINVAL;
+   }
+   memdev_info->valid = true;
+
+   /*
+* Now read each DUNIT8/9/10/11 to check the rank of each dimms.
+*/
+   for (i = 0; i < BXT_D_CR_DRP0_DUNIT_MAX; i++) {
+   val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
+   if (val != 0x) {
+   uint8_t rank;
+   enum rank ch_rank;
+
+   memdev_info->num_channels++;

[Intel-gfx] [PATCH v7 5/8] drm/i915/skl+: change WM calc to fixed point 16.16

[Mahesh Kumar]

This patch changes Watermak calculation to fixed point calculation.
Problem with current calculation is during plane_blocks_per_line
calculation we divide intermediate blocks with min_scanlines and
takes floor of the result because of integer operation.
hence we end-up assigning less blocks than required. Which leads to
flickers.

Changes since V1:
 - Add fixed point data type as per Paulo's review
Changes since V2:
 - use fixed_point instead of fp_16_16
Changes since V3:
 - rebase

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h | 84 +
 drivers/gpu/drm/i915/intel_pm.c | 69 +++--
 2 files changed, 124 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 64b0c90..b78dc9a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -119,6 +119,90 @@ bool __i915_inject_load_failure(const char *func, int 
line);
 #define i915_inject_load_failure() \
__i915_inject_load_failure(__func__, __LINE__)
 
+typedef struct {
+   uint32_t val;
+} uint_fixed_16_16_t;
+
+#define FP_16_16_MAX ({ \
+   uint_fixed_16_16_t fp; \
+   fp.val = UINT_MAX; \
+   fp; \
+})
+
+static inline uint_fixed_16_16_t u32_to_fixed_point(uint32_t val)
+{
+   uint_fixed_16_16_t fp;
+
+   WARN_ON(val >> 16);
+
+   fp.val = val << 16;
+   return fp;
+}
+
+static inline uint32_t fixed_point_to_u32_round_up(uint_fixed_16_16_t fp)
+{
+   return DIV_ROUND_UP(fp.val, 1 << 16);
+}
+
+static inline uint32_t fixed_point_to_u32(uint_fixed_16_16_t fp)
+{
+   return (fp.val / (1 << 16));
+}
+
+static inline uint_fixed_16_16_t min_fixed_point(uint_fixed_16_16_t min1,
+   uint_fixed_16_16_t min2)
+{
+   uint_fixed_16_16_t min;
+
+   min.val = min(min1.val, min2.val);
+   return min;
+}
+
+static inline uint_fixed_16_16_t max_fixed_point(uint_fixed_16_16_t max1,
+   uint_fixed_16_16_t max2)
+{
+   uint_fixed_16_16_t max;
+
+   max.val = max(max1.val, max2.val);
+   return max;
+}
+
+static inline uint_fixed_16_16_t fixed_point_div_round_up(uint32_t val,
+   uint32_t d)
+{
+   uint_fixed_16_16_t fp, res;
+
+   fp = u32_to_fixed_point(val);
+   res.val = DIV_ROUND_UP(fp.val, d);
+   return res;
+}
+
+static inline uint_fixed_16_16_t fixed_point_div_round_up_u64(uint32_t val,
+   uint32_t d)
+{
+   uint_fixed_16_16_t res;
+   uint64_t interm_val;
+
+   interm_val = (uint64_t)val << 16;
+   interm_val = DIV_ROUND_UP_ULL(interm_val, d);
+   WARN_ON(interm_val >> 32);
+   res.val = (uint32_t) interm_val;
+
+   return res;
+}
+
+static inline uint_fixed_16_16_t mul_fixed_point_u32(uint32_t val,
+   uint_fixed_16_16_t mul)
+{
+   uint64_t intermediate_val;
+   uint_fixed_16_16_t fp;
+
+   intermediate_val = (uint64_t) val * mul.val;
+   WARN_ON(intermediate_val >> 32);
+   fp.val = (uint32_t) intermediate_val;
+   return fp;
+}
+
 static inline const char *yesno(bool v)
 {
return v ? "yes" : "no";
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8f0e6f5..cc8fc84 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3503,32 +3503,35 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
 */
-static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t 
latency)
+static uint_fixed_16_16_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp,
+uint32_t latency)
 {
-   uint32_t wm_intermediate_val, ret;
+   uint32_t wm_intermediate_val;
+   uint_fixed_16_16_t ret;
 
if (latency == 0)
-   return UINT_MAX;
-
-   wm_intermediate_val = latency * pixel_rate * cpp / 512;
-   ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
+   return FP_16_16_MAX;
 
+   wm_intermediate_val = latency * pixel_rate * cpp;
+   ret = fixed_point_div_round_up_u64(wm_intermediate_val, 1000 * 512);
return ret;
 }
 
-static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
-  uint32_t latency, uint32_t plane_blocks_per_line)
+static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
+   uint32_t pipe_htotal,
+   uint32_t latency,
+   uint_fixed_16_16_t plane_blocks_per_line)
 {
-   uint32_t ret;
uint32_t wm_intermediate_val;
+   uint_fixed_16_16_t ret;
 
if (latency == 0)
-

[Intel-gfx] [PATCH v7 4/8] drm/i915/bxt: Enable IPC support

[Mahesh Kumar]

This patch adds IPC support for platforms. This patch enables IPC
only for BXT/KBL platform as for SKL recommendation is to keep is disabled.
IPC (Isochronous Priority Control) is the hardware feature, which
dynamically controles the memory read priority of Display.

When IPC is enabled, plane read requests are sent at high priority until
filling above the transition watermark, then the requests are sent at
lower priority until dropping below the level 0 watermark.
The lower priority requests allow other memory clients to have better
memory access. When IPC is disabled, all plane read requests are sent at
high priority.

Changes since V1:
 - Remove commandline parameter to disable ipc
 - Address Paulo's comments
Changes since V2:
 - Address review comments
 - Set ipc_enabled flag
Changes since V3:
 - move ipc_enabled flag assignment inside intel_ipc_enable function

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.c  |  2 +-
 drivers/gpu/drm/i915/i915_reg.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 16 
 4 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f27e4bd..1c689b6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1251,7 +1251,7 @@ int i915_driver_load(struct pci_dev *pdev, const struct 
pci_device_id *ent)
 
intel_runtime_pm_enable(dev_priv);
 
-   dev_priv->ipc_enabled = false;
+   intel_enable_ipc(dev_priv);
 
/* Everything is in place, we can now relax! */
DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6747d68..649319d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6418,6 +6418,7 @@ enum {
 #define  DISP_FBC_WM_DIS   (1<<15)
 #define DISP_ARB_CTL2  _MMIO(0x45004)
 #define  DISP_DATA_PARTITION_5_6   (1<<6)
+#define  DISP_IPC_ENABLE   (1<<3)
 #define DBUF_CTL   _MMIO(0x45008)
 #define  DBUF_POWER_REQUEST(1<<31)
 #define  DBUF_POWER_STATE  (1<<30)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 9bbe5c5..3069512 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1755,6 +1755,7 @@ bool skl_ddb_allocation_overlaps(const struct 
skl_ddb_entry **entries,
 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
 bool ilk_disable_lp_wm(struct drm_device *dev);
 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
+void intel_enable_ipc(struct drm_i915_private *dev_priv);
 static inline int intel_enable_rc6(void)
 {
return i915.enable_rc6;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3650c74..8f0e6f5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4655,6 +4655,22 @@ void intel_update_watermarks(struct intel_crtc *crtc)
dev_priv->display.update_wm(crtc);
 }
 
+void intel_enable_ipc(struct drm_i915_private *dev_priv)
+{
+   u32 val;
+
+   dev_priv->ipc_enabled = false;
+   if (!(IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)))
+   return;
+
+   val = I915_READ(DISP_ARB_CTL2);
+
+   val |= DISP_IPC_ENABLE;
+
+   I915_WRITE(DISP_ARB_CTL2, val);
+   dev_priv->ipc_enabled = true;
+}
+
 /*
  * Lock protecting IPS related data structures
  */
-- 
2.10.1

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[Intel-gfx] [PATCH v7 0/8] GEN-9 Arbitrated Bandwidth WM WA's & IPC

[Mahesh Kumar]

This series implements following set of functionality
Implement IPC WA's for Broxton/KBL
Enable IPC in supported platforms
Convert WM calculation to fixed point calculation
Calculation of System memory Bandwidth for SKL/KBL/BXT
Implementation of Arbitrated memory Bandwidth related WM WA's


Mahesh Kumar (8):
  drm/i915/skl: Add variables to check x_tile and y_tile
  drm/i915/bxt: IPC WA for Broxton
  drm/i915/kbl: IPC workaround for kabylake
  drm/i915/bxt: Enable IPC support
  drm/i915/skl+: change WM calc to fixed point 16.16
  drm/i915: Add intel_atomic_get_existing_crtc_state function
  drm/i915: Decode system memory bandwidth
  drm/i915/gen9: WM memory bandwidth related workaround

 drivers/gpu/drm/i915/i915_drv.c  | 175 ++
 drivers/gpu/drm/i915/i915_drv.h  | 109 ++
 drivers/gpu/drm/i915/i915_reg.h  |  38 +
 drivers/gpu/drm/i915/intel_display.c |  24 
 drivers/gpu/drm/i915/intel_drv.h |  15 ++
 drivers/gpu/drm/i915/intel_pm.c  | 272 +--
 6 files changed, 586 insertions(+), 47 deletions(-)

-- 
2.10.1

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[Intel-gfx] [PATCH v7 1/8] drm/i915/skl: Add variables to check x_tile and y_tile

[Mahesh Kumar]

This patch adds variable to check for X_tiled & y_tiled planes, instead
of always checking against framebuffer-modifiers.

Changes:
 - Created separate patch as per Paulo's comment
 - Added x_tiled variable as well
Changes since V2:
 - Incorporate Paulo's comments
 - Rebase

Signed-off-by: Mahesh Kumar 
Reviewed-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_pm.c | 22 --
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 29b6653..a467ffe 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3579,13 +3579,18 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
struct intel_atomic_state *state =
to_intel_atomic_state(cstate->base.state);
bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
+   bool y_tiled, x_tiled;
 
if (latency == 0 || !cstate->base.active || 
!intel_pstate->base.visible) {
*enabled = false;
return 0;
}
 
-   if (apply_memory_bw_wa && fb->modifier == I915_FORMAT_MOD_X_TILED)
+   y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
+   fb->modifier == I915_FORMAT_MOD_Yf_TILED;
+   x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
+
+   if (apply_memory_bw_wa && x_tiled)
latency += 15;
 
width = drm_rect_width(_pstate->base.src) >> 16;
@@ -3624,16 +3629,15 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
y_min_scanlines *= 2;
 
plane_bytes_per_line = width * cpp;
-   if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
-   fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
+   if (y_tiled) {
plane_blocks_per_line =
  DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
plane_blocks_per_line /= y_min_scanlines;
-   } else if (fb->modifier == DRM_FORMAT_MOD_NONE) {
+   } else if (x_tiled) {
+   plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
+   } else {
plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
+ 1;
-   } else {
-   plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
}
 
method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
@@ -3644,8 +3648,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
 
y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
 
-   if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
-   fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
+   if (y_tiled) {
selected_result = max(method2, y_tile_minimum);
} else {
if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
@@ -3661,8 +3664,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
 
if (level >= 1 && level <= 7) {
-   if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
-   fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
+   if (y_tiled) {
res_blocks += y_tile_minimum;
res_lines += y_min_scanlines;
} else {
-- 
2.10.1

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[Intel-gfx] [PATCH i-g-t 3/3] tests/gem_reset_stats: Add test to check client bans

[Mika Kuoppala]

Client will get banned from creating new context
if it has managed to get > 3 context banned.

Signed-off-by: Mika Kuoppala 
---
 tests/gem_reset_stats.c | 47 ++-
 1 file changed, 42 insertions(+), 5 deletions(-)

diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
index 669a30a..1b9b5cd 100644
--- a/tests/gem_reset_stats.c
+++ b/tests/gem_reset_stats.c
@@ -327,15 +327,15 @@ static void test_rs_ctx(const struct 
intel_execution_engine *e,
}
 }
 
-static void test_ban_ctx(const struct intel_execution_engine *e,
-const bool ban_default)
+static void __test_ban_ctx(int fd_bad,
+  const struct intel_execution_engine *e,
+  const bool ban_default)
 {
struct local_drm_i915_reset_stats rs_bad, rs_good;
-   int fd_bad, fd_good, i;
+   int fd_good, i;
uint32_t ctx_good, ctx_bad;
int active_count = 0, pending_count = 0;
 
-   fd_bad = drm_open_driver(DRIVER_INTEL);
fd_good = drm_open_driver(DRIVER_INTEL);
 
ctx_good = gem_context_create(fd_bad);
@@ -401,10 +401,44 @@ static void test_ban_ctx(const struct 
intel_execution_engine *e,
igt_assert_eq(rs_good.batch_active, 0);
igt_assert_eq(rs_good.batch_pending, 0);
 
-   close(fd_bad);
close(fd_good);
 }
 
+static void test_ban_ctx(const struct intel_execution_engine *e, bool 
ban_default)
+{
+   int fd;
+   fd = drm_open_driver(DRIVER_INTEL);
+
+   __test_ban_ctx(fd, e, ban_default);
+
+   close(fd);
+}
+
+static void test_ban_client(const struct intel_execution_engine *e)
+{
+   struct drm_i915_gem_context_create create;
+   int fd;
+   fd = drm_open_driver(DRIVER_INTEL);
+
+   __test_ban_ctx(fd, e, false);
+   igt_assert_lt(0, noop(fd, 0, e));
+
+   __test_ban_ctx(fd, e, false);
+   igt_assert_lt(0, noop(fd, 0, e));
+
+   __test_ban_ctx(fd, e, false);
+   igt_assert_lt(0, noop(fd, 0, e));
+
+   __test_ban_ctx(fd, e, false);
+
+   memset(, 0, sizeof(create));
+   igt_assert_eq(-1, igt_ioctl(fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, 
));
+   igt_assert_eq(-EIO, -errno);
+   igt_assert_lt(0, noop(fd, 0, e));
+
+   close(fd);
+}
+
 static void test_unrelated_ctx(const struct intel_execution_engine *e)
 {
int fd1,fd2;
@@ -844,6 +878,9 @@ igt_main
igt_subtest_f("ban-ctx-%s", e->name)
RUN_CTX_TEST(test_ban_ctx(e, false));
 
+   igt_subtest_f("ban-client-%s", e->name)
+   RUN_CTX_TEST(test_ban_client(e));
+
igt_subtest_f("reset-count-%s", e->name)
RUN_TEST(test_reset_count(e, false));
 
-- 
2.7.4

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[Intel-gfx] [PATCH i-g-t 1/3] tests/gem_reset_stats: Change pending/active assertions

[Mika Kuoppala]

Now that we replay the non guilty contexts and always replay
the default ctx, even when guilty, the assumptions of how many
active and pending batches there was in the time of reset has
changed.

Driver doesn't increment pending counts for contexts that it
considered unaffected by reset. Because it can now replay the
queued requests.

For contexts, guilty of reset, we replay the request envelopes,
but nop the batchbuffer starts. This changes of how many 'hangs'
we think there were queued. As future queued hangs are now NOPed
out, we need to change the assumption of active counts also.

Adapt to these changes of how the replaying of batches affect
the assertions in pending/active counting and banning tests.
While doing this, throw out the retrying to be more strict about
the determinism we want to achieve.

Cc: Chris Wilson 
Signed-off-by: Mika Kuoppala 
---
 tests/gem_reset_stats.c | 154 ++--
 1 file changed, 56 insertions(+), 98 deletions(-)

diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
index 3de74af..2718a33 100644
--- a/tests/gem_reset_stats.c
+++ b/tests/gem_reset_stats.c
@@ -152,7 +152,7 @@ static struct timespec ts_injected;
 
 #define BAN HANG_ALLOW_BAN
 #define ASYNC 2
-static void inject_hang(int fd, uint32_t ctx,
+static bool inject_hang(int fd, uint32_t ctx,
const struct intel_execution_engine *e,
unsigned flags)
 {
@@ -163,6 +163,8 @@ static void inject_hang(int fd, uint32_t ctx,
hang = igt_hang_ctx(fd, ctx, e->exec_id | e->flags, flags & BAN, NULL);
if ((flags & ASYNC) == 0)
igt_post_hang_ring(fd, hang);
+
+   return hang.handle >= 0;
 }
 
 static const char *status_to_string(int x)
@@ -239,7 +241,7 @@ static void test_rs(const struct intel_execution_engine *e,
if (i == hang_index)
assert_reset_status(i, fd[i], 0, RS_BATCH_ACTIVE);
if (i > hang_index)
-   assert_reset_status(i, fd[i], 0, RS_BATCH_PENDING);
+   assert_reset_status(i, fd[i], 0, RS_NO_ERROR);
}
 
igt_assert(igt_seconds_elapsed(_injected) <= 30);
@@ -312,10 +314,10 @@ static void test_rs_ctx(const struct 
intel_execution_engine *e,
RS_BATCH_ACTIVE);
if (i == hang_index && j > hang_context)
assert_reset_status(i, fd[i], ctx[i][j],
-   RS_BATCH_PENDING);
+   RS_NO_ERROR);
if (i > hang_index)
assert_reset_status(i, fd[i], ctx[i][j],
-   RS_BATCH_PENDING);
+   RS_NO_ERROR);
}
}
 
@@ -325,128 +327,84 @@ static void test_rs_ctx(const struct 
intel_execution_engine *e,
}
 }
 
-static void test_ban(const struct intel_execution_engine *e)
+static void test_ban_ctx(const struct intel_execution_engine *e,
+const bool ban_default)
 {
struct local_drm_i915_reset_stats rs_bad, rs_good;
-   int fd_bad, fd_good;
-   int ban, retry = 10;
+   int fd_bad, fd_good, i;
+   uint32_t ctx_good, ctx_bad;
int active_count = 0, pending_count = 0;
 
fd_bad = drm_open_driver(DRIVER_INTEL);
fd_good = drm_open_driver(DRIVER_INTEL);
 
-   assert_reset_status(fd_bad, fd_bad, 0, RS_NO_ERROR);
+   ctx_good = gem_context_create(fd_bad);
+   if (!ban_default)
+   ctx_bad = gem_context_create(fd_bad);
+   else
+   ctx_bad = 0;
+
+   assert_reset_status(fd_bad, fd_bad, ctx_bad, RS_NO_ERROR);
+   assert_reset_status(fd_bad, fd_bad, ctx_good, RS_NO_ERROR);
assert_reset_status(fd_good, fd_good, 0, RS_NO_ERROR);
 
-   noop(fd_bad, 0, e);
-   noop(fd_good, 0, e);
+   igt_assert_lt(0, noop(fd_bad, ctx_bad, e));
+   igt_assert_lt(0, noop(fd_bad, ctx_good, e));
+   igt_assert_lt(0, noop(fd_good, 0, e));
 
-   assert_reset_status(fd_bad, fd_bad, 0, RS_NO_ERROR);
+   assert_reset_status(fd_bad, fd_bad, ctx_bad, RS_NO_ERROR);
+   assert_reset_status(fd_bad, fd_bad, ctx_good, RS_NO_ERROR);
assert_reset_status(fd_good, fd_good, 0, RS_NO_ERROR);
 
-   inject_hang(fd_bad, 0, e, BAN | ASYNC);
-   active_count++;
+   inject_hang(fd_bad, ctx_bad, e, BAN | ASYNC);
+   /* The next synced ban below ban will get nopped if default ctx */
+   if (!ctx_bad)
+   active_count++;
 
-   noop(fd_good, 0, e);
-   noop(fd_good, 0, e);
+   igt_assert_lt(0, noop(fd_good, 0, e));
+   /* We don't skip requests for default ctx, so no
+* pending change as they will be replayed */
+   

[Intel-gfx] [PATCH i-g-t 2/3] tests/gem_reset_stats: test no progress detection

[Mika Kuoppala]

If seqno is not incrementing but head is moving,
we declare hang but much slower. Add test to check
that this mechanism is working properly.

Signed-off-by: Mika Kuoppala 
---
 tests/gem_reset_stats.c | 75 +
 1 file changed, 75 insertions(+)

diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
index 2718a33..669a30a 100644
--- a/tests/gem_reset_stats.c
+++ b/tests/gem_reset_stats.c
@@ -711,6 +711,75 @@ static void defer_hangcheck(const struct 
intel_execution_engine *engine)
close(fd);
 }
 
+static void test_no_seqno_progress(const struct intel_execution_engine *engine,
+  const bool use_ctx)
+{
+   struct drm_i915_gem_relocation_entry reloc;
+   struct drm_i915_gem_execbuffer2 eb;
+   struct drm_i915_gem_exec_object2 exec;
+   struct local_drm_i915_reset_stats before, after;
+   int len = 0, ctx, fd;
+   uint32_t batch[16*1024];
+   struct timespec ts_start;
+
+   fd = drm_open_driver(DRIVER_INTEL);
+
+   memset(, 0, sizeof(reloc));
+memset(, 0, sizeof(exec));
+memset(, 0, sizeof(eb));
+   memset(, 0, sizeof(batch));
+
+   exec.handle = gem_create(fd, sizeof(batch));
+   exec.relocation_count = 1;
+exec.relocs_ptr = (uintptr_t)
+
+   igt_assert((int)exec.handle > 0);
+
+   if (use_ctx)
+   ctx = gem_context_create(fd);
+   else
+   ctx = 0;
+
+   len = 2;
+   if (intel_gen(intel_get_drm_devid(fd)) >= 8)
+   len++;
+
+   batch[sizeof(batch)/sizeof(uint32_t) - len] = MI_BATCH_BUFFER_START | 
(len - 2);
+gem_write(fd, exec.handle, 0, batch, sizeof(batch));
+
+reloc.offset = sizeof(batch) - ((len-1) * 4);
+reloc.delta = 0;
+reloc.target_handle = exec.handle;
+reloc.read_domains = I915_GEM_DOMAIN_COMMAND;
+
+   eb.buffers_ptr = (uintptr_t)
+   eb.buffer_count = 1;
+   eb.flags = engine->exec_id;
+if (ctx)
+   i915_execbuffer2_set_context_id(eb, ctx);
+
+   igt_assert_eq(gem_reset_stats(fd, ctx, ), 0);
+
+   clock_gettime(CLOCK_MONOTONIC, _start);
+
+   igt_assert_eq(0, __gem_execbuf(fd, ));
+   igt_assert_lte(0, noop(fd, ctx, engine));
+   gem_sync(fd, exec.handle);
+
+   igt_assert_lte(0, noop(fd, ctx, engine));
+   igt_assert_eq(gem_reset_stats(fd, ctx, ), 0);
+
+   sync_gpu();
+
+   igt_assert(after.batch_active == before.batch_active + 1);
+
+   gem_close(fd, exec.handle);
+   close(fd);
+
+   igt_assert(igt_seconds_elapsed(_start) > 5);
+   igt_assert(igt_seconds_elapsed(_start) < 15);
+}
+
 static bool gem_has_reset_stats(int fd)
 {
struct local_drm_i915_reset_stats rs;
@@ -798,5 +867,11 @@ igt_main
 
igt_subtest_f("defer-hangcheck-%s", e->name)
RUN_TEST(defer_hangcheck(e));
+
+   igt_subtest_f("no-progress-%s", e->name)
+   RUN_TEST(test_no_seqno_progress(e, false));
+
+   igt_subtest_f("no-progress-ctx-%s", e->name)
+   RUN_CTX_TEST(test_no_seqno_progress(e, true));
}
 }
-- 
2.7.4

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Re: [Intel-gfx] [PATCH i-g-t 3/3] tests/gem_reset_stats: Add test to check client bans

[Chris Wilson]

On Thu, Dec 01, 2016 at 03:31:45PM +0200, Mika Kuoppala wrote:
> Client will get banned from creating new context
> if it has managed to get > 3 context banned.

I'm not thrilled about baking that magic number into an ABI requirement.

Just make it N bans, test timing out after say 120s of happiness (with
skip)?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] [PATCH 11/15] drm/i915: Protect DSPARB registers with a spinlock

[Maarten Lankhorst]

Op 01-12-16 om 14:13 schreef Ville Syrjälä:
> On Thu, Dec 01, 2016 at 12:56:16PM +0100, Maarten Lankhorst wrote:
>> Op 28-11-16 om 18:37 schreef ville.syrj...@linux.intel.com:
>>> From: Ville Syrjälä 
>>>
>>> Each DSPARB register can house bits for two separate pipes, hence
>>> we must protect the registers during reprogramming so that parallel
>>> FIFO reconfigurations happening simultaneosly on multiple pipes won't
>>> corrupt each others values.
>>>
>>> Signed-off-by: Ville Syrjälä 
>>> ---
>>>  drivers/gpu/drm/i915/i915_drv.c | 1 +
>>>  drivers/gpu/drm/i915/i915_drv.h | 3 +++
>>>  drivers/gpu/drm/i915/intel_pm.c | 6 ++
>>>  3 files changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>>> b/drivers/gpu/drm/i915/i915_drv.c
>>> index 0fba4bb5655e..c98032e9112b 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.c
>>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>>> @@ -811,6 +811,7 @@ static int i915_driver_init_early(struct 
>>> drm_i915_private *dev_priv,
>>> spin_lock_init(_priv->uncore.lock);
>>> spin_lock_init(_priv->mm.object_stat_lock);
>>> spin_lock_init(_priv->mmio_flip_lock);
>>> +   spin_lock_init(_priv->wm.dsparb_lock);
>> Can we make sure all wm updates are done with dev_priv->wm.wm_mutex held 
>> instead?
> We can't grab a mutex from the vblank evade critical section. We'd have
> to hold the mutex across the whole thing then. Not sure if that would be
> a good or a bad thing.
Ah right, I missed that part since it didn't happen in the patches yet, might 
be worth pointing out in the commit message.

Will vlv_wm_values also be updated with that lock in the future? Looks like it 
could be a fun race otherwise.
>> gen9 wm's and ilk wm's use that mutex, for similar reasons.
>>> mutex_init(_priv->sb_lock);
>>> mutex_init(_priv->modeset_restore_lock);
>>> mutex_init(_priv->av_mutex);
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>>> b/drivers/gpu/drm/i915/i915_drv.h
>>> index 9d808b706824..75439e9a67f7 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2169,6 +2169,9 @@ struct drm_i915_private {
>>> } sagv_status;
>>>  
>>> struct {
>>> +   /* protects DSPARB registers on pre-g4x/vlv/chv */
>>> +   spinlock_t dsparb_lock;
>>> +
>>> /*
>>>  * Raw watermark latency values:
>>>  * in 0.1us units for WM0,
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
>>> b/drivers/gpu/drm/i915/intel_pm.c
>>> index 24d85a4e4ed3..9f25f2195a6a 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -1215,6 +1215,8 @@ static void vlv_pipe_set_fifo_size(struct intel_crtc 
>>> *crtc)
>>>   pipe_name(crtc->pipe), sprite0_start,
>>>   sprite1_start, fifo_size);
>>>  
>>> +   spin_lock(_priv->wm.dsparb_lock);
>>> +
>>> switch (crtc->pipe) {
>>> uint32_t dsparb, dsparb2, dsparb3;
>>> case PIPE_A:
>>> @@ -1271,6 +1273,10 @@ static void vlv_pipe_set_fifo_size(struct intel_crtc 
>>> *crtc)
>>> default:
>>> break;
>>> }
>>> +
>>> +   POSTING_READ(DSPARB);
>>> +
>>> +   spin_unlock(_priv->wm.dsparb_lock);
>>>  }
>>>  
>>>  #undef VLV_FIFO


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[Intel-gfx] ✗ Fi.CI.BAT: warning for GEM object create and driver init dev_priv cleanups (rev2)

[Patchwork]

== Series Details ==

Series: GEM object create and driver init dev_priv cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/16162/
State : warning

== Summary ==

Series 16162v2 GEM object create and driver init dev_priv cleanups
https://patchwork.freedesktop.org/api/1.0/series/16162/revisions/2/mbox/

Test kms_pipe_crc_basic:
Subgroup bad-nb-words-1:
pass   -> DMESG-WARN (fi-ivb-3770)

fi-bdw-5557u total:245  pass:226  dwarn:0   dfail:0   fail:4   skip:15 
fi-bsw-n3050 total:245  pass:203  dwarn:0   dfail:0   fail:2   skip:40 
fi-bxt-t5700 total:245  pass:213  dwarn:0   dfail:0   fail:4   skip:28 
fi-byt-j1900 total:245  pass:214  dwarn:0   dfail:0   fail:3   skip:28 
fi-byt-n2820 total:245  pass:210  dwarn:0   dfail:0   fail:3   skip:32 
fi-hsw-4770  total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20 
fi-hsw-4770r total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20 
fi-ilk-650   total:245  pass:189  dwarn:0   dfail:0   fail:3   skip:53 
fi-ivb-3520m total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-ivb-3770  total:245  pass:218  dwarn:1   dfail:0   fail:4   skip:22 
fi-kbl-7500u total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-skl-6260u total:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14 
fi-skl-6700hqtotal:245  pass:220  dwarn:0   dfail:0   fail:4   skip:21 
fi-skl-6700k total:245  pass:219  dwarn:1   dfail:0   fail:4   skip:21 
fi-skl-6770hqtotal:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14 
fi-snb-2600  total:245  pass:209  dwarn:0   dfail:0   fail:3   skip:33 

15f4397c9b50b0212dcb99fb2b5b8a3867133e81 drm-tip: 2016y-12m-01d-13h-26m-26s UTC 
integration manifest
a6838f4 drm/i915: Make intel_pm_setup take dev_priv
f2ef943 drm/i915: Make i915_save/restore_state and intel_i2c_reset take dev_priv
065196e drm/i915: Make i915_destroy_error_state take dev_priv
5e5a2ec drm/i915: Make gmbus setup take dev_priv
81ddb80 drm/i915: Unexport VGA switcheroo functions
b8756a6 drm/i915: dev_priv cleanup in bridge/bar/mmio init code
e74be3e drm/i915: More GEM init dev_priv cleanup
3f48e34 drm/i915: Make various init functions take dev_priv
c6faec2 drm/i915: Make GEM object create and create from data take dev_priv
b75f2e6 drm/i915: Make GEM object alloc/free and stolen created take dev_priv

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3162/
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Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/lspcon: Enable AUX interrupts for resume time initialization (rev2)

[Imre Deak]

On ti, 2016-11-29 at 21:53 +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/lspcon: Enable AUX interrupts for resume time initialization 
> (rev2)
> URL   : https://patchwork.freedesktop.org/series/16106/
> State : success
> 
> == Summary ==
> 
> Series 16106v2 drm/i915/lspcon: Enable AUX interrupts for resume time 
> initialization
> https://patchwork.freedesktop.org/api/1.0/series/16106/revisions/2/mbox/

I pushed the patch to -dinq, thanks for the testing and review.

--Imre

> 
> 
> fi-bdw-5557u total:245  pass:230  dwarn:0   dfail:0   fail:0   skip:15 
> fi-bsw-n3050 total:245  pass:205  dwarn:0   dfail:0   fail:0   skip:40 
> fi-byt-j1900 total:245  pass:217  dwarn:0   dfail:0   fail:0   skip:28 
> fi-byt-n2820 total:245  pass:213  dwarn:0   dfail:0   fail:0   skip:32 
> fi-hsw-4770  total:245  pass:225  dwarn:0   dfail:0   fail:0   skip:20 
> fi-hsw-4770r total:245  pass:225  dwarn:0   dfail:0   fail:0   skip:20 
> fi-ilk-650   total:245  pass:192  dwarn:0   dfail:0   fail:0   skip:53 
> fi-ivb-3520m total:245  pass:223  dwarn:0   dfail:0   fail:0   skip:22 
> fi-ivb-3770  total:245  pass:223  dwarn:0   dfail:0   fail:0   skip:22 
> fi-kbl-7500u total:245  pass:223  dwarn:0   dfail:0   fail:0   skip:22 
> fi-skl-6260u total:245  pass:231  dwarn:0   dfail:0   fail:0   skip:14 
> fi-skl-6700hqtotal:245  pass:224  dwarn:0   dfail:0   fail:0   skip:21 
> fi-skl-6700k total:245  pass:223  dwarn:1   dfail:0   fail:0   skip:21 
> fi-skl-6770hqtotal:245  pass:231  dwarn:0   dfail:0   fail:0   skip:14 
> fi-snb-2520m total:245  pass:213  dwarn:0   dfail:0   fail:0   skip:32 
> fi-snb-2600  total:245  pass:212  dwarn:0   dfail:0   fail:0   skip:33 
> 
> 41799fbb771e82427273492bfad8f2e2ae3027ef drm-tip: 2016y-11m-29d-20h-54m-07s 
> UTC integration manifest
> d61aedb drm/i915/lspcon: Enable AUX interrupts for resume time initialization
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3147/
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[Intel-gfx] [PATCH v7 2/8] drm/i915/bxt: IPC WA for Broxton

[Mahesh Kumar]

Display Workarounds #1135
If IPC is enabled in BXT, display underruns are observed.
WA: The Line Time programmed in the WM_LINETIME register should be
half of the actual calculated Line Time.

Programmed Line Time = 1/2*Calculated Line Time

Changes since V1:
 - Add Workaround number in commit & code

Signed-off-by: Mahesh Kumar 
Reviewed-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/i915_drv.c |  2 ++
 drivers/gpu/drm/i915/i915_drv.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c | 12 ++--
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b893e67..f27e4bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1251,6 +1251,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct 
pci_device_id *ent)
 
intel_runtime_pm_enable(dev_priv);
 
+   dev_priv->ipc_enabled = false;
+
/* Everything is in place, we can now relax! */
DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
 driver.name, driver.major, driver.minor, driver.patchlevel,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1ec9619..64b0c90 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2306,6 +2306,8 @@ struct drm_i915_private {
/* perform PHY state sanity checks? */
bool chv_phy_assert[2];
 
+   bool ipc_enabled;
+
/* Used to save the pipe-to-encoder mapping for audio */
struct intel_encoder *av_enc_map[I915_MAX_PIPES];
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a467ffe..89d8a28 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3755,7 +3755,10 @@ skl_compute_wm_level(const struct drm_i915_private 
*dev_priv,
 static uint32_t
 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
 {
+   struct drm_atomic_state *state = cstate->base.state;
+   struct drm_i915_private *dev_priv = to_i915(state->dev);
uint32_t pixel_rate;
+   uint32_t linetime_wm;
 
if (!cstate->base.active)
return 0;
@@ -3765,8 +3768,13 @@ skl_compute_linetime_wm(struct intel_crtc_state *cstate)
if (WARN_ON(pixel_rate == 0))
return 0;
 
-   return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
-   pixel_rate);
+   linetime_wm = DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal *
+   1000, pixel_rate);
+   /* Display WA #1135 for BXT:All */
+   if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled)
+   linetime_wm = DIV_ROUND_UP(linetime_wm, 2);
+
+   return linetime_wm;
 }
 
 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
-- 
2.10.1

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[Intel-gfx] [PATCH v7 6/8] drm/i915: Add intel_atomic_get_existing_crtc_state function

[Mahesh Kumar]

This patch Adds a function to extract intel_crtc_state from the
atomic_state, if not available it returns NULL.

Signed-off-by: Mahesh Kumar 
Reviewed-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_drv.h | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3069512..dbee392 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1804,6 +1804,20 @@ intel_atomic_get_crtc_state(struct drm_atomic_state 
*state,
return to_intel_crtc_state(crtc_state);
 }
 
+static inline struct intel_crtc_state *
+intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+   struct drm_crtc_state *crtc_state;
+
+   crtc_state = drm_atomic_get_existing_crtc_state(state, >base);
+
+   if (crtc_state)
+   return to_intel_crtc_state(crtc_state);
+   else
+   return NULL;
+}
+
 static inline struct intel_plane_state *
 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
  struct intel_plane *plane)
-- 
2.10.1

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[Intel-gfx] [PATCH v7 8/8] drm/i915/gen9: WM memory bandwidth related workaround

[Mahesh Kumar]

This patch implemnets Workariunds related to display arbitrated memory
bandwidth. These WA are applicabe for all gen-9 based platforms.

Changes since v1:
 - Rebase on top of Paulo's patch series
Changes since v2:
 - Address review comments
 - Rebase/rework as per other patch changes in series
Changes since v3:
 - Rework based on Maarten's comments

Signed-off-by: Mahesh Kumar 
---
 drivers/gpu/drm/i915/i915_drv.h  |  11 +++
 drivers/gpu/drm/i915/intel_display.c |  24 ++
 drivers/gpu/drm/i915/intel_pm.c  | 155 +--
 3 files changed, 181 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 69213a4..3126259 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1216,6 +1216,13 @@ enum intel_sbi_destination {
SBI_MPHY,
 };
 
+/* SKL+ Watermark arbitrated display bandwidth Workarounds */
+enum watermark_memory_wa {
+   WATERMARK_WA_NONE,
+   WATERMARK_WA_X_TILED,
+   WATERMARK_WA_Y_TILED,
+};
+
 #define QUIRK_PIPEA_FORCE (1<<0)
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
@@ -1788,6 +1795,10 @@ struct skl_ddb_allocation {
 
 struct skl_wm_values {
unsigned dirty_pipes;
+   /* any WaterMark memory workaround Required */
+   enum watermark_memory_wa mem_wa;
+   uint32_t pipe_bw_kbps[I915_MAX_PIPES];
+   bool pipe_ytiled[I915_MAX_PIPES];
struct skl_ddb_allocation ddb;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 5d11002..f8da488 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14574,6 +14574,28 @@ static void intel_atomic_track_fbs(struct 
drm_atomic_state *state)
  to_intel_plane(plane)->frontbuffer_bit);
 }
 
+static void
+intel_update_wm_bw_wa(struct drm_atomic_state *state)
+{
+   struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+   struct drm_i915_private *dev_priv = to_i915(state->dev);
+   const struct drm_crtc *crtc;
+   const struct drm_crtc_state *cstate;
+   struct skl_wm_values *results = _state->wm_results;
+   struct skl_wm_values *hw_vals = _priv->wm.skl_hw;
+   int i;
+
+   if (!IS_GEN9(dev_priv))
+   return;
+
+   for_each_crtc_in_state(state, crtc, cstate, i) {
+   hw_vals->pipe_bw_kbps[i] = results->pipe_bw_kbps[i];
+   hw_vals->pipe_ytiled[i] = results->pipe_ytiled[i];
+   }
+
+   hw_vals->mem_wa = results->mem_wa;
+}
+
 /**
  * intel_atomic_commit - commit validated state object
  * @dev: DRM device
@@ -14614,6 +14636,8 @@ static int intel_atomic_commit(struct drm_device *dev,
intel_shared_dpll_commit(state);
intel_atomic_track_fbs(state);
 
+   intel_update_wm_bw_wa(state);
+
if (intel_state->modeset) {
memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
   sizeof(intel_state->min_pixclk));
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cc8fc84..fda6e1e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2878,11 +2878,7 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
 
 #define SKL_SAGV_BLOCK_TIME30 /* µs */
 
-/*
- * FIXME: We still don't have the proper code detect if we need to apply the 
WA,
- * so assume we'll always need it in order to avoid underruns.
- */
-static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
+static bool intel_needs_memory_bw_wa(struct intel_atomic_state *state)
 {
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 
@@ -3056,7 +3052,7 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
 
latency = dev_priv->wm.skl_latency[level];
 
-   if (skl_needs_memory_bw_wa(intel_state) &&
+   if (intel_needs_memory_bw_wa(intel_state) &&
plane->base.state->fb->modifier ==
I915_FORMAT_MOD_X_TILED)
latency += 15;
@@ -3584,7 +3580,7 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
uint32_t y_min_scanlines;
struct intel_atomic_state *state =
to_intel_atomic_state(cstate->base.state);
-   bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
+   enum watermark_memory_wa mem_wa;
bool y_tiled, x_tiled;
 
if (latency == 0 || !cstate->base.active || 
!intel_pstate->base.visible) {
@@ -3600,7 +3596,8 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
latency += 4;
 
-   if (apply_memory_bw_wa && x_tiled)
+   mem_wa = state->wm_results.mem_wa;
+   if (mem_wa != WATERMARK_WA_NONE && x_tiled)
latency += 15;
 
 

[Intel-gfx] [PATCH v7 3/8] drm/i915/kbl: IPC workaround for kabylake

[Mahesh Kumar]

Display Workarounds #1141
IPC (Isoch Priority Control) may cause underflows.

KBL WA: When IPC is enabled, watermark latency values must be increased
by 4us across all levels. This brings level 0 up to 6us.

Changes since V1:
 - Add Workaround number in commit & code

Signed-off-by: Mahesh Kumar 
Reviewed-by: Paulo Zanoni 
---
 drivers/gpu/drm/i915/intel_pm.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89d8a28..3650c74 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3590,6 +3590,10 @@ static int skl_compute_plane_wm(const struct 
drm_i915_private *dev_priv,
fb->modifier == I915_FORMAT_MOD_Yf_TILED;
x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
 
+   /* IPC WA for kabylake Display WA #1141 */
+   if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)
+   latency += 4;
+
if (apply_memory_bw_wa && x_tiled)
latency += 15;
 
-- 
2.10.1

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[Intel-gfx] [PATCH 02/10] drm/i915: Make GEM object create and create from data take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Makes all GEM object constructors consistent.

v2: Fix compilation in GVT code.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson  (v1)
Reviewed-by: Joonas Lahtinen  (v1)
---
 drivers/gpu/drm/i915/gvt/cmd_parser.c  |  5 ++---
 drivers/gpu/drm/i915/i915_drv.h|  9 +
 drivers/gpu/drm/i915/i915_gem.c| 20 ++--
 drivers/gpu/drm/i915/i915_gem_context.c|  5 +++--
 drivers/gpu/drm/i915/i915_guc_submission.c |  2 +-
 drivers/gpu/drm/i915/i915_perf.c   |  2 +-
 drivers/gpu/drm/i915/intel_display.c   |  2 +-
 drivers/gpu/drm/i915/intel_fbdev.c |  2 +-
 drivers/gpu/drm/i915/intel_guc_loader.c|  5 +++--
 drivers/gpu/drm/i915/intel_lrc.c   |  4 ++--
 drivers/gpu/drm/i915/intel_overlay.c   |  2 +-
 drivers/gpu/drm/i915/intel_ringbuffer.c|  4 ++--
 12 files changed, 32 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c 
b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index d26a092c70e8..9a4b23c3ee97 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1602,7 +1602,7 @@ static int perform_bb_shadow(struct parser_exec_state *s)
return -ENOMEM;
 
entry_obj->obj =
-   i915_gem_object_create(&(s->vgpu->gvt->dev_priv->drm),
+   i915_gem_object_create(s->vgpu->gvt->dev_priv,
   roundup(bb_size, PAGE_SIZE));
if (IS_ERR(entry_obj->obj)) {
ret = PTR_ERR(entry_obj->obj);
@@ -2665,14 +2665,13 @@ int intel_gvt_scan_and_shadow_workload(struct 
intel_vgpu_workload *workload)
 
 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 {
-   struct drm_device *dev = _ctx->workload->vgpu->gvt->dev_priv->drm;
int ctx_size = wa_ctx->indirect_ctx.size;
unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
struct drm_i915_gem_object *obj;
int ret = 0;
void *map;
 
-   obj = i915_gem_object_create(dev,
+   obj = i915_gem_object_create(wa_ctx->workload->vgpu->gvt->dev_priv,
 roundup(ctx_size + CACHELINE_BYTES,
 PAGE_SIZE));
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 65d7a7811236..8b725d13d24e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2985,10 +2985,11 @@ void *i915_gem_object_alloc(struct drm_i915_private 
*dev_priv);
 void i915_gem_object_free(struct drm_i915_gem_object *obj);
 void i915_gem_object_init(struct drm_i915_gem_object *obj,
 const struct drm_i915_gem_object_ops *ops);
-struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
-  u64 size);
-struct drm_i915_gem_object *i915_gem_object_create_from_data(
-   struct drm_device *dev, const void *data, size_t size);
+struct drm_i915_gem_object *
+i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
+struct drm_i915_gem_object *
+i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
+const void *data, size_t size);
 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
 void i915_gem_free_object(struct drm_gem_object *obj);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index ab75d27b74d5..10c3b505f49a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -635,7 +635,7 @@ void i915_gem_object_free(struct drm_i915_gem_object *obj)
 
 static int
 i915_gem_create(struct drm_file *file,
-   struct drm_device *dev,
+   struct drm_i915_private *dev_priv,
uint64_t size,
uint32_t *handle_p)
 {
@@ -648,7 +648,7 @@ i915_gem_create(struct drm_file *file,
return -EINVAL;
 
/* Allocate the new object */
-   obj = i915_gem_object_create(dev, size);
+   obj = i915_gem_object_create(dev_priv, size);
if (IS_ERR(obj))
return PTR_ERR(obj);
 
@@ -670,7 +670,7 @@ i915_gem_dumb_create(struct drm_file *file,
/* have to work out size/pitch and return them */
args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
args->size = args->pitch * args->height;
-   return i915_gem_create(file, dev,
+   return i915_gem_create(file, to_i915(dev),
   args->size, >handle);
 }
 
@@ -684,11 +684,12 @@ int
 i915_gem_create_ioctl(struct drm_device *dev, void *data,
  struct drm_file *file)
 {
+   struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_create *args = data;
 
-   

[Intel-gfx] [PATCH 01/10] drm/i915: Make GEM object alloc/free and stolen created take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Where it is more appropriate and also to be consistent with
the direction of the driver.

v2: Leave out object alloc/free inlining. (Joonas Lahtinen)

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.h  |  6 +++---
 drivers/gpu/drm/i915/i915_gem.c  |  5 ++---
 drivers/gpu/drm/i915/i915_gem_dmabuf.c   |  2 +-
 drivers/gpu/drm/i915/i915_gem_internal.c |  2 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c   | 21 +
 drivers/gpu/drm/i915/i915_gem_userptr.c  |  2 +-
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_engine_cs.c   |  2 +-
 drivers/gpu/drm/i915/intel_fbdev.c   |  2 +-
 drivers/gpu/drm/i915/intel_overlay.c |  3 +--
 drivers/gpu/drm/i915/intel_pm.c  |  4 ++--
 drivers/gpu/drm/i915/intel_ringbuffer.c  |  2 +-
 12 files changed, 24 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 34f2b0da6a81..65d7a7811236 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2981,7 +2981,7 @@ void i915_gem_load_init_fences(struct drm_i915_private 
*dev_priv);
 int i915_gem_freeze(struct drm_i915_private *dev_priv);
 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
 
-void *i915_gem_object_alloc(struct drm_device *dev);
+void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
 void i915_gem_object_free(struct drm_i915_gem_object *obj);
 void i915_gem_object_init(struct drm_i915_gem_object *obj,
 const struct drm_i915_gem_object_ops *ops);
@@ -3366,9 +3366,9 @@ void i915_gem_stolen_remove_node(struct drm_i915_private 
*dev_priv,
 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_stolen(struct drm_device *dev);
 struct drm_i915_gem_object *
-i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
+i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
 struct drm_i915_gem_object *
-i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
+i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private 
*dev_priv,
   u32 stolen_offset,
   u32 gtt_offset,
   u32 size);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8ebefb6f6cf2..ab75d27b74d5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -622,9 +622,8 @@ i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
return ret;
 }
 
-void *i915_gem_object_alloc(struct drm_device *dev)
+void *i915_gem_object_alloc(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
 }
 
@@ -3990,7 +3989,7 @@ i915_gem_object_create(struct drm_device *dev, u64 size)
if (overflows_type(size, obj->base.size))
return ERR_PTR(-E2BIG);
 
-   obj = i915_gem_object_alloc(dev);
+   obj = i915_gem_object_alloc(dev_priv);
if (obj == NULL)
return ERR_PTR(-ENOMEM);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_dmabuf.c 
b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
index 5e38299b5df6..d037adcda6f2 100644
--- a/drivers/gpu/drm/i915/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/i915_gem_dmabuf.c
@@ -278,7 +278,7 @@ struct drm_gem_object *i915_gem_prime_import(struct 
drm_device *dev,
 
get_dma_buf(dma_buf);
 
-   obj = i915_gem_object_alloc(dev);
+   obj = i915_gem_object_alloc(to_i915(dev));
if (obj == NULL) {
ret = -ENOMEM;
goto fail_detach;
diff --git a/drivers/gpu/drm/i915/i915_gem_internal.c 
b/drivers/gpu/drm/i915/i915_gem_internal.c
index 4b3ff3e5b911..08d26306d40e 100644
--- a/drivers/gpu/drm/i915/i915_gem_internal.c
+++ b/drivers/gpu/drm/i915/i915_gem_internal.c
@@ -155,7 +155,7 @@ i915_gem_object_create_internal(struct drm_i915_private 
*i915,
 {
struct drm_i915_gem_object *obj;
 
-   obj = i915_gem_object_alloc(>drm);
+   obj = i915_gem_object_alloc(i915);
if (!obj)
return ERR_PTR(-ENOMEM);
 
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/i915_gem_stolen.c
index ebaa941c83af..b3bac2557665 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -579,22 +579,21 @@ static const struct drm_i915_gem_object_ops 
i915_gem_object_stolen_ops = {
 };
 
 static struct drm_i915_gem_object *
-_i915_gem_object_create_stolen(struct drm_device *dev,
+_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
   struct drm_mm_node *stolen)
 {

[Intel-gfx] [PATCH v2 00/10] GEM object create and driver init dev_priv cleanups

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Autumn of churn continues. :)

This series tidies GEM object construction to take dev_priv instead of dev
in all cases and also does a bit of random tidy in the driver load/init code.

Basically functions which only need dev_priv are changed to take dev_priv
instead of dev. There is often a cascade effect and the end result is a
saving in lines of code. And even in binary occasionally but not worth much
mention.

v2: Review feedback.

Tvrtko Ursulin (10):
  drm/i915: Make GEM object alloc/free and stolen created take dev_priv
  drm/i915: Make GEM object create and create from data take dev_priv
  drm/i915: Make various init functions take dev_priv
  drm/i915: More GEM init dev_priv cleanup
  drm/i915: dev_priv cleanup in bridge/bar/mmio init code
  drm/i915: Unexport VGA switcheroo functions
  drm/i915: Make gmbus setup take dev_priv
  drm/i915: Make i915_destroy_error_state take dev_priv
  drm/i915: Make i915_save/restore_state and intel_i2c_reset take
dev_priv
  drm/i915: Make intel_pm_setup take dev_priv

 drivers/gpu/drm/i915/i915_debugfs.c|   8 +--
 drivers/gpu/drm/i915/i915_drv.c| 108 +
 drivers/gpu/drm/i915/i915_drv.h|  63 +
 drivers/gpu/drm/i915/i915_gem.c|  72 ---
 drivers/gpu/drm/i915/i915_gem_context.c|  39 +--
 drivers/gpu/drm/i915/i915_gem_dmabuf.c |   2 +-
 drivers/gpu/drm/i915/i915_gem_internal.c   |   2 +-
 drivers/gpu/drm/i915/i915_gem_stolen.c |  21 +++---
 drivers/gpu/drm/i915/i915_gem_userptr.c|   2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c  |   5 +-
 drivers/gpu/drm/i915/i915_guc_submission.c |  12 ++--
 drivers/gpu/drm/i915/i915_perf.c   |   2 +-
 drivers/gpu/drm/i915/i915_suspend.c|  22 +++---
 drivers/gpu/drm/i915/i915_sysfs.c  |   4 +-
 drivers/gpu/drm/i915/intel_display.c   |   6 +-
 drivers/gpu/drm/i915/intel_drv.h   |   2 +-
 drivers/gpu/drm/i915/intel_engine_cs.c |   7 +-
 drivers/gpu/drm/i915/intel_fbdev.c |   4 +-
 drivers/gpu/drm/i915/intel_guc_loader.c|  36 +-
 drivers/gpu/drm/i915/intel_i2c.c   |  16 ++---
 drivers/gpu/drm/i915/intel_lrc.c   |   4 +-
 drivers/gpu/drm/i915/intel_lrc.h   |   2 +-
 drivers/gpu/drm/i915/intel_mocs.c  |   5 +-
 drivers/gpu/drm/i915/intel_mocs.h  |   2 +-
 drivers/gpu/drm/i915/intel_overlay.c   |   5 +-
 drivers/gpu/drm/i915/intel_pm.c|   8 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c|   6 +-
 drivers/gpu/drm/i915/intel_uc.h|  10 +--
 28 files changed, 214 insertions(+), 261 deletions(-)

-- 
2.7.4

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[Intel-gfx] [PATCH 07/10] drm/i915: Make gmbus setup take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Simplify the code by passing the right argument in.

v2: Commit message. (Joonas Lahtinen)

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c  | 4 ++--
 drivers/gpu/drm/i915/i915_drv.h  | 4 ++--
 drivers/gpu/drm/i915/intel_display.c | 2 +-
 drivers/gpu/drm/i915/intel_i2c.c | 8 +++-
 4 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 362c8baef640..fee0b46a04bc 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -592,7 +592,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_csr;
 
-   intel_setup_gmbus(dev);
+   intel_setup_gmbus(dev_priv);
 
/* Important: The output setup functions called by modeset_init need
 * working irqs for e.g. gmbus and dp aux transfers. */
@@ -629,7 +629,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
 cleanup_irq:
intel_guc_fini(dev_priv);
drm_irq_uninstall(dev);
-   intel_teardown_gmbus(dev);
+   intel_teardown_gmbus(dev_priv);
 cleanup_csr:
intel_csr_ucode_fini(dev_priv);
intel_power_domains_fini(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6cb4bb349c89..44aecad47b21 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3478,8 +3478,8 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv);
 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
 
 /* intel_i2c.c */
-extern int intel_setup_gmbus(struct drm_device *dev);
-extern void intel_teardown_gmbus(struct drm_device *dev);
+extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
+extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 unsigned int pin);
 
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 2785c619fa55..16fb90964a64 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -17162,7 +17162,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
 
intel_cleanup_gt_powersave(dev_priv);
 
-   intel_teardown_gmbus(dev);
+   intel_teardown_gmbus(dev_priv);
 }
 
 void intel_connector_attach_encoder(struct intel_connector *connector,
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 83f260bb4eef..85faba415633 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -617,11 +617,10 @@ static const struct i2c_algorithm gmbus_algorithm = {
 
 /**
  * intel_gmbus_setup - instantiate all Intel i2c GMBuses
- * @dev: DRM device
+ * @dev_priv: i915 device private
  */
-int intel_setup_gmbus(struct drm_device *dev)
+int intel_setup_gmbus(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
struct intel_gmbus *bus;
unsigned int pin;
@@ -724,9 +723,8 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, 
bool force_bit)
mutex_unlock(_priv->gmbus_mutex);
 }
 
-void intel_teardown_gmbus(struct drm_device *dev)
+void intel_teardown_gmbus(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_gmbus *bus;
unsigned int pin;
 
-- 
2.7.4

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[Intel-gfx] [PATCH 04/10] drm/i915: More GEM init dev_priv cleanup

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Simplifies the code to pass the right parameter in.

v2: Commit message. (Joonas Lahtinen)

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c |  8 
 drivers/gpu/drm/i915/i915_drv.h |  8 
 drivers/gpu/drm/i915/i915_gem.c | 10 +++---
 drivers/gpu/drm/i915/i915_gem_context.c |  5 ++---
 4 files changed, 13 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a7f85bdf8d66..383bf1ac1bdd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -544,8 +544,8 @@ static const struct vga_switcheroo_client_ops 
i915_switcheroo_ops = {
 static void i915_gem_fini(struct drm_i915_private *dev_priv)
 {
mutex_lock(_priv->drm.struct_mutex);
-   i915_gem_cleanup_engines(_priv->drm);
-   i915_gem_context_fini(_priv->drm);
+   i915_gem_cleanup_engines(dev_priv);
+   i915_gem_context_fini(dev_priv);
mutex_unlock(_priv->drm.struct_mutex);
 
rcu_barrier();
@@ -833,7 +833,7 @@ static int i915_driver_init_early(struct drm_i915_private 
*dev_priv,
intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
intel_init_audio_hooks(dev_priv);
-   ret = i915_gem_load_init(_priv->drm);
+   ret = i915_gem_load_init(dev_priv);
if (ret < 0)
goto err_gvt;
 
@@ -861,7 +861,7 @@ static int i915_driver_init_early(struct drm_i915_private 
*dev_priv,
 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 {
i915_perf_fini(dev_priv);
-   i915_gem_load_cleanup(_priv->drm);
+   i915_gem_load_cleanup(dev_priv);
i915_workqueues_cleanup(dev_priv);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bbc6d0f2d8bf..20bc0aef656a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2975,8 +2975,8 @@ int i915_gem_get_aperture_ioctl(struct drm_device *dev, 
void *data,
struct drm_file *file_priv);
 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
-int i915_gem_load_init(struct drm_device *dev);
-void i915_gem_load_cleanup(struct drm_device *dev);
+int i915_gem_load_init(struct drm_i915_private *dev_priv);
+void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
 int i915_gem_freeze(struct drm_i915_private *dev_priv);
 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
@@ -3180,7 +3180,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object 
*obj, bool force);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
-void i915_gem_cleanup_engines(struct drm_device *dev);
+void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
 int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
unsigned int flags);
 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
@@ -3269,7 +3269,7 @@ void i915_gem_object_save_bit_17_swizzle(struct 
drm_i915_gem_object *obj,
 /* i915_gem_context.c */
 int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv);
 void i915_gem_context_lost(struct drm_i915_private *dev_priv);
-void i915_gem_context_fini(struct drm_device *dev);
+void i915_gem_context_fini(struct drm_i915_private *dev_priv);
 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
 int i915_switch_context(struct drm_i915_gem_request *req);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b2a2e5843dc8..59065ae0b153 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4480,9 +4480,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
 }
 
 void
-i915_gem_cleanup_engines(struct drm_device *dev)
+i915_gem_cleanup_engines(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_engine_cs *engine;
enum intel_engine_id id;
 
@@ -4522,9 +4521,8 @@ i915_gem_load_init_fences(struct drm_i915_private 
*dev_priv)
 }
 
 int
-i915_gem_load_init(struct drm_device *dev)
+i915_gem_load_init(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
int err = -ENOMEM;
 
dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN);
@@ -4593,10 +4591,8 @@ i915_gem_load_init(struct drm_device *dev)

Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsi: Fix swapping of MIPI_SEQ_DEASSERT_RESET / MIPI_SEQ_ASSERT_RESET

[Hans de Goede]

Hi,

On 29-11-16 14:06, Hans de Goede wrote:




p.s.

I'm also trying to come up with some patches which properly
integrate pwm-lpss with the i915 driver instead of it
throwing a "Failed to own the pwm chip" error. But as soon
as I hook up things so that pwm_get() returns the pwm-lpss
pwm0 I hit:

https://bugs.freedesktop.org/show_bug.cgi?id=97330

I get the same pipe-a stuck (or not seeing vblank irqs?)
problems sometimes without the pwm-lpss driver in the loop
but then only sometimes and with pwm-lpss I get this
problem when loading the i915 driver most of the time
(but not all the time).

I've been debugging this a couple of evenings in a row
now, but no luck sofar.


Ok, a couple of more evenings of debugging + working on
this today has finally resulted in me finding a fix :)

The problem is that on driver load we call
chv_pipe_power_well_ops.enable() which calls
vlv_init_display_clock_gating() which clears
the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D
while the DSI panel is being driven by PIPE-A, as
already documented in intel_dsi_pre_enable()
allowing the DPOUNIT to get gated while DSI
active will result in a stuck PIPE-A.

I've written a patch for this, I'll send this
right after this mail, and attach it to bug:
https://bugs.freedesktop.org/show_bug.cgi?id=97330

Which I believe is the same issue.

Regards,

Hans
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[Intel-gfx] [PATCH 09/10] drm/i915: Make i915_save/restore_state and intel_i2c_reset take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

dev_priv is more appropriate since it is used much more in these.

v2: Commit message and keep the local pdev variable. (Joonas Lahtinen)

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h |  6 +++---
 drivers/gpu/drm/i915/i915_suspend.c | 16 +++-
 drivers/gpu/drm/i915/intel_i2c.c|  8 +++-
 4 files changed, 15 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 809315cad316..bd8994d02813 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1439,7 +1439,7 @@ static int i915_drm_suspend(struct drm_device *dev)
 
i915_gem_suspend_gtt_mappings(dev_priv);
 
-   i915_save_state(dev);
+   i915_save_state(dev_priv);
 
opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
intel_opregion_notify_adapter(dev_priv, opregion_target_state);
@@ -1562,7 +1562,7 @@ static int i915_drm_resume(struct drm_device *dev)
 
i915_gem_resume(dev_priv);
 
-   i915_restore_state(dev);
+   i915_restore_state(dev_priv);
intel_pps_unlock_regs_wa(dev_priv);
intel_opregion_setup(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2006ea033354..90ef5a09b40d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3470,8 +3470,8 @@ extern void i915_perf_register(struct drm_i915_private 
*dev_priv);
 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
 
 /* i915_suspend.c */
-extern int i915_save_state(struct drm_device *dev);
-extern int i915_restore_state(struct drm_device *dev);
+extern int i915_save_state(struct drm_i915_private *dev_priv);
+extern int i915_restore_state(struct drm_i915_private *dev_priv);
 
 /* i915_sysfs.c */
 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
@@ -3491,7 +3491,7 @@ static inline bool intel_gmbus_is_forced_bit(struct 
i2c_adapter *adapter)
 {
return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
 }
-extern void intel_i2c_reset(struct drm_device *dev);
+extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
 
 /* intel_bios.c */
 int intel_bios_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_suspend.c 
b/drivers/gpu/drm/i915/i915_suspend.c
index b0e1e7ca75da..5c86925a0294 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -56,13 +56,12 @@ static void i915_restore_display(struct drm_i915_private 
*dev_priv)
i915_redisable_vga(dev_priv);
 }
 
-int i915_save_state(struct drm_device *dev)
+int i915_save_state(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
int i;
 
-   mutex_lock(>struct_mutex);
+   mutex_lock(_priv->drm.struct_mutex);
 
i915_save_display(dev_priv);
 
@@ -97,18 +96,17 @@ int i915_save_state(struct drm_device *dev)
dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
}
 
-   mutex_unlock(>struct_mutex);
+   mutex_unlock(_priv->drm.struct_mutex);
 
return 0;
 }
 
-int i915_restore_state(struct drm_device *dev)
+int i915_restore_state(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
int i;
 
-   mutex_lock(>struct_mutex);
+   mutex_lock(_priv->drm.struct_mutex);
 
i915_gem_restore_fences(dev_priv);
 
@@ -145,9 +143,9 @@ int i915_restore_state(struct drm_device *dev)
I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
}
 
-   mutex_unlock(>struct_mutex);
+   mutex_unlock(_priv->drm.struct_mutex);
 
-   intel_i2c_reset(dev);
+   intel_i2c_reset(dev_priv);
 
return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 85faba415633..62fe529516b1 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -111,10 +111,8 @@ to_intel_gmbus(struct i2c_adapter *i2c)
 }
 
 void
-intel_i2c_reset(struct drm_device *dev)
+intel_i2c_reset(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
-
I915_WRITE(GMBUS0, 0);
I915_WRITE(GMBUS4, 0);
 }
@@ -211,7 +209,7 @@ intel_gpio_pre_xfer(struct i2c_adapter *adapter)
   adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
 
-   intel_i2c_reset(_priv->drm);
+   intel_i2c_reset(dev_priv);
intel_i2c_quirk_set(dev_priv, true);
set_data(bus, 1);

Re: [Intel-gfx] [PATCH i-g-t 2/3] tests/gem_reset_stats: test no progress detection

[Chris Wilson]

On Thu, Dec 01, 2016 at 03:31:44PM +0200, Mika Kuoppala wrote:
> If seqno is not incrementing but head is moving,
> we declare hang but much slower. Add test to check
> that this mechanism is working properly.
> 
> Signed-off-by: Mika Kuoppala 
> ---
>  tests/gem_reset_stats.c | 75 
> +
>  1 file changed, 75 insertions(+)
> 
> diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
> index 2718a33..669a30a 100644
> --- a/tests/gem_reset_stats.c
> +++ b/tests/gem_reset_stats.c
> @@ -711,6 +711,75 @@ static void defer_hangcheck(const struct 
> intel_execution_engine *engine)
>   close(fd);
>  }
>  
> +static void test_no_seqno_progress(const struct intel_execution_engine 
> *engine,
> +const bool use_ctx)
> +{
> + struct drm_i915_gem_relocation_entry reloc;
> + struct drm_i915_gem_execbuffer2 eb;
> + struct drm_i915_gem_exec_object2 exec;

I would advise using obj instead of exec

> + struct local_drm_i915_reset_stats before, after;
> + int len = 0, ctx, fd;
> + uint32_t batch[16*1024];

Not needed, see later.
#define BATCH_SIZE (16 << 10)

> + struct timespec ts_start;
> +
> + fd = drm_open_driver(DRIVER_INTEL);
> +
> + memset(, 0, sizeof(reloc));
> +memset(, 0, sizeof(exec));
> +memset(, 0, sizeof(eb));

> + memset(, 0, sizeof(batch));
> +
> + exec.handle = gem_create(fd, sizeof(batch));
> + exec.relocation_count = 1;
> +exec.relocs_ptr = (uintptr_t)
> +
> + igt_assert((int)exec.handle > 0);

Already asserted for you.

> +
> + if (use_ctx)
> + ctx = gem_context_create(fd);
> + else
> + ctx = 0;
> +
> + len = 2;
> + if (intel_gen(intel_get_drm_devid(fd)) >= 8)
> + len++;
> +
> + batch[sizeof(batch)/sizeof(uint32_t) - len] = MI_BATCH_BUFFER_START | 
> (len - 2);
> +gem_write(fd, exec.handle, 0, batch, sizeof(batch));

gem_write(fd, exec.handle, BATCH_SIZE - 16, , sizeof(cmd));

> +
> +reloc.offset = sizeof(batch) - ((len-1) * 4);

reloc.offset = BATCH_SIZE - 16 + sizeof(cmd);

> +reloc.delta = 0;
> +reloc.target_handle = exec.handle;
> +reloc.read_domains = I915_GEM_DOMAIN_COMMAND;

> + eb.buffers_ptr = (uintptr_t)
> + eb.buffer_count = 1;
> + eb.flags = engine->exec_id;
> +if (ctx)
> + i915_execbuffer2_set_context_id(eb, ctx);

eb.rsvd1 = ctx; It's perfectly fine to set it to zero.

> + igt_assert_eq(gem_reset_stats(fd, ctx, ), 0);
> +
> + clock_gettime(CLOCK_MONOTONIC, _start);

struct timespec ts = {};
igt_seconds_elapsed(_start)

> +
> + igt_assert_eq(0, __gem_execbuf(fd, ));

gem_execbuf();

> + igt_assert_lte(0, noop(fd, ctx, engine));

See earlier comments about noop.

> + gem_sync(fd, exec.handle);
> +
> + igt_assert_lte(0, noop(fd, ctx, engine));
> + igt_assert_eq(gem_reset_stats(fd, ctx, ), 0);
> +
> + sync_gpu();
> +
> + igt_assert(after.batch_active == before.batch_active + 1);

igt_assert_eq(after, before + 1);

> + gem_close(fd, exec.handle);
> + close(fd);
> +
> + igt_assert(igt_seconds_elapsed(_start) > 5);

You really want to demand a minimum time?

> + igt_assert(igt_seconds_elapsed(_start) < 15);

Play state thy sources. Upper bound should be closer to 120s.
-Chris

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Re: [Intel-gfx] [PATCH 12/15] drm/i915: Zero out HOWM registers before writing new WM/HOWM register values

[Maarten Lankhorst]

Op 28-11-16 om 18:37 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä 
>
> On VLV/CHV some of the watermark values are split across two registers:
> low order bits in one, and high order bits in another. So we may not be
> able to update a single watermark value atomically, and thus we must be
> careful that we don't temporarily introduce out of bounds values during
> the reprogramming. To prevent this we can simply zero out all the high
> order bits initially, then we update the low order bits, and finally
> we update the high order bits with the final value.
>
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 17 +++--
>  1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9f25f2195a6a..8a3441bbff30 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -877,6 +877,17 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
>  (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
>  (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
>  
> + /*
> +  * Zero the (unused) WM1 watermarks, and also clear all the
> +  * high order bits so that there are no out of bounds values
> +  * present in the registers during the reprogramming.
> +  */
> + I915_WRITE(DSPHOWM, 0);
> + I915_WRITE(DSPHOWM1, 0);
> + I915_WRITE(DSPFW4, 0);
> + I915_WRITE(DSPFW5, 0);
> + I915_WRITE(DSPFW6, 0);
Watermarks for DSPHOWM are inverted right? And lower values just mean more 
wakeups?
Should be harmless then.

Reviewed-by: Maarten Lankhorst 
>   I915_WRITE(DSPFW1,
>  FW_WM(wm->sr.plane, SR) |
>  FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
> @@ -924,12 +935,6 @@ static void vlv_write_wm_values(struct intel_crtc *crtc,
>  FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, 
> PLANEA_HI));
>   }
>  
> - /* zero (unused) WM1 watermarks */
> - I915_WRITE(DSPFW4, 0);
> - I915_WRITE(DSPFW5, 0);
> - I915_WRITE(DSPFW6, 0);
> - I915_WRITE(DSPHOWM1, 0);
> -
>   POSTING_READ(DSPFW1);
>  }
>  


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[Intel-gfx] [PATCH] drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating

[Hans de Goede]

On my Cherrytrail CUBE iwork8 Air tablet PIPE-A would get stuck on loading
i915 at boot 1 out of every 3 boots, resulting in a non functional LCD.
Once the i915 driver has successfully loaded, the panel can be disabled /
enabled without hitting this issue.

The getting stuck is caused by vlv_init_display_clock_gating() clearing
the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D when called from
chv_pipe_power_well_ops.enable() on driver load, while PIPE-A is enabled
driving the DSI LCD by the BIOS.

Clearing this bit while DSI is in use is a known issue and
intel_dsi_pre_enable() / intel_dsi_post_disable() already set / clear it
as appropriate.

This commit modifies vlv_init_display_clock_gating() to leave the
DPOUNIT_CLOCK_GATE_DISABLE bit alone fixing PIPE-A getting stuck.

BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=97330
Cc: sta...@vger.kernel.org
Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 356c662..b5ce7cb 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1039,7 +1039,18 @@ static bool vlv_power_well_enabled(struct 
drm_i915_private *dev_priv,
 
 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 {
-   I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
+   u32 val;
+
+   /*
+* When on driver load, PIPE A may be active and driving a DSI display.
+* Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid PIPE A getting stuck
+* (and never recovering) in this case. intel_dsi_post_disable() will
+* clear it when we turn off the display.
+*/
+   val = I915_READ(DSPCLK_GATE_D);
+   val &= DPOUNIT_CLOCK_GATE_DISABLE;
+   val |= VRHUNIT_CLOCK_GATE_DISABLE;
+   I915_WRITE(DSPCLK_GATE_D, val);
 
/*
 * Disable trickle feed and enable pnd deadline calculation
-- 
2.9.3

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[Intel-gfx] [PATCH 05/10] drm/i915: dev_priv cleanup in bridge/bar/mmio init code

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

dev_priv is more appropriate for these so converting saves
some lines of source.

v2: Commit message and keep the pdev local variable. (Joonas Lahtinen)

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson  (v1)
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c | 45 -
 1 file changed, 17 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 383bf1ac1bdd..1312cd5e4465 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -142,9 +142,8 @@ static enum intel_pch intel_virt_detect_pch(struct 
drm_i915_private *dev_priv)
return ret;
 }
 
-static void intel_detect_pch(struct drm_device *dev)
+static void intel_detect_pch(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pch = NULL;
 
/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
@@ -361,10 +360,8 @@ static int i915_getparam(struct drm_device *dev, void 
*data,
return 0;
 }
 
-static int i915_get_bridge_dev(struct drm_device *dev)
+static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
-
dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
if (!dev_priv->bridge_dev) {
DRM_ERROR("bridge device not found\n");
@@ -375,9 +372,8 @@ static int i915_get_bridge_dev(struct drm_device *dev)
 
 /* Allocate space for the MCH regs if needed, return nonzero on error */
 static int
-intel_alloc_mchbar_resource(struct drm_device *dev)
+intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp_lo, temp_hi = 0;
u64 mchbar_addr;
@@ -421,9 +417,8 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
 
 /* Setup MCHBAR if possible, return true if we should disable it again */
 static void
-intel_setup_mchbar(struct drm_device *dev)
+intel_setup_mchbar(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp;
bool enabled;
@@ -445,7 +440,7 @@ intel_setup_mchbar(struct drm_device *dev)
if (enabled)
return;
 
-   if (intel_alloc_mchbar_resource(dev))
+   if (intel_alloc_mchbar_resource(dev_priv))
return;
 
dev_priv->mchbar_need_disable = true;
@@ -461,9 +456,8 @@ intel_setup_mchbar(struct drm_device *dev)
 }
 
 static void
-intel_teardown_mchbar(struct drm_device *dev)
+intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 
if (dev_priv->mchbar_need_disable) {
@@ -493,9 +487,9 @@ intel_teardown_mchbar(struct drm_device *dev)
 /* true = enable decode, false = disable decoder */
 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 {
-   struct drm_device *dev = cookie;
+   struct drm_i915_private *dev_priv = cookie;
 
-   intel_modeset_vga_set_state(to_i915(dev), state);
+   intel_modeset_vga_set_state(dev_priv, state);
if (state)
return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
   VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
@@ -574,7 +568,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
 * then we do not take part in VGA arbitration and the
 * vga_client_register() fails with -ENODEV.
 */
-   ret = vga_client_register(pdev, dev, NULL, i915_vga_set_decode);
+   ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
if (ret && ret != -ENODEV)
goto out;
 
@@ -823,7 +817,7 @@ static int i915_driver_init_early(struct drm_i915_private 
*dev_priv,
goto err_workqueues;
 
/* This must be called before any calls to HAS_PCH_* */
-   intel_detect_pch(_priv->drm);
+   intel_detect_pch(dev_priv);
 
intel_pm_setup(_priv->drm);
intel_init_dpio(dev_priv);
@@ -865,9 +859,8 @@ static void i915_driver_cleanup_early(struct 
drm_i915_private *dev_priv)
i915_workqueues_cleanup(dev_priv);
 }
 
-static int i915_mmio_setup(struct drm_device *dev)
+static int i915_mmio_setup(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
int mmio_bar;
int mmio_size;
@@ -893,17 +886,16 @@ static int i915_mmio_setup(struct drm_device *dev)
}
 
/* Try to make sure MCHBAR 

Re: [Intel-gfx] [PATCH i-g-t 1/3] tests/gem_reset_stats: Change pending/active assertions

[Chris Wilson]

How about a patch 0 to enable hang testing contexts on all rings now?
Then exploration of how one ring affects another...

You will want to use busy batches to load the engines without hanging,
that will be tricky...

On Thu, Dec 01, 2016 at 03:31:43PM +0200, Mika Kuoppala wrote:
> Now that we replay the non guilty contexts and always replay
> the default ctx, even when guilty, the assumptions of how many
> active and pending batches there was in the time of reset has
> changed.
> 
> Driver doesn't increment pending counts for contexts that it
> considered unaffected by reset. Because it can now replay the
> queued requests.
> 
> For contexts, guilty of reset, we replay the request envelopes,
> but nop the batchbuffer starts. This changes of how many 'hangs'
> we think there were queued. As future queued hangs are now NOPed
> out, we need to change the assumption of active counts also.
> 
> Adapt to these changes of how the replaying of batches affect
> the assertions in pending/active counting and banning tests.
> While doing this, throw out the retrying to be more strict about
> the determinism we want to achieve.
> 
> Cc: Chris Wilson 
> Signed-off-by: Mika Kuoppala 
> ---
>  tests/gem_reset_stats.c | 154 
> ++--
>  1 file changed, 56 insertions(+), 98 deletions(-)
> 
> diff --git a/tests/gem_reset_stats.c b/tests/gem_reset_stats.c
> index 3de74af..2718a33 100644
> --- a/tests/gem_reset_stats.c
> +++ b/tests/gem_reset_stats.c
> @@ -152,7 +152,7 @@ static struct timespec ts_injected;
>  
>  #define BAN HANG_ALLOW_BAN
>  #define ASYNC 2
> -static void inject_hang(int fd, uint32_t ctx,
> +static bool inject_hang(int fd, uint32_t ctx,
>   const struct intel_execution_engine *e,
>   unsigned flags)
>  {
> @@ -163,6 +163,8 @@ static void inject_hang(int fd, uint32_t ctx,
>   hang = igt_hang_ctx(fd, ctx, e->exec_id | e->flags, flags & BAN, NULL);
>   if ((flags & ASYNC) == 0)
>   igt_post_hang_ring(fd, hang);
> +
> + return hang.handle >= 0;

Never returns false. Future patch?

>  static const char *status_to_string(int x)
> @@ -239,7 +241,7 @@ static void test_rs(const struct intel_execution_engine 
> *e,
>   if (i == hang_index)
>   assert_reset_status(i, fd[i], 0, RS_BATCH_ACTIVE);
>   if (i > hang_index)
> - assert_reset_status(i, fd[i], 0, RS_BATCH_PENDING);
> + assert_reset_status(i, fd[i], 0, RS_NO_ERROR);
>   }
>  
>   igt_assert(igt_seconds_elapsed(_injected) <= 30);
> @@ -312,10 +314,10 @@ static void test_rs_ctx(const struct 
> intel_execution_engine *e,
>   RS_BATCH_ACTIVE);
>   if (i == hang_index && j > hang_context)
>   assert_reset_status(i, fd[i], ctx[i][j],
> - RS_BATCH_PENDING);
> + RS_NO_ERROR);
>   if (i > hang_index)
>   assert_reset_status(i, fd[i], ctx[i][j],
> - RS_BATCH_PENDING);
> + RS_NO_ERROR);
>   }
>   }
>  
> @@ -325,128 +327,84 @@ static void test_rs_ctx(const struct 
> intel_execution_engine *e,
>   }
>  }
>  
> -static void test_ban(const struct intel_execution_engine *e)
> +static void test_ban_ctx(const struct intel_execution_engine *e,
> +  const bool ban_default)
>  {
>   struct local_drm_i915_reset_stats rs_bad, rs_good;
> - int fd_bad, fd_good;
> - int ban, retry = 10;
> + int fd_bad, fd_good, i;
> + uint32_t ctx_good, ctx_bad;
>   int active_count = 0, pending_count = 0;
>  
>   fd_bad = drm_open_driver(DRIVER_INTEL);
>   fd_good = drm_open_driver(DRIVER_INTEL);
>  
> - assert_reset_status(fd_bad, fd_bad, 0, RS_NO_ERROR);
> + ctx_good = gem_context_create(fd_bad);
> + if (!ban_default)
> + ctx_bad = gem_context_create(fd_bad);
> + else
> + ctx_bad = 0;
> +
> + assert_reset_status(fd_bad, fd_bad, ctx_bad, RS_NO_ERROR);
> + assert_reset_status(fd_bad, fd_bad, ctx_good, RS_NO_ERROR);
>   assert_reset_status(fd_good, fd_good, 0, RS_NO_ERROR);
>  
> - noop(fd_bad, 0, e);
> - noop(fd_good, 0, e);
> + igt_assert_lt(0, noop(fd_bad, ctx_bad, e));
> + igt_assert_lt(0, noop(fd_bad, ctx_good, e));
> + igt_assert_lt(0, noop(fd_good, 0, e));

Yuck.

__noop();
noop() { igt_assert_eq(__noop, 0));

(Or better names than noop? )

Otherwise, lgtm. R-b if you feel so inclined.
-Chris

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[Intel-gfx] [PATCH 10/10] drm/i915: Make intel_pm_setup take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Function actually wants dev_priv so give it to it.

v2: Commit message. (Joonas Lahtinen)

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c  | 2 +-
 drivers/gpu/drm/i915/intel_drv.h | 2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 4 +---
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index bd8994d02813..ace9be8f6ff9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -822,7 +822,7 @@ static int i915_driver_init_early(struct drm_i915_private 
*dev_priv,
/* This must be called before any calls to HAS_PCH_* */
intel_detect_pch(dev_priv);
 
-   intel_pm_setup(_priv->drm);
+   intel_pm_setup(dev_priv);
intel_init_dpio(dev_priv);
intel_power_domains_init(dev_priv);
intel_irq_init(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 460f3742ebd7..1d126c29598f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1724,7 +1724,7 @@ int ilk_wm_max_level(const struct drm_i915_private 
*dev_priv);
 void intel_update_watermarks(struct intel_crtc *crtc);
 void intel_init_pm(struct drm_i915_private *dev_priv);
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
-void intel_pm_setup(struct drm_device *dev);
+void intel_pm_setup(struct drm_i915_private *dev_priv);
 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 void intel_gpu_ips_teardown(void);
 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ca31cdd82ebd..c45ee1732715 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7955,10 +7955,8 @@ void intel_queue_rps_boost_for_request(struct 
drm_i915_gem_request *req)
queue_work(req->i915->wq, >work);
 }
 
-void intel_pm_setup(struct drm_device *dev)
+void intel_pm_setup(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
-
mutex_init(_priv->rps.hw_lock);
spin_lock_init(_priv->rps.client_lock);
 
-- 
2.7.4

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[Intel-gfx] [PATCH 03/10] drm/i915: Make various init functions take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Like GEM init, GUC init, MOCS init and context creation.

Enables them to lose dev_priv locals.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c| 31 ++--
 drivers/gpu/drm/i915/i915_drv.h| 10 -
 drivers/gpu/drm/i915/i915_gem.c| 28 -
 drivers/gpu/drm/i915/i915_gem_context.c| 31 +---
 drivers/gpu/drm/i915/i915_guc_submission.c | 10 -
 drivers/gpu/drm/i915/intel_engine_cs.c |  5 ++---
 drivers/gpu/drm/i915/intel_guc_loader.c| 33 ++
 drivers/gpu/drm/i915/intel_lrc.h   |  2 +-
 drivers/gpu/drm/i915/intel_mocs.c  |  5 ++---
 drivers/gpu/drm/i915/intel_mocs.h  |  2 +-
 drivers/gpu/drm/i915/intel_uc.h| 10 -
 11 files changed, 77 insertions(+), 90 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 89af78eb5c32..a7f85bdf8d66 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -603,9 +603,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_irq;
 
-   intel_guc_init(dev);
+   intel_guc_init(dev_priv);
 
-   ret = i915_gem_init(dev);
+   ret = i915_gem_init(dev_priv);
if (ret)
goto cleanup_irq;
 
@@ -626,11 +626,11 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
 
 cleanup_gem:
-   if (i915_gem_suspend(dev))
+   if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev_priv);
 cleanup_irq:
-   intel_guc_fini(dev);
+   intel_guc_fini(dev_priv);
drm_irq_uninstall(dev);
intel_teardown_gmbus(dev);
 cleanup_csr:
@@ -1283,7 +1283,7 @@ void i915_driver_unload(struct drm_device *dev)
 
intel_fbdev_fini(dev);
 
-   if (i915_gem_suspend(dev))
+   if (i915_gem_suspend(dev_priv))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
 
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
@@ -1320,7 +1320,7 @@ void i915_driver_unload(struct drm_device *dev)
/* Flush any outstanding unpin_work. */
drain_workqueue(dev_priv->wq);
 
-   intel_guc_fini(dev);
+   intel_guc_fini(dev_priv);
i915_gem_fini(dev_priv);
intel_fbc_cleanup_cfb(dev_priv);
 
@@ -1425,14 +1425,14 @@ static int i915_drm_suspend(struct drm_device *dev)
 
pci_save_state(pdev);
 
-   error = i915_gem_suspend(dev);
+   error = i915_gem_suspend(dev_priv);
if (error) {
dev_err(>dev,
"GEM idle failed, resume might fail\n");
goto out;
}
 
-   intel_guc_suspend(dev);
+   intel_guc_suspend(dev_priv);
 
intel_display_suspend(dev);
 
@@ -1568,7 +1568,7 @@ static int i915_drm_resume(struct drm_device *dev)
 
intel_csr_ucode_resume(dev_priv);
 
-   i915_gem_resume(dev);
+   i915_gem_resume(dev_priv);
 
i915_restore_state(dev);
intel_pps_unlock_regs_wa(dev_priv);
@@ -1591,13 +1591,13 @@ static int i915_drm_resume(struct drm_device *dev)
drm_mode_config_reset(dev);
 
mutex_lock(>struct_mutex);
-   if (i915_gem_init_hw(dev)) {
+   if (i915_gem_init_hw(dev_priv)) {
DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
i915_gem_set_wedged(dev_priv);
}
mutex_unlock(>struct_mutex);
 
-   intel_guc_resume(dev);
+   intel_guc_resume(dev_priv);
 
intel_modeset_init_hw(dev);
 
@@ -1770,11 +1770,10 @@ static void enable_engines_irq(struct drm_i915_private 
*dev_priv)
  */
 void i915_reset(struct drm_i915_private *dev_priv)
 {
-   struct drm_device *dev = _priv->drm;
struct i915_gpu_error *error = _priv->gpu_error;
int ret;
 
-   lockdep_assert_held(>struct_mutex);
+   lockdep_assert_held(_priv->drm.struct_mutex);
 
if (!test_and_clear_bit(I915_RESET_IN_PROGRESS, >flags))
return;
@@ -1814,7 +1813,7 @@ void i915_reset(struct drm_i915_private *dev_priv)
 * was running at the time of the reset (i.e. we weren't VT
 * switched away).
 */
-   ret = i915_gem_init_hw(dev);
+   ret = i915_gem_init_hw(dev_priv);
if (ret) {
DRM_ERROR("Failed hw init on reset %d\n", ret);
goto error;
@@ -2328,7 +2327,7 @@ static int intel_runtime_suspend(struct device *kdev)
 */
i915_gem_runtime_suspend(dev_priv);
 
-   intel_guc_suspend(dev);
+   intel_guc_suspend(dev_priv);
 
intel_runtime_pm_disable_interrupts(dev_priv);
 

[Intel-gfx] [PATCH 08/10] drm/i915: Make i915_destroy_error_state take dev_priv

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

Since it does not need dev at all.

Also change the stored pointer in struct i915_error_state_file_priv
to i915.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_debugfs.c   | 8 
 drivers/gpu/drm/i915/i915_drv.c   | 2 +-
 drivers/gpu/drm/i915/i915_drv.h   | 6 +++---
 drivers/gpu/drm/i915/i915_gpu_error.c | 5 ++---
 drivers/gpu/drm/i915/i915_sysfs.c | 4 ++--
 5 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 2434130087be..d006ed131a54 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -946,7 +946,7 @@ i915_error_state_write(struct file *filp,
struct i915_error_state_file_priv *error_priv = filp->private_data;
 
DRM_DEBUG_DRIVER("Resetting error state\n");
-   i915_destroy_error_state(error_priv->dev);
+   i915_destroy_error_state(error_priv->i915);
 
return cnt;
 }
@@ -960,7 +960,7 @@ static int i915_error_state_open(struct inode *inode, 
struct file *file)
if (!error_priv)
return -ENOMEM;
 
-   error_priv->dev = _priv->drm;
+   error_priv->i915 = dev_priv;
 
i915_error_state_get(_priv->drm, error_priv);
 
@@ -988,8 +988,8 @@ static ssize_t i915_error_state_read(struct file *file, 
char __user *userbuf,
ssize_t ret_count = 0;
int ret;
 
-   ret = i915_error_state_buf_init(_str,
-   to_i915(error_priv->dev), count, *pos);
+   ret = i915_error_state_buf_init(_str, error_priv->i915,
+   count, *pos);
if (ret)
return ret;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index fee0b46a04bc..809315cad316 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1307,7 +1307,7 @@ void i915_driver_unload(struct drm_device *dev)
 
/* Free error state after interrupts are fully disabled. */
cancel_delayed_work_sync(_priv->gpu_error.hangcheck_work);
-   i915_destroy_error_state(dev);
+   i915_destroy_error_state(dev_priv);
 
/* Flush any outstanding unpin_work. */
drain_workqueue(dev_priv->wq);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44aecad47b21..2006ea033354 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1459,7 +1459,7 @@ struct drm_i915_error_state_buf {
 };
 
 struct i915_error_state_file_priv {
-   struct drm_device *dev;
+   struct drm_i915_private *i915;
struct drm_i915_error_state *error;
 };
 
@@ -3434,7 +3434,7 @@ void i915_capture_error_state(struct drm_i915_private 
*dev_priv,
 void i915_error_state_get(struct drm_device *dev,
  struct i915_error_state_file_priv *error_priv);
 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
-void i915_destroy_error_state(struct drm_device *dev);
+void i915_destroy_error_state(struct drm_i915_private *dev_priv);
 
 #else
 
@@ -3444,7 +3444,7 @@ static inline void i915_capture_error_state(struct 
drm_i915_private *dev_priv,
 {
 }
 
-static inline void i915_destroy_error_state(struct drm_device *dev)
+static inline void i915_destroy_error_state(struct drm_i915_private *dev_priv)
 {
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
b/drivers/gpu/drm/i915/i915_gpu_error.c
index 82458ea60150..a14f7badc337 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -514,7 +514,7 @@ static void err_print_capabilities(struct 
drm_i915_error_state_buf *m,
 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
const struct i915_error_state_file_priv *error_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(error_priv->dev);
+   struct drm_i915_private *dev_priv = error_priv->i915;
struct pci_dev *pdev = dev_priv->drm.pdev;
struct drm_i915_error_state *error = error_priv->error;
struct drm_i915_error_object *obj;
@@ -1644,9 +1644,8 @@ void i915_error_state_put(struct 
i915_error_state_file_priv *error_priv)
kref_put(_priv->error->ref, i915_error_state_free);
 }
 
-void i915_destroy_error_state(struct drm_device *dev)
+void i915_destroy_error_state(struct drm_i915_private *dev_priv)
 {
-   struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_error_state *error;
 
spin_lock_irq(_priv->gpu_error.lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c 
b/drivers/gpu/drm/i915/i915_sysfs.c
index 47590ab08d7e..b99fd9668317 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -535,7 +535,7 @@ 

[Intel-gfx] [PATCH 06/10] drm/i915: Unexport VGA switcheroo functions

[Tvrtko Ursulin]

From: Tvrtko Ursulin 

They are only used in i915_drv.c so a forward declaration is enough.

Signed-off-by: Tvrtko Ursulin 
Reviewed-by: Chris Wilson 
Reviewed-by: Joonas Lahtinen 
---
 drivers/gpu/drm/i915/i915_drv.c | 5 -
 drivers/gpu/drm/i915/i915_drv.h | 3 ---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1312cd5e4465..362c8baef640 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -497,6 +497,9 @@ static unsigned int i915_vga_set_decode(void *cookie, bool 
state)
return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 }
 
+static int i915_resume_switcheroo(struct drm_device *dev);
+static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
+
 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum 
vga_switcheroo_state state)
 {
struct drm_device *dev = pci_get_drvdata(pdev);
@@ -1710,7 +1713,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
return ret;
 }
 
-int i915_resume_switcheroo(struct drm_device *dev)
+static int i915_resume_switcheroo(struct drm_device *dev)
 {
int ret;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 20bc0aef656a..6cb4bb349c89 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2759,9 +2759,6 @@ static inline bool intel_scanout_needs_vtd_wa(struct 
drm_i915_private *dev_priv)
return false;
 }
 
-extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
-extern int i915_resume_switcheroo(struct drm_device *dev);
-
 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
int enable_ppgtt);
 
-- 
2.7.4

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Re: [Intel-gfx] [PATCH 15/15] drm/i915: Pass crtc state to vlv_compute_wm_level()

[Maarten Lankhorst]

Op 28-11-16 om 18:37 schreef ville.syrj...@linux.intel.com:
> From: Ville Syrjälä 
>
> Rather than accessing crtc->config in vlv_compute_wm_level() let's
> pass in the crtc state explicitly. One step closer to atomic.
>
> Signed-off-by: Ville Syrjälä 
Yay. All users of intel_crtc->config have to die in the future, but this is 
temporarily a legit use for it.

For patch 13, 14 and 15

Reviewed-by: Maarten Lankhorst 
>  drivers/gpu/drm/i915/intel_pm.c | 20 +++-
>  1 file changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 291843c2b61b..2a2aa8968b93 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -978,24 +978,26 @@ static void vlv_setup_wm_latency(struct 
> drm_i915_private *dev_priv)
>   }
>  }
>  
> -static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
> -  struct intel_crtc *crtc,
> -  const struct intel_plane_state *state,
> +static uint16_t vlv_compute_wm_level(const struct intel_crtc_state 
> *crtc_state,
> +  const struct intel_plane_state 
> *plane_state,
>int level)
>  {
> + struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
>   struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + const struct drm_display_mode *adjusted_mode =
> + _state->base.adjusted_mode;
>   int clock, htotal, cpp, width, wm;
>  
>   if (dev_priv->wm.pri_latency[level] == 0)
>   return USHRT_MAX;
>  
> - if (!state->base.visible)
> + if (!plane_state->base.visible)
>   return 0;
>  
> - cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
> - clock = crtc->config->base.adjusted_mode.crtc_clock;
> - htotal = crtc->config->base.adjusted_mode.crtc_htotal;
> - width = crtc->config->pipe_src_w;
> + cpp = drm_format_plane_cpp(plane_state->base.fb->pixel_format, 0);
> + clock = adjusted_mode->crtc_clock;
> + htotal = adjusted_mode->crtc_htotal;
> + width = crtc_state->pipe_src_w;
>   if (WARN_ON(htotal == 0))
>   htotal = 1;
>  
> @@ -1145,7 +1147,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
>  
>   /* normal watermarks */
>   for (level = 0; level < wm_state->num_levels; level++) {
> - int wm = vlv_compute_wm_level(plane, crtc, state, 
> level);
> + int wm = vlv_compute_wm_level(crtc->config, state, 
> level);
>   int max_wm = plane->wm.fifo_size;
>  
>   /* hack */


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Re: [Intel-gfx] 4.8.6, NULL pointer in __wake_up_common / drm / i915

[Olaf Hering]

On Wed, Nov 16, Olaf Hering wrote:

> During boot into a current openSUSE Tumbleweed 20161108 this laptop
> starts to hang sometimes with 4.8.x.  Today I was able to catch this
> crash in __wake_up_common caused by i915 or drm or whatever:
> 
> ...
> [   69.851635] BUG: unable to handle kernel NULL pointer dereference at   
> (null)
> [   69.851754] IP: [] __wake_up_common+0x25/0x80

This still happens with 4.8.10.

Any idea how to fix it?

Olaf

[0.00] microcode: microcode updated early to revision 0xa4, date = 
2010-10-02
[0.00] Linux version 4.8.10-1-default (geeko@buildhost) (gcc version 
6.2.1 20160830 [gcc-6-branch revision 239856] (SUSE Linux) ) #1 SMP PREEMPT Mon 
Nov 21 13:50:28 UTC 2016 (d1ec066)
[0.00] Command line: 
BOOT_IMAGE=(lvm/sd240_crypt_lvm-sd240_btrfs)/tw_xfce/boot/vmlinuz quiet panic=9 
net.ifnames=0 rootflags=subvol=/tw_xfce,noatime plymouth.enable=0 
resume=/dev/disk/by-label/SD240_CRYPT_SWP
[0.00] x86/fpu: Legacy x87 FPU detected.
[0.00] x86/fpu: Using 'eager' FPU context switches.
[0.00] e820: BIOS-provided physical RAM map:
[0.00] BIOS-e820: [mem 0x-0x0009f7ff] usable
[0.00] BIOS-e820: [mem 0x0009f800-0x0009] reserved
[0.00] BIOS-e820: [mem 0x000dc000-0x000f] reserved
[0.00] BIOS-e820: [mem 0x0010-0xbf67] usable
[0.00] BIOS-e820: [mem 0xbf68-0xbf690fff] ACPI NVS
[0.00] BIOS-e820: [mem 0xbf691000-0xbfff] reserved
[0.00] BIOS-e820: [mem 0xe000-0xefff] reserved
[0.00] BIOS-e820: [mem 0xfec0-0xfec0] reserved
[0.00] BIOS-e820: [mem 0xfed0-0xfed003ff] reserved
[0.00] BIOS-e820: [mem 0xfed14000-0xfed19fff] reserved
[0.00] BIOS-e820: [mem 0xfed1c000-0xfed8] reserved
[0.00] BIOS-e820: [mem 0xfee0-0xfee00fff] reserved
[0.00] BIOS-e820: [mem 0xff00-0x] reserved
[0.00] BIOS-e820: [mem 0x0001-0x00013fff] usable
[0.00] NX (Execute Disable) protection: active
[0.00] SMBIOS 2.4 present.
[0.00] DMI: FUJITSU SIEMENS ESPRIMO Mobile M9400/M11D, BIOS 1.06 - R059 
- 1566 04/22/2008
[0.00] e820: update [mem 0x-0x0fff] usable ==> reserved
[0.00] e820: remove [mem 0x000a-0x000f] usable
[0.00] e820: last_pfn = 0x14 max_arch_pfn = 0x4
[0.00] MTRR default type: uncachable
[0.00] MTRR fixed ranges enabled:
[0.00]   0-9 write-back
[0.00]   A-B uncachable
[0.00]   C-F write-protect
[0.00] MTRR variable ranges enabled:
[0.00]   0 base 0C000 mask FC000 uncachable
[0.00]   1 base 0 mask F write-back
[0.00]   2 base 1 mask FC000 write-back
[0.00]   3 base 0BF70 mask 0 uncachable
[0.00]   4 base 0BF80 mask FFF80 uncachable
[0.00]   5 disabled
[0.00]   6 disabled
[0.00]   7 disabled
[0.00] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- WT  
[0.00] e820: update [mem 0xbf70-0x] usable ==> reserved
[0.00] e820: last_pfn = 0xbf680 max_arch_pfn = 0x4
[0.00] found SMP MP-table at [mem 0x000f77a0-0x000f77af] mapped at 
[8801c00f77a0]
[0.00] Scanning 1 areas for low memory corruption
[0.00] Base memory trampoline at [8801c0099000] 99000 size 24576
[0.00] BRK [0x108262000, 0x108262fff] PGTABLE
[0.00] BRK [0x108263000, 0x108263fff] PGTABLE
[0.00] BRK [0x108264000, 0x108264fff] PGTABLE
[0.00] BRK [0x108265000, 0x108265fff] PGTABLE
[0.00] BRK [0x108266000, 0x108266fff] PGTABLE
[0.00] BRK [0x108267000, 0x108267fff] PGTABLE
[0.00] BRK [0x108268000, 0x108268fff] PGTABLE
[0.00] BRK [0x108269000, 0x108269fff] PGTABLE
[0.00] RAMDISK: [mem 0x35b33000-0x36d90fff]
[0.00] ACPI: Early table checksum verification disabled
[0.00] ACPI: RSDP 0x000F7710 24 (v02 PTLTD )
[0.00] ACPI: XSDT 0xBF688021 8C (v01 FSCPC   
0604  LTP )
[0.00] ACPI: FACP 0xBF68FD0C F4 (v03 INTEL  CRESTLNE 
0604 ALAN 0001)
[0.00] ACPI: DSDT 0xBF689526 006772 (v02 IEC___ M11_ 
0604 INTL 20050624)
[0.00] ACPI: FACS 0xBF690FC0 40
[0.00] ACPI: FACS 0xBF690FC0 40
[0.00] ACPI: APIC 0xBF68FE00 68 (v01 INTEL  CRESTLNE 
0604 LOHR 005A)
[0.00] ACPI: HPET 0xBF68FE68 38 (v01 INTEL  CRESTLNE 
0604 LOHR 005A)
[0.00] ACPI: MCFG 0xBF68FEA0 3C (v01 INTEL  CRESTLNE 
0604 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: Enable dynamic debug for DRM_[DEV]_DEBUG*

[Patchwork]

== Series Details ==

Series: drm: Enable dynamic debug for DRM_[DEV]_DEBUG*
URL   : https://patchwork.freedesktop.org/series/16235/
State : success

== Summary ==

Series 16235v1 drm: Enable dynamic debug for DRM_[DEV]_DEBUG*
https://patchwork.freedesktop.org/api/1.0/series/16235/revisions/1/mbox/


fi-bdw-5557u total:245  pass:226  dwarn:0   dfail:0   fail:4   skip:15 
fi-bsw-n3050 total:245  pass:203  dwarn:0   dfail:0   fail:2   skip:40 
fi-byt-j1900 total:245  pass:214  dwarn:0   dfail:0   fail:3   skip:28 
fi-byt-n2820 total:245  pass:210  dwarn:0   dfail:0   fail:3   skip:32 
fi-hsw-4770  total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20 
fi-hsw-4770r total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20 
fi-ilk-650   total:245  pass:189  dwarn:0   dfail:0   fail:3   skip:53 
fi-ivb-3520m total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-ivb-3770  total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-kbl-7500u total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-skl-6260u total:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14 
fi-skl-6700hqtotal:245  pass:220  dwarn:0   dfail:0   fail:4   skip:21 
fi-skl-6700k total:245  pass:219  dwarn:1   dfail:0   fail:4   skip:21 
fi-skl-6770hqtotal:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14 
fi-snb-2520m total:245  pass:210  dwarn:0   dfail:0   fail:3   skip:32 
fi-snb-2600  total:245  pass:209  dwarn:0   dfail:0   fail:3   skip:33 

15f4397c9b50b0212dcb99fb2b5b8a3867133e81 drm-tip: 2016y-12m-01d-13h-26m-26s UTC 
integration manifest
ca6f4f6 drm: Enable dynamic debug for DRM_[DEV]_DEBUG*

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3164/
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[Intel-gfx] ✓ Fi.CI.BAT: success for GEN-9 Arbitrated Bandwidth WM WA's & IPC (rev3)

[Patchwork]

== Series Details ==

Series: GEN-9 Arbitrated Bandwidth WM WA's & IPC (rev3)
URL   : https://patchwork.freedesktop.org/series/15562/
State : success

== Summary ==

Series 15562v3 GEN-9 Arbitrated Bandwidth WM WA's & IPC
https://patchwork.freedesktop.org/api/1.0/series/15562/revisions/3/mbox/


fi-bdw-5557u total:245  pass:226  dwarn:0   dfail:0   fail:4   skip:15 
fi-bsw-n3050 total:245  pass:203  dwarn:0   dfail:0   fail:2   skip:40 
fi-bxt-t5700 total:245  pass:213  dwarn:0   dfail:0   fail:4   skip:28 
fi-byt-j1900 total:245  pass:214  dwarn:0   dfail:0   fail:3   skip:28 
fi-byt-n2820 total:245  pass:210  dwarn:0   dfail:0   fail:3   skip:32 
fi-hsw-4770  total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20 
fi-hsw-4770r total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20 
fi-ilk-650   total:245  pass:189  dwarn:0   dfail:0   fail:3   skip:53 
fi-ivb-3520m total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-ivb-3770  total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-kbl-7500u total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-skl-6260u total:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14 
fi-skl-6700hqtotal:245  pass:220  dwarn:0   dfail:0   fail:4   skip:21 
fi-skl-6700k total:245  pass:219  dwarn:1   dfail:0   fail:4   skip:21 
fi-skl-6770hqtotal:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14 
fi-snb-2520m total:245  pass:210  dwarn:0   dfail:0   fail:3   skip:32 
fi-snb-2600  total:245  pass:209  dwarn:0   dfail:0   fail:3   skip:33 

15f4397c9b50b0212dcb99fb2b5b8a3867133e81 drm-tip: 2016y-12m-01d-13h-26m-26s UTC 
integration manifest
b0ac9a9 drm/i915/gen9: WM memory bandwidth related workaround
f84d26c drm/i915: Decode system memory bandwidth
338d933 drm/i915: Add intel_atomic_get_existing_crtc_state function
2b11985b drm/i915/skl+: change WM calc to fixed point 16.16
8e23bea drm/i915/bxt: Enable IPC support
fcc35ec drm/i915/kbl: IPC workaround for kabylake
31150d7 drm/i915/bxt: IPC WA for Broxton
c11e0c0 drm/i915/skl: Add variables to check x_tile and y_tile

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3163/
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Re: [Intel-gfx] [PATCH 02/10] drm/i915: Make GEM object create and create from data take dev_priv

[Chris Wilson]

On Thu, Dec 01, 2016 at 02:16:37PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> Makes all GEM object constructors consistent.
> 
> v2: Fix compilation in GVT code.
> 
> Signed-off-by: Tvrtko Ursulin 
> Reviewed-by: Chris Wilson  (v1)
> Reviewed-by: Joonas Lahtinen  (v1)

Still lgtm to me.
-Chris

-- 
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Re: [Intel-gfx] [PATCH 05/10] drm/i915: dev_priv cleanup in bridge/bar/mmio init code

[Chris Wilson]

On Thu, Dec 01, 2016 at 02:16:40PM +, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin 
> 
> dev_priv is more appropriate for these so converting saves
> some lines of source.
> 
> v2: Commit message and keep the pdev local variable. (Joonas Lahtinen)
> 
> Signed-off-by: Tvrtko Ursulin 
> Reviewed-by: Chris Wilson  (v1)
> Reviewed-by: Joonas Lahtinen 

Lgtm as well.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for GEM object create and driver init dev_priv cleanups (rev2)

[Tvrtko Ursulin]

On 01/12/2016 14:45, Patchwork wrote:

== Series Details ==

Series: GEM object create and driver init dev_priv cleanups (rev2)
URL   : https://patchwork.freedesktop.org/series/16162/
State : warning

== Summary ==

Series 16162v2 GEM object create and driver init dev_priv cleanups
https://patchwork.freedesktop.org/api/1.0/series/16162/revisions/2/mbox/

Test kms_pipe_crc_basic:
Subgroup bad-nb-words-1:
pass   -> DMESG-WARN (fi-ivb-3770)


Invalid EDID checksum is back: 
https://bugs.freedesktop.org/show_bug.cgi?id=98228




fi-bdw-5557u total:245  pass:226  dwarn:0   dfail:0   fail:4   skip:15
fi-bsw-n3050 total:245  pass:203  dwarn:0   dfail:0   fail:2   skip:40
fi-bxt-t5700 total:245  pass:213  dwarn:0   dfail:0   fail:4   skip:28
fi-byt-j1900 total:245  pass:214  dwarn:0   dfail:0   fail:3   skip:28
fi-byt-n2820 total:245  pass:210  dwarn:0   dfail:0   fail:3   skip:32
fi-hsw-4770  total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20
fi-hsw-4770r total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20
fi-ilk-650   total:245  pass:189  dwarn:0   dfail:0   fail:3   skip:53
fi-ivb-3520m total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22
fi-ivb-3770  total:245  pass:218  dwarn:1   dfail:0   fail:4   skip:22
fi-kbl-7500u total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22
fi-skl-6260u total:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14
fi-skl-6700hqtotal:245  pass:220  dwarn:0   dfail:0   fail:4   skip:21
fi-skl-6700k total:245  pass:219  dwarn:1   dfail:0   fail:4   skip:21
fi-skl-6770hqtotal:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14
fi-snb-2600  total:245  pass:209  dwarn:0   dfail:0   fail:3   skip:33

15f4397c9b50b0212dcb99fb2b5b8a3867133e81 drm-tip: 2016y-12m-01d-13h-26m-26s UTC 
integration manifest
a6838f4 drm/i915: Make intel_pm_setup take dev_priv
f2ef943 drm/i915: Make i915_save/restore_state and intel_i2c_reset take dev_priv
065196e drm/i915: Make i915_destroy_error_state take dev_priv
5e5a2ec drm/i915: Make gmbus setup take dev_priv
81ddb80 drm/i915: Unexport VGA switcheroo functions
b8756a6 drm/i915: dev_priv cleanup in bridge/bar/mmio init code
e74be3e drm/i915: More GEM init dev_priv cleanup
3f48e34 drm/i915: Make various init functions take dev_priv
c6faec2 drm/i915: Make GEM object create and create from data take dev_priv
b75f2e6 drm/i915: Make GEM object alloc/free and stolen created take dev_priv


Merged to dinq. Thanks for the review! (And for spotting all the places 
where it is needed.) :)


Regards,

Tvrtko
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[Intel-gfx] [PATCH] drm/i915/perf: use DRM_DEBUG for userspace issues

[Robert Bragg]

Avoid using DRM_ERROR for conditions userspace can trigger with a bad
config when opening a stream or from not reading data in a timely
fashion (whereby the OA buffer fills up). These conditions are tested
by i-g-t which treats error messages as failures if using the test
runner. This wasn't an issue while the i915-perf igt tests were being
run in isolation.

One message relating to seeing a spurious zeroed report was changed to
use DRM_NOTE instead of DRM_ERROR. Ideally this warning shouldn't be
seen, but it's not a serious problem if it is. Considering that the
tail margin mechanism is only a heuristic it's possible we might see
this from time to time.

Signed-off-by: Robert Bragg 

fix i915_perf dbg messages
---
 drivers/gpu/drm/i915/i915_perf.c | 42 
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 9551282..5705005 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -474,7 +474,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream 
*stream,
 * copying it to userspace...
 */
if (report32[0] == 0) {
-   DRM_ERROR("Skipping spurious, invalid OA report\n");
+   DRM_NOTE("Skipping spurious, invalid OA report\n");
continue;
}
 
@@ -551,7 +551,7 @@ static int gen7_oa_read(struct i915_perf_stream *stream,
if (ret)
return ret;
 
-   DRM_ERROR("OA buffer overflow: force restart\n");
+   DRM_DEBUG("OA buffer overflow: force restart\n");
 
dev_priv->perf.oa.ops.oa_disable(dev_priv);
dev_priv->perf.oa.ops.oa_enable(dev_priv);
@@ -1000,17 +1000,17 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 * IDs
 */
if (!dev_priv->perf.metrics_kobj) {
-   DRM_ERROR("OA metrics weren't advertised via sysfs\n");
+   DRM_DEBUG("OA metrics weren't advertised via sysfs\n");
return -EINVAL;
}
 
if (!(props->sample_flags & SAMPLE_OA_REPORT)) {
-   DRM_ERROR("Only OA report sampling supported\n");
+   DRM_DEBUG("Only OA report sampling supported\n");
return -EINVAL;
}
 
if (!dev_priv->perf.oa.ops.init_oa_buffer) {
-   DRM_ERROR("OA unit not supported\n");
+   DRM_DEBUG("OA unit not supported\n");
return -ENODEV;
}
 
@@ -1019,17 +1019,17 @@ static int i915_oa_stream_init(struct i915_perf_stream 
*stream,
 * we currently only allow exclusive access
 */
if (dev_priv->perf.oa.exclusive_stream) {
-   DRM_ERROR("OA unit already in use\n");
+   DRM_DEBUG("OA unit already in use\n");
return -EBUSY;
}
 
if (!props->metrics_set) {
-   DRM_ERROR("OA metric set not specified\n");
+   DRM_DEBUG("OA metric set not specified\n");
return -EINVAL;
}
 
if (!props->oa_format) {
-   DRM_ERROR("OA report format not specified\n");
+   DRM_DEBUG("OA report format not specified\n");
return -EINVAL;
}
 
@@ -1384,7 +1384,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private 
*dev_priv,
if (IS_ERR(specific_ctx)) {
ret = PTR_ERR(specific_ctx);
if (ret != -EINTR)
-   DRM_ERROR("Failed to look up context with ID %u 
for opening perf stream\n",
+   DRM_DEBUG("Failed to look up context with ID %u 
for opening perf stream\n",
  ctx_handle);
goto err;
}
@@ -1397,7 +1397,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private 
*dev_priv,
 */
if (!specific_ctx &&
i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
-   DRM_ERROR("Insufficient privileges to open system-wide i915 
perf stream\n");
+   DRM_DEBUG("Insufficient privileges to open system-wide i915 
perf stream\n");
ret = -EACCES;
goto err_ctx;
}
@@ -1476,7 +1476,7 @@ static int read_properties_unlocked(struct 
drm_i915_private *dev_priv,
memset(props, 0, sizeof(struct perf_open_properties));
 
if (!n_props) {
-   DRM_ERROR("No i915 perf properties given");
+   DRM_DEBUG("No i915 perf properties given\n");
return -EINVAL;
}
 
@@ -1487,7 +1487,7 @@ static int read_properties_unlocked(struct 
drm_i915_private *dev_priv,
 * from userspace.
 */
if (n_props >= DRM_I915_PERF_PROP_MAX) {
- 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/perf: use DRM_DEBUG for userspace issues

[Patchwork]

== Series Details ==

Series: drm/i915/perf: use DRM_DEBUG for userspace issues
URL   : https://patchwork.freedesktop.org/series/16236/
State : success

== Summary ==

Series 16236v1 drm/i915/perf: use DRM_DEBUG for userspace issues
https://patchwork.freedesktop.org/api/1.0/series/16236/revisions/1/mbox/


fi-bdw-5557u total:245  pass:226  dwarn:0   dfail:0   fail:4   skip:15 
fi-bsw-n3050 total:245  pass:203  dwarn:0   dfail:0   fail:2   skip:40 
fi-bxt-t5700 total:245  pass:213  dwarn:0   dfail:0   fail:4   skip:28 
fi-byt-j1900 total:245  pass:214  dwarn:0   dfail:0   fail:3   skip:28 
fi-byt-n2820 total:245  pass:210  dwarn:0   dfail:0   fail:3   skip:32 
fi-hsw-4770  total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20 
fi-hsw-4770r total:245  pass:221  dwarn:0   dfail:0   fail:4   skip:20 
fi-ilk-650   total:245  pass:189  dwarn:0   dfail:0   fail:3   skip:53 
fi-ivb-3520m total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-ivb-3770  total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-kbl-7500u total:245  pass:219  dwarn:0   dfail:0   fail:4   skip:22 
fi-skl-6260u total:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14 
fi-skl-6700hqtotal:245  pass:220  dwarn:0   dfail:0   fail:4   skip:21 
fi-skl-6700k total:245  pass:219  dwarn:1   dfail:0   fail:4   skip:21 
fi-skl-6770hqtotal:245  pass:227  dwarn:0   dfail:0   fail:4   skip:14 
fi-snb-2520m total:245  pass:210  dwarn:0   dfail:0   fail:3   skip:32 
fi-snb-2600  total:245  pass:209  dwarn:0   dfail:0   fail:3   skip:33 

15f4397c9b50b0212dcb99fb2b5b8a3867133e81 drm-tip: 2016y-12m-01d-13h-26m-26s UTC 
integration manifest
e0bdfdc drm/i915/perf: use DRM_DEBUG for userspace issues

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3165/
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[Intel-gfx] [RFC] drm: Enable dynamic debug for DRM_[DEV]_DEBUG*

[Robert Bragg]

I'm currently considering the use of DRM_ERROR in i915 perf for steam
config validation errors (i.e. userspace misconfigurations) that should
be changed so that i-g-t tests aren't treated as failures when
triggering these.

I initially proposed changing these to DRM_INFO messages and
intentionally wanted to avoid DRM_DEBUG since in my limited experience
DRM_DEBUG messages aren't practical to work with.

I thought I'd see if DRM_DEBUG could be updated to have a bit more fine
grained control in case that might help sway my view.

Tbh, although I think something like this could be nice to have, I'm
still not really convinced that debug messages are a great fit for
helping userspace developers hitting EINVAL errors. Such developers
don't need to be drm/i915 developers and imho shouldn't be expected to
know of the existence of optional debug messages, and if you don't know
of there existence then the control interface isn't important and they
won't help anyone.

--- >8 --- (git am --scissors)

Dynamic debug messages (ref: Documentation/dynamic-debug-howto.txt)
allow fine grained control over which debug messages are enabled with
runtime control through /sysfs/kernel/debug/dynamic_debug/control

This provides more control than the current drm.drm_debug parameter
which for some use cases is impractical to use given how chatty
some drm debug categories are.

For example all debug messages in i915_drm.c can be enabled with:
echo "file i915_perf.c +p" > dynamic_debug/control

This aims to maintain compatibility with controlling debug messages
using the drm_debug parameter. The new dynamic debug macros are called
by default but conditionally calling [dev_]printk if the category flag
is set (side stepping the dynamic debug condition in that case)

This removes the drm_[dev_]printk wrappers considering that the dynamic
debug macros are only useful if they can track the __FILE__, __func__
and __LINE__ where they are called. The wrapper didn't seem necessary in
the DRM_UT_NONE case with no category flag.

The output format should be compatible, unless the _DEV macros are
passed a NULL dev pointer considering how the core.c dev_printk
implementation adds "(NULL device *)" to the message in that case while
the drm wrapper would fallback to a plain printk in this case.
Previously some of non-dev drm debug macros were defined in terms of
passing NULL to a dev version but that's avoided now due to this
difference.

I haven't so far looked to see what affect these have on linked object
sizes.

Signed-off-by: Robert Bragg 
Cc: Chris Wilson 
---
 drivers/gpu/drm/drm_drv.c |  47 -
 include/drm/drmP.h| 168 +-
 2 files changed, 108 insertions(+), 107 deletions(-)

diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index cc6c253..5b2dbcd 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -65,53 +65,6 @@ static struct idr drm_minors_idr;
 
 static struct dentry *drm_debugfs_root;
 
-#define DRM_PRINTK_FMT "[" DRM_NAME ":%s]%s %pV"
-
-void drm_dev_printk(const struct device *dev, const char *level,
-   unsigned int category, const char *function_name,
-   const char *prefix, const char *format, ...)
-{
-   struct va_format vaf;
-   va_list args;
-
-   if (category != DRM_UT_NONE && !(drm_debug & category))
-   return;
-
-   va_start(args, format);
-   vaf.fmt = format;
-   vaf.va = 
-
-   if (dev)
-   dev_printk(level, dev, DRM_PRINTK_FMT, function_name, prefix,
-  );
-   else
-   printk("%s" DRM_PRINTK_FMT, level, function_name, prefix, );
-
-   va_end(args);
-}
-EXPORT_SYMBOL(drm_dev_printk);
-
-void drm_printk(const char *level, unsigned int category,
-   const char *format, ...)
-{
-   struct va_format vaf;
-   va_list args;
-
-   if (category != DRM_UT_NONE && !(drm_debug & category))
-   return;
-
-   va_start(args, format);
-   vaf.fmt = format;
-   vaf.va = 
-
-   printk("%s" "[" DRM_NAME ":%ps]%s %pV",
-  level, __builtin_return_address(0),
-  strcmp(level, KERN_ERR) == 0 ? " *ERROR*" : "", );
-
-   va_end(args);
-}
-EXPORT_SYMBOL(drm_printk);
-
 /*
  * DRM Minors
  * A DRM device can provide several char-dev interfaces on the DRM-Major. Each
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index b352a7b..d61d937 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -58,6 +58,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -129,7 +130,6 @@ struct dma_buf_attachment;
  * run-time by echoing the debug value in its sysfs node:
  *   # echo 0xf > /sys/module/drm/parameters/debug
  */
-#define DRM_UT_NONE0x00
 #define DRM_UT_CORE0x01
 #define DRM_UT_DRIVER  0x02
 #define DRM_UT_KMS 0x04
@@ -146,25 

Re: [Intel-gfx] [PATCH 1/3] drm: Add a new connector atomic property for link status

[Manasi Navare]

Sean, could you please review this patch, I have tried to address
all the comments from you.

Regards
Manasi

On Tue, Nov 29, 2016 at 11:30:31PM -0800, Manasi Navare wrote:
> At the time userspace does setcrtc, we've already promised the mode
> would work. The promise is based on the theoretical capabilities of
> the link, but it's possible we can't reach this in practice. The DP
> spec describes how the link should be reduced, but we can't reduce
> the link below the requirements of the mode. Black screen follows.
> 
> One idea would be to have setcrtc return a failure. However, it
> already should not fail as the atomic checks have passed. It would
> also conflict with the idea of making setcrtc asynchronous in the
> future, returning before the actual mode setting and link training.
> 
> Another idea is to train the link "upfront" at hotplug time, before
> pruning the mode list, so that we can do the pruning based on
> practical not theoretical capabilities. However, the changes for link
> training are pretty drastic, all for the sake of error handling and
> DP compliance, when the most common happy day scenario is the current
> approach of link training at mode setting time, using the optimal
> parameters for the mode. It is also not certain all hardware could do
> this without the pipe on; not even all our hardware can do this. Some
> of this can be solved, but not trivially.
> 
> Both of the above ideas also fail to address link degradation *during*
> operation.
> 
> The solution is to add a new "link-status" connector property in order
> to address link training failure in a way that:
> a) changes the current happy day scenario as little as possible, to
> avoid regressions, b) can be implemented the same way by all drm
> drivers, c) is still opt-in for the drivers and userspace, and opting
> out doesn't regress the user experience, d) doesn't prevent drivers
> from implementing better or alternate approaches, possibly without
> userspace involvement. And, of course, handles all the issues presented.
> In the usual happy day scenario, this is always "good". If something
> fails during or after a mode set, the kernel driver can set the link
> status to "bad" and issue a hotplug uevent for userspace to have it
> re-check the valid modes through GET_CONNECTOR IOCTL, and try modeset
> again. If the theoretical capabilities of the link can't be reached,
> the mode list is trimmed based on that.
> 
> v4:
> * Add comments in kernel-doc format (Daniel Vetter)
> * Update the kernel-doc for link-status (Sean Paul)
> v3:
> * Fixed a build error (Jani Saarinen)
> v2:
> * Removed connector->link_status (Daniel Vetter)
> * Set connector->state->link_status in 
> drm_mode_connector_set_link_status_property
> (Daniel Vetter)
> * Set the connector_changed flag to true if connector->state->link_status 
> changed.
> * Reset link_status to GOOD in update_output_state (Daniel Vetter)
> * Never allow userspace to set link status from Good To Bad (Daniel Vetter)
> 
> Acked-by: Tony Cheng 
> Acked-by: Harry Wentland 
> Cc: Jani Nikula 
> Cc: Daniel Vetter 
> Cc: Ville Syrjala 
> Cc: Chris Wilson 
> Cc: Sean Paul 
> Signed-off-by: Manasi Navare 
> ---
>  drivers/gpu/drm/drm_atomic.c| 10 +++
>  drivers/gpu/drm/drm_atomic_helper.c |  8 ++
>  drivers/gpu/drm/drm_connector.c | 54 
> -
>  include/drm/drm_connector.h | 19 +
>  include/drm/drm_mode_config.h   |  5 
>  include/uapi/drm/drm_mode.h |  4 +++
>  6 files changed, 99 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
> index 89737e4..990f013 100644
> --- a/drivers/gpu/drm/drm_atomic.c
> +++ b/drivers/gpu/drm/drm_atomic.c
> @@ -1087,6 +1087,14 @@ int drm_atomic_connector_set_property(struct 
> drm_connector *connector,
>* now?) atomic writes to DPMS property:
>*/
>   return -EINVAL;
> + } else if (property == config->link_status_property) {
> + /* Never downgrade from GOOD to BAD on userspace's request here,
> +  * only hw issues can do that.
> +  */
> + if (state->link_status == DRM_LINK_STATUS_GOOD)
> + return 0;
> + state->link_status = val;
> + return 0;
>   } else if (connector->funcs->atomic_set_property) {
>   return connector->funcs->atomic_set_property(connector,
>   state, property, val);
> @@ -1135,6 +1143,8 @@ static void drm_atomic_connector_print_state(struct 
> drm_printer *p,
>   *val = (state->crtc) ? state->crtc->base.id : 0;
>   } else if (property == config->dpms_property) {
>   *val = 

Re: [Intel-gfx] [PATCH 1/3] drm: Add a new connector atomic property for link status

[Sean Paul]

On Thu, Dec 1, 2016 at 1:58 PM, Manasi Navare  wrote:
> Sean, could you please review this patch, I have tried to address
> all the comments from you.
>

Comments look good to me.

Reviewed-by: Sean Paul 

Sean

> Regards
> Manasi
>
> On Tue, Nov 29, 2016 at 11:30:31PM -0800, Manasi Navare wrote:
>> At the time userspace does setcrtc, we've already promised the mode
>> would work. The promise is based on the theoretical capabilities of
>> the link, but it's possible we can't reach this in practice. The DP
>> spec describes how the link should be reduced, but we can't reduce
>> the link below the requirements of the mode. Black screen follows.
>>
>> One idea would be to have setcrtc return a failure. However, it
>> already should not fail as the atomic checks have passed. It would
>> also conflict with the idea of making setcrtc asynchronous in the
>> future, returning before the actual mode setting and link training.
>>
>> Another idea is to train the link "upfront" at hotplug time, before
>> pruning the mode list, so that we can do the pruning based on
>> practical not theoretical capabilities. However, the changes for link
>> training are pretty drastic, all for the sake of error handling and
>> DP compliance, when the most common happy day scenario is the current
>> approach of link training at mode setting time, using the optimal
>> parameters for the mode. It is also not certain all hardware could do
>> this without the pipe on; not even all our hardware can do this. Some
>> of this can be solved, but not trivially.
>>
>> Both of the above ideas also fail to address link degradation *during*
>> operation.
>>
>> The solution is to add a new "link-status" connector property in order
>> to address link training failure in a way that:
>> a) changes the current happy day scenario as little as possible, to
>> avoid regressions, b) can be implemented the same way by all drm
>> drivers, c) is still opt-in for the drivers and userspace, and opting
>> out doesn't regress the user experience, d) doesn't prevent drivers
>> from implementing better or alternate approaches, possibly without
>> userspace involvement. And, of course, handles all the issues presented.
>> In the usual happy day scenario, this is always "good". If something
>> fails during or after a mode set, the kernel driver can set the link
>> status to "bad" and issue a hotplug uevent for userspace to have it
>> re-check the valid modes through GET_CONNECTOR IOCTL, and try modeset
>> again. If the theoretical capabilities of the link can't be reached,
>> the mode list is trimmed based on that.
>>
>> v4:
>> * Add comments in kernel-doc format (Daniel Vetter)
>> * Update the kernel-doc for link-status (Sean Paul)
>> v3:
>> * Fixed a build error (Jani Saarinen)
>> v2:
>> * Removed connector->link_status (Daniel Vetter)
>> * Set connector->state->link_status in 
>> drm_mode_connector_set_link_status_property
>> (Daniel Vetter)
>> * Set the connector_changed flag to true if connector->state->link_status 
>> changed.
>> * Reset link_status to GOOD in update_output_state (Daniel Vetter)
>> * Never allow userspace to set link status from Good To Bad (Daniel Vetter)
>>
>> Acked-by: Tony Cheng 
>> Acked-by: Harry Wentland 
>> Cc: Jani Nikula 
>> Cc: Daniel Vetter 
>> Cc: Ville Syrjala 
>> Cc: Chris Wilson 
>> Cc: Sean Paul 
>> Signed-off-by: Manasi Navare 
>> ---
>>  drivers/gpu/drm/drm_atomic.c| 10 +++
>>  drivers/gpu/drm/drm_atomic_helper.c |  8 ++
>>  drivers/gpu/drm/drm_connector.c | 54 
>> -
>>  include/drm/drm_connector.h | 19 +
>>  include/drm/drm_mode_config.h   |  5 
>>  include/uapi/drm/drm_mode.h |  4 +++
>>  6 files changed, 99 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
>> index 89737e4..990f013 100644
>> --- a/drivers/gpu/drm/drm_atomic.c
>> +++ b/drivers/gpu/drm/drm_atomic.c
>> @@ -1087,6 +1087,14 @@ int drm_atomic_connector_set_property(struct 
>> drm_connector *connector,
>>* now?) atomic writes to DPMS property:
>>*/
>>   return -EINVAL;
>> + } else if (property == config->link_status_property) {
>> + /* Never downgrade from GOOD to BAD on userspace's request 
>> here,
>> +  * only hw issues can do that.
>> +  */
>> + if (state->link_status == DRM_LINK_STATUS_GOOD)
>> + return 0;
>> + state->link_status = val;
>> + return 0;
>>   } else if (connector->funcs->atomic_set_property) {
>>   return connector->funcs->atomic_set_property(connector,
>>   state, 

[Intel-gfx] [drm-intel:drm-intel-next-queued 3/10] htmldocs: drivers/gpu/drm/i915/intel_guc_loader.c:779: warning: No description found for parameter 'dev_priv'

[kbuild test robot]

tree:   git://anongit.freedesktop.org/drm-intel drm-intel-next-queued
head:   192aa18142b28fdcb63b12984e02466ced382a54
commit: bf9e8429ab9747f584e692bad52a7a9f1787a4da [3/10] drm/i915: Make various 
init functions take dev_priv
reproduce: make htmldocs

All warnings (new ones prefixed by >>):

   make[3]: warning: jobserver unavailable: using -j1.  Add '+' to parent make 
rule.
   include/linux/init.h:1: warning: no structured comments found
   include/linux/workqueue.h:392: warning: No description found for parameter 
'...'
   include/linux/workqueue.h:392: warning: Excess function parameter 'args' 
description in 'alloc_workqueue'
   include/linux/workqueue.h:413: warning: No description found for parameter 
'...'
   include/linux/workqueue.h:413: warning: Excess function parameter 'args' 
description in 'alloc_ordered_workqueue'
   include/linux/kthread.h:26: warning: No description found for parameter '...'
   kernel/sys.c:1: warning: no structured comments found
   drivers/dma-buf/seqno-fence.c:1: warning: no structured comments found
   include/sound/core.h:324: warning: No description found for parameter '...'
   include/sound/core.h:335: warning: No description found for parameter '...'
   include/sound/core.h:388: warning: No description found for parameter '...'
   include/drm/drm_drv.h:295: warning: Incorrect use of kernel-doc format:  
 * Hook for allocating the GEM object struct, for use by core
   include/drm/drm_drv.h:407: warning: No description found for parameter 'load'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'firstopen'
   include/drm/drm_drv.h:407: warning: No description found for parameter 'open'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'preclose'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'postclose'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'lastclose'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'unload'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'dma_ioctl'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'dma_quiescent'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'context_dtor'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'set_busid'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'irq_handler'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'irq_preinstall'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'irq_postinstall'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'irq_uninstall'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'debugfs_init'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'debugfs_cleanup'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_open_object'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_close_object'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_create_object'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'prime_handle_to_fd'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'prime_fd_to_handle'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_export'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_import'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_pin'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_unpin'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_res_obj'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_get_sg_table'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_import_sg_table'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_vmap'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_vunmap'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_prime_mmap'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'vgaarb_irq'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'gem_vm_ops'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'major'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'minor'
   include/drm/drm_drv.h:407: warning: No description found for parameter 
'patchlevel'
   include/drm/drm_drv.h:407: warning: No description found for parameter 'name'
   include/drm/drm_drv.h:407: warning: No description found for parameter 'desc'
   include/drm/drm_drv.h:407: warning: No 

[Intel-gfx] [PATCH 07/18] drm/i915/dsi: Move intel_dsi_clear_device_ready()

[Hans de Goede]

Move the intel_dsi_clear_device_ready() function to higher up in
intel_dsi.c this pairs it with intel_dsi_device_ready(); and pairs
intel_dsi_*enable* with intel_dsi_*disable without
intel_dsi_clear_device_ready() sitting in the middle of them.

This commit purely moves code around, it does not make any
changes what-so-ever.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 86 
 1 file changed, 43 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index cb15c0a..229 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -445,6 +445,49 @@ static void intel_dsi_device_ready(struct intel_encoder 
*encoder)
bxt_dsi_device_ready(encoder);
 }
 
+static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
+   enum port port;
+
+   DRM_DEBUG_KMS("\n");
+   for_each_dsi_port(port, intel_dsi->ports) {
+   /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
+   i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
+   BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
+   u32 val;
+
+   I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+   ULPS_STATE_ENTER);
+   usleep_range(2000, 2500);
+
+   I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+   ULPS_STATE_EXIT);
+   usleep_range(2000, 2500);
+
+   I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
+   ULPS_STATE_ENTER);
+   usleep_range(2000, 2500);
+
+   /* Wait till Clock lanes are in LP-00 state for MIPI Port A
+* only. MIPI Port C has no similar bit for checking
+*/
+   if (intel_wait_for_register(dev_priv,
+   port_ctrl, AFE_LATCHOUT, 0,
+   30))
+   DRM_ERROR("DSI LP not going Low\n");
+
+   /* Disable MIPI PHY transparent latch */
+   val = I915_READ(port_ctrl);
+   I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
+   usleep_range(1000, 1500);
+
+   I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
+   usleep_range(2000, 2500);
+   }
+}
+
 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 {
struct drm_device *dev = encoder->base.dev;
@@ -601,49 +644,6 @@ static void intel_dsi_pre_disable(struct intel_encoder 
*encoder,
}
 }
 
-static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
-{
-   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
-   enum port port;
-
-   DRM_DEBUG_KMS("\n");
-   for_each_dsi_port(port, intel_dsi->ports) {
-   /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
-   i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ?
-   BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
-   u32 val;
-
-   I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
-   ULPS_STATE_ENTER);
-   usleep_range(2000, 2500);
-
-   I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
-   ULPS_STATE_EXIT);
-   usleep_range(2000, 2500);
-
-   I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
-   ULPS_STATE_ENTER);
-   usleep_range(2000, 2500);
-
-   /* Wait till Clock lanes are in LP-00 state for MIPI Port A
-* only. MIPI Port C has no similar bit for checking
-*/
-   if (intel_wait_for_register(dev_priv,
-   port_ctrl, AFE_LATCHOUT, 0,
-   30))
-   DRM_ERROR("DSI LP not going Low\n");
-
-   /* Disable MIPI PHY transparent latch */
-   val = I915_READ(port_ctrl);
-   I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
-   usleep_range(1000, 1500);
-
-   I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
-   usleep_range(2000, 2500);
-   }
-}
-
 static void intel_dsi_post_disable(struct intel_encoder *encoder,
   struct intel_crtc_state *pipe_config,
   struct drm_connector_state *conn_state)
-- 
2.9.3

[Intel-gfx] [PATCH 09/18] drm/i915/dsi: Make intel_dsi_enable/disable directly exec VBT sequences

[Hans de Goede]

The drm_panel_enable/disable and drm_panel_prepare/unprepare calls are
not fine grained enough to abstract all the different steps we need to
take (and VBT sequences we need to exec) properly. So simply remove the
panel _enable/disable and prepare/unprepare callbacks and instead
export intel_dsi_exec_vbt_sequence() from intel_dsi_panel_vbt.c
and call that from intel_dsi_enable/disable().

No functional changes.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c   | 14 +++---
 drivers/gpu/drm/i915/intel_dsi.h   |  3 +++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 43 ++
 3 files changed, 15 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 85b748d..cf761e8 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -656,7 +656,10 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
/* put device in ready state */
intel_dsi_device_ready(encoder);
 
-   drm_panel_prepare(intel_dsi->panel);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 
/* Enable port in pre-enable phase itself because as per hw team
 * recommendation, port should be enabled befor plane & pipe */
@@ -669,7 +672,8 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
dpi_send_cmd(intel_dsi, TURN_ON, false, port);
msleep(100);
 
-   drm_panel_enable(intel_dsi->panel);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 
intel_dsi_port_enable(encoder);
}
@@ -732,7 +736,8 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
 * if disable packets are sent before sending shutdown packet then in
 * some next enable sequence send turn on packet error is observed
 */
-   drm_panel_disable(intel_dsi->panel);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 
intel_dsi_clear_device_ready(encoder);
 
@@ -746,7 +751,8 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
I915_WRITE(DSPCLK_GATE_D, val);
}
 
-   drm_panel_unprepare(intel_dsi->panel);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 
msleep(intel_dsi->panel_off_delay);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index d567823..5486491 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -132,6 +132,9 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct 
drm_encoder *encoder)
 
 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
 
+void intel_dsi_exec_vbt_sequence(struct intel_dsi *intel_dsi,
+enum mipi_seq seq_id);
+
 bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
 int intel_compute_dsi_pll(struct intel_encoder *encoder,
  struct intel_crtc_state *config);
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index b5a02c6..f71f913 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -400,10 +400,9 @@ static const char *sequence_name(enum mipi_seq seq_id)
return "(unknown)";
 }
 
-static void generic_exec_sequence(struct drm_panel *panel, enum mipi_seq 
seq_id)
+void intel_dsi_exec_vbt_sequence(struct intel_dsi *intel_dsi,
+enum mipi_seq seq_id)
 {
-   struct vbt_panel *vbt_panel = to_vbt_panel(panel);
-   struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
const u8 *data;
fn_mipi_elem_exec mipi_elem_exec;
@@ -467,40 +466,6 @@ static void generic_exec_sequence(struct drm_panel *panel, 
enum mipi_seq seq_id)
}
 }
 
-static int vbt_panel_prepare(struct drm_panel *panel)
-{
-   generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
-   generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
-   generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
-   generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
-
-   return 0;
-}
-
-static int vbt_panel_unprepare(struct drm_panel *panel)
-{
-   generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
-   generic_exec_sequence(panel, MIPI_SEQ_POWER_OFF);
-
-   return 0;

[Intel-gfx] [PATCH 04/18] drm/i915/dsi: Merge intel_dsi_disable/enable into their respective callers

[Hans de Goede]

intel_dsi_disable/enable only have one caller, merge them into their
respective callers.

Change msleep(2) into usleep_range(2000, 5000) to make checkpatch happy,
otherwise no funtional changes.

The main advantage of this change is that it makes it easier to
follow all the steps of the panel enable / disable sequence when
reading the code.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 109 ---
 1 file changed, 45 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 587ba07..b33381a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -508,32 +508,6 @@ static void intel_dsi_port_disable(struct intel_encoder 
*encoder)
}
 }
 
-static void intel_dsi_enable(struct intel_encoder *encoder)
-{
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
-   enum port port;
-
-   DRM_DEBUG_KMS("\n");
-
-   if (is_cmd_mode(intel_dsi)) {
-   for_each_dsi_port(port, intel_dsi->ports)
-   I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
-   } else {
-   msleep(20); /* XXX */
-   for_each_dsi_port(port, intel_dsi->ports)
-   dpi_send_cmd(intel_dsi, TURN_ON, false, port);
-   msleep(100);
-
-   drm_panel_enable(intel_dsi->panel);
-
-   intel_dsi_port_enable(encoder);
-   }
-
-   intel_panel_enable_backlight(intel_dsi->attached_connector);
-}
-
 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
  struct intel_crtc_state *pipe_config);
 
@@ -543,6 +517,7 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
+   enum port port;
 
DRM_DEBUG_KMS("\n");
 
@@ -577,7 +552,21 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
 
/* Enable port in pre-enable phase itself because as per hw team
 * recommendation, port should be enabled befor plane & pipe */
-   intel_dsi_enable(encoder);
+   if (is_cmd_mode(intel_dsi)) {
+   for_each_dsi_port(port, intel_dsi->ports)
+   I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
+   } else {
+   msleep(20); /* XXX */
+   for_each_dsi_port(port, intel_dsi->ports)
+   dpi_send_cmd(intel_dsi, TURN_ON, false, port);
+   msleep(100);
+
+   drm_panel_enable(intel_dsi->panel);
+
+   intel_dsi_port_enable(encoder);
+   }
+
+   intel_panel_enable_backlight(intel_dsi->attached_connector);
 }
 
 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
@@ -611,42 +600,6 @@ static void intel_dsi_pre_disable(struct intel_encoder 
*encoder,
}
 }
 
-static void intel_dsi_disable(struct intel_encoder *encoder)
-{
-   struct drm_device *dev = encoder->base.dev;
-   struct drm_i915_private *dev_priv = to_i915(dev);
-   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
-   enum port port;
-   u32 temp;
-
-   DRM_DEBUG_KMS("\n");
-
-   if (is_vid_mode(intel_dsi)) {
-   for_each_dsi_port(port, intel_dsi->ports)
-   wait_for_dsi_fifo_empty(intel_dsi, port);
-
-   intel_dsi_port_disable(encoder);
-   msleep(2);
-   }
-
-   for_each_dsi_port(port, intel_dsi->ports) {
-   /* Panel commands can be sent when clock is in LP11 */
-   I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
-
-   intel_dsi_reset_clocks(encoder, port);
-   I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
-
-   temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
-   temp &= ~VID_MODE_FORMAT_MASK;
-   I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
-
-   I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
-   }
-   /* if disable packets are sent before sending shutdown packet then in
-* some next enable sequence send turn on packet error is observed */
-   drm_panel_disable(intel_dsi->panel);
-}
-
 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -698,10 +651,38 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
+   enum port port;
+   u32 temp;
 
DRM_DEBUG_KMS("\n");
 
-   intel_dsi_disable(encoder);
+   if (is_vid_mode(intel_dsi)) {
+   for_each_dsi_port(port, 

[Intel-gfx] [PATCH 05/18] drm/i915/dsi: Add intel_dsi_unprepare() helper

[Hans de Goede]

The enable path has an intel_dsi_prepare() helper which prepares various
registers for the mode-set. Move the function undoing this to a new
intel_dsi_unprepare() helper for better symmetry between the enable and
disable paths. No functional changes.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 38 --
 1 file changed, 24 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index b33381a..967bae9 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -510,6 +510,7 @@ static void intel_dsi_port_disable(struct intel_encoder 
*encoder)
 
 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
  struct intel_crtc_state *pipe_config);
+static void intel_dsi_unprepare(struct intel_encoder *encoder);
 
 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 struct intel_crtc_state *pipe_config,
@@ -652,7 +653,6 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
enum port port;
-   u32 temp;
 
DRM_DEBUG_KMS("\n");
 
@@ -664,19 +664,7 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
usleep_range(2000, 5000);
}
 
-   for_each_dsi_port(port, intel_dsi->ports) {
-   /* Panel commands can be sent when clock is in LP11 */
-   I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
-
-   intel_dsi_reset_clocks(encoder, port);
-   I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
-
-   temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
-   temp &= ~VID_MODE_FORMAT_MASK;
-   I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
-
-   I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
-   }
+   intel_dsi_unprepare(encoder);
 
/*
 * if disable packets are sent before sending shutdown packet then in
@@ -1272,6 +1260,28 @@ static void intel_dsi_prepare(struct intel_encoder 
*intel_encoder,
}
 }
 
+static void intel_dsi_unprepare(struct intel_encoder *encoder)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+   struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
+   enum port port;
+   u32 temp;
+
+   for_each_dsi_port(port, intel_dsi->ports) {
+   /* Panel commands can be sent when clock is in LP11 */
+   I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
+
+   intel_dsi_reset_clocks(encoder, port);
+   I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+
+   temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
+   temp &= ~VID_MODE_FORMAT_MASK;
+   I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp);
+
+   I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
+   }
+}
+
 static enum drm_connector_status
 intel_dsi_detect(struct drm_connector *connector, bool force)
 {
-- 
2.9.3

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Re: [Intel-gfx] linux-next: problems fetching the drm-intel, etc trees

[Stephen Rothwell]

Hi Daniel,

On Thu, 01 Dec 2016 11:02:26 + Daniel Stone  wrote:
>
> On Nov 30 2016, at 10:49 pm, Rob Clark  wrote:  
> 
> > yeah, {cgit,anongit}.fd.o have been having problems all day.. (the ssh
> git urls for folks who have push access work fine).. although it has  
> worked for me a couple times today, given enough time.
> >  
> > (not sure if we have github/etc mirrors somewhere? I do have a github
> clone of mesa which is up to date as of ~10min ago.. I could do the  
> same for other git trees if someone somewhere is stuck)
> 
> Sorry about this, it is quite bad. I think having mirrors for the key DRM
> trees on GitHub is a good idea though, and I can get to setting that up.
> Stephen, you need DRM (airlied), drm-misc, drm-panel, drm-intel, drm-tegra,
> drm-exynos and drm-msm, right?

Well, here are the trees I fetch from *.freedesktop.org:

drm-intel-fixes git://anongit.freedesktop.org/drm-intel for-linux-next-fixes
drm-misc-fixes  git://anongit.freedesktop.org/drm/drm-misc  
for-linux-next-fixes
drm git://people.freedesktop.org/~airlied/linux.git drm-next
drm-panel   git://anongit.freedesktop.org/tegra/linux.git   
drm/panel/for-next
drm-intel   git://anongit.freedesktop.org/drm-intel for-linux-next
drm-tegra   git://anongit.freedesktop.org/tegra/linux.git   
drm/tegra/for-next
drm-miscgit://anongit.freedesktop.org/drm/drm-misc  for-linux-next
drm-msm git://people.freedesktop.org/~robclark/linuxmsm-next

I did not have any trouble with the people.fd.o ones.

> Though, whilst you're at it, I noticed that the drm-misc tree needs updating:
> it's now at git://anongit.freedesktop.org/drm/drm-misc, rather than a branch
> of drm-intel.

I was informed, thanks.

Having mirrors is probably more effort for me than the slight outage
was (I would have to modify my control file for the outage period).  I
can merely use the version of a tree I already have if I can't fetch it
for a day or so.  If you were to have official mirrors, then
git.kernel.org makes more sense for the kernel parts anyway.

-- 
Cheers,
Stephen Rothwell
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[Intel-gfx] [PATCH 11/18] drm/i915/dsi: Move MIPI_SEQ_POWER_ON/OFF calls together with pmic gpio calls

[Hans de Goede]

Now that we are no longer bound to the drm_panel_ callbacks, call
MIPI_SEQ_POWER_ON/OFF at the proper place.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 1f16211..8927c7a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -638,10 +638,10 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
 
intel_dsi_prepare(encoder, pipe_config);
 
-   /* Panel Enable over CRC PMIC */
+   /* Power on, try both CRC pmic gpio and VBT */
if (intel_dsi->gpio_panel)
gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
-
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
msleep(intel_dsi->panel_on_delay);
 
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
@@ -656,7 +656,6 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
/* put device in ready state */
intel_dsi_device_ready(encoder);
 
-   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 
@@ -751,11 +750,10 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
}
 
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
-   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
 
+   /* Power off, try both CRC pmic gpio and VBT */
msleep(intel_dsi->panel_off_delay);
-
-   /* Panel Disable over CRC PMIC */
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
if (intel_dsi->gpio_panel)
gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
 
-- 
2.9.3

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[Intel-gfx] [PATCH 06/18] drm/i915/dsi: Move disable pll call outside of clear_device_ready()

[Hans de Goede]

On enable intel_dsi_enable() directly calls intel_enable_dsi_pll(),
make intel_dsi_disable() also directly call intel_disable_dsi_pll(),
rather then hiding the call in intel_dsi_clear_device_ready(),
no functional changes.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 967bae9..cb15c0a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -642,8 +642,6 @@ static void intel_dsi_clear_device_ready(struct 
intel_encoder *encoder)
I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
usleep_range(2000, 2500);
}
-
-   intel_disable_dsi_pll(encoder);
 }
 
 static void intel_dsi_post_disable(struct intel_encoder *encoder,
@@ -674,6 +672,8 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
 
intel_dsi_clear_device_ready(encoder);
 
+   intel_disable_dsi_pll(encoder);
+
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
u32 val;
 
-- 
2.9.3

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[Intel-gfx] [PATCH 10/18] drm/i915/dsi: Drop bogus MIPI_SEQ_ASSERT_RESET before POWER_ON

[Hans de Goede]

MIPI_SEQ_ASSERT_RESET before POWER_ON is not necessary for 2 reasons:
1) The reset should already be asserted before intel_dsi_pre_enable()
   gets called
2) Most (some?) VBTs will ensure reset was asserted in their
   MIPI_SEQ_DEASSERT_RESET themselves

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index cf761e8..1f16211 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -656,7 +656,6 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
/* put device in ready state */
intel_dsi_device_ready(encoder);
 
-   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
-- 
2.9.3

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[Intel-gfx] [PATCH 12/18] drm/i915/dsi: Group DPOunit clock gate workaround with PLL enable

[Hans de Goede]

Move the DPOunit clock gate workaround to directly after the PLL enable.

The exact location of the workaround does not matter and there are 2
reasons to group it with the PLL enable:

1) This moves it out of the middle of the init sequence from the spec,
   making it easier to follow the init sequence / compare it to the spec

2) It is grouped with the pll disable call in intel_dsi_post_disable,
   so for consistency it should be grouped with the pll enable in
   intel_dsi_pre_enable

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 8927c7a..9e3cf54 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -636,14 +636,6 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
intel_disable_dsi_pll(encoder);
intel_enable_dsi_pll(encoder, pipe_config);
 
-   intel_dsi_prepare(encoder, pipe_config);
-
-   /* Power on, try both CRC pmic gpio and VBT */
-   if (intel_dsi->gpio_panel)
-   gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
-   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
-   msleep(intel_dsi->panel_on_delay);
-
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
u32 val;
 
@@ -653,6 +645,14 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
I915_WRITE(DSPCLK_GATE_D, val);
}
 
+   intel_dsi_prepare(encoder, pipe_config);
+
+   /* Power on, try both CRC pmic gpio and VBT */
+   if (intel_dsi->gpio_panel)
+   gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
+   msleep(intel_dsi->panel_on_delay);
+
/* put device in ready state */
intel_dsi_device_ready(encoder);
 
-- 
2.9.3

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[Intel-gfx] [PATCH 15/18] drm/i915/dsi: Document always using v3 SHUTDOWN / MIPI_SEQ_DISPLAY_OFF order

[Hans de Goede]

According to the spec for v2 VBTs we should call MIPI_SEQ_DISPLAY_OFF
before sending SHUTDOWN, where as for v3 VBTs we should send SHUTDOWN
first.

Since the v2 order has known issues, we use the v3 order everywhere,
add a comment documenting this.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 9b0c9152..7761806 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -708,6 +708,11 @@ static void intel_dsi_pre_disable(struct intel_encoder 
*encoder,
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
intel_panel_disable_backlight(intel_dsi->attached_connector);
 
+   /*
+* XXX: According to the spec we should send SHUTDOWN before
+* MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but testing in the field
+* has shown that we should do this for v2 VBTs too?
+*/
if (is_vid_mode(intel_dsi)) {
/* Send Shutdown command to the panel in LP mode */
for_each_dsi_port(port, intel_dsi->ports)
@@ -739,6 +744,8 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
/*
 * if disable packets are sent before sending shutdown packet then in
 * some next enable sequence send turn on packet error is observed
+* XXX spec specifies SHUTDOWN before MIPI_SEQ_DISPLAY_OFF for
+* v3 VBTs, but not for v2 VBTs?
 */
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 
-- 
2.9.3

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[Intel-gfx] [PATCH 17/18] drm/i915/dsi: Call MIPI_SEQ_TEAR_ON and DISPLAY_ON for cmd-mode (untested)

[Hans de Goede]

According to the spec we should call MIPI_SEQ_TEAR_ON and DISPLAY_ON
on enable for cmd-mode, just like we already call their counterparts
on disable. Note: untested, my panel is a vid-mode panel.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index e3ecb5a..bf956a3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -667,6 +667,8 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
if (is_cmd_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports)
I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
} else {
msleep(20); /* XXX */
for_each_dsi_port(port, intel_dsi->ports)
-- 
2.9.3

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[Intel-gfx] [PATCH 16/18] drm/i915/dsi: Execute MIPI_SEQ_TEAR_OFF from intel_dsi_post_disable

[Hans de Goede]

For v3 VBTs we should call MIPI_SEQ_TEAR_OFF before
MIPI_SEQ_DISPLAY_OFF, for non v3 VBTs this is a nop.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 7761806..e3ecb5a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -747,6 +747,7 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
 * XXX spec specifies SHUTDOWN before MIPI_SEQ_DISPLAY_OFF for
 * v3 VBTs, but not for v2 VBTs?
 */
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 
/* Transition to LP-00 */
-- 
2.9.3

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[Intel-gfx] [PATCH 14/18] drm/i915/dsi: Group MIPI_SEQ_BACKLIGHT_ON/OFF with panel_[en|dis]able_backlight

[Hans de Goede]

Execute the MIPI_SEQ_BACKLIGHT_ON/OFF VBT sequences at the same time as
we call intel_panel_enable_backlight() / intel_panel_disable_backlight().

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 03a7a7c..9b0c9152 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -674,12 +674,13 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
msleep(100);
 
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
-   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 
intel_dsi_port_enable(encoder);
}
 
+   /* Enable backlight, both pwm and VBT */
intel_panel_enable_backlight(intel_dsi->attached_connector);
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
 }
 
 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
@@ -703,6 +704,8 @@ static void intel_dsi_pre_disable(struct intel_encoder 
*encoder,
 
DRM_DEBUG_KMS("\n");
 
+   /* Disable backlight, both VBT and pwm */
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
intel_panel_disable_backlight(intel_dsi->attached_connector);
 
if (is_vid_mode(intel_dsi)) {
@@ -737,7 +740,6 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
 * if disable packets are sent before sending shutdown packet then in
 * some next enable sequence send turn on packet error is observed
 */
-   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 
/* Transition to LP-00 */
-- 
2.9.3

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Re: [Intel-gfx] linux-next: problems fetching the drm-intel, etc trees

[Daniel Stone]

Hi Stephen,

On 1 December 2016 at 20:45, Stephen Rothwell  wrote:
> On Thu, 01 Dec 2016 11:02:26 + Daniel Stone  wrote:
>> Sorry about this, it is quite bad. I think having mirrors for the key DRM
>> trees on GitHub is a good idea though, and I can get to setting that up.
>> Stephen, you need DRM (airlied), drm-misc, drm-panel, drm-intel, drm-tegra,
>> drm-exynos and drm-msm, right?
>
> Well, here are the trees I fetch from *.freedesktop.org:
>
> [...]
>
> I did not have any trouble with the people.fd.o ones.

That's actually interesting, given that they lie on the same host.
Perhaps it means that the locally-mounted ones were fine, and it was
the NFS (cough) mount between git/anongit which took a dive ... thanks
for the datapoint!

Cheers,
Daniel
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[Intel-gfx] [PATCH 13/18] drm/i915/dsi: Execute MIPI_SEQ_DEASSERT_RESET before calling device_ready()

[Hans de Goede]

Execute MIPI_SEQ_DEASSERT_RESET before putting the device in ready
state (LP-11), this is the sequence in which things should be done
according to the spec.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 9e3cf54..03a7a7c 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -653,10 +653,13 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
msleep(intel_dsi->panel_on_delay);
 
-   /* put device in ready state */
+   /* Deassert reset */
+   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
+
+   /* Put device in ready state (LP-11) */
intel_dsi_device_ready(encoder);
 
-   intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
+   /* Send initialization commands in LP mode */
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
 
/* Enable port in pre-enable phase itself because as per hw team
@@ -737,6 +740,7 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
 
+   /* Transition to LP-00 */
intel_dsi_clear_device_ready(encoder);
 
intel_disable_dsi_pll(encoder);
@@ -749,6 +753,7 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
I915_WRITE(DSPCLK_GATE_D, val);
}
 
+   /* Assert reset */
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 
/* Power off, try both CRC pmic gpio and VBT */
-- 
2.9.3

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[Intel-gfx] [PATCH 18/18] drm/i915/dsi: Skip delays for v3 VBTs in vid-mode

[Hans de Goede]

For v3 VBTs in vid-mode the delays are part of the VBT sequences, so
we should not also delay ourselves otherwise we get double delays.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index bf956a3..b60612a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -555,6 +555,17 @@ static void intel_dsi_prepare(struct intel_encoder 
*intel_encoder,
  struct intel_crtc_state *pipe_config);
 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 
+static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
+{
+   struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+
+   /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
+   if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
+   return;
+
+   msleep(msec);
+}
+
 /*
  * Panel enable/disable sequences from the spec:
  *
@@ -651,7 +662,7 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
if (intel_dsi->gpio_panel)
gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
-   msleep(intel_dsi->panel_on_delay);
+   intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
 
/* Deassert reset */
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
@@ -673,7 +684,7 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
msleep(20); /* XXX */
for_each_dsi_port(port, intel_dsi->ports)
dpi_send_cmd(intel_dsi, TURN_ON, false, port);
-   msleep(100);
+   intel_dsi_msleep(intel_dsi, 100);
 
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
 
@@ -769,7 +780,7 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
 
/* Power off, try both CRC pmic gpio and VBT */
-   msleep(intel_dsi->panel_off_delay);
+   intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
if (intel_dsi->gpio_panel)
gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
@@ -778,7 +789,7 @@ static void intel_dsi_post_disable(struct intel_encoder 
*encoder,
 * FIXME As we do with eDP, just make a note of the time here
 * and perform the wait before the next panel power on.
 */
-   msleep(intel_dsi->panel_pwr_cycle_delay);
+   intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
 }
 
 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
-- 
2.9.3

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Re: [Intel-gfx] ✗ Fi.CI.BAT: warning for GEM object create and driver init dev_priv cleanups (rev2)

[Chris Wilson]

On Thu, Dec 01, 2016 at 06:08:25PM +, Tvrtko Ursulin wrote:
> Merged to dinq. Thanks for the review! (And for spotting all the
> places where it is needed.) :)

Oops, better run make htmldocs and catch the important information that
intel_guc_fini() takes dev_priv.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[Intel-gfx] [PATCH 00/18] drm/i915/dsi: Fix / cleanup dsi enable / disable sequences

[Hans de Goede]

Hi All,

So while trying to fix my cherrytrail tablet's screen sometimes not
initializing properly (*) I started working on this series to cleanup /
(minor) refactor the dsi enable / disable code, with as goal to then
change it to match the enable / disable sequences which Ville Syrjälä
recently dug up from within the spec.

The first 2 patches I've send before, but I'm resending them since
the other patches in this series depend on them.

The 3th patch is a (small) functional change, which makes the
patches following it move less code around.

Patches 4 - 9 move some stuff around with as goal to have
intel_dsi_pre_enable() and intel_dsi_pre_disable() +
intel_dsi_post_disable() have the entire (de)init sequence in a
clearly readable one function call per step (more or less)
style, so that the ordering is obvious and we can easily match
the code to the spec

Patches 10 - 18 actually modify the code to match the spec, there are
9 patches here as I've chosen to do one tiny change per patch so that
regressions can be bisected to a commit more specific then a
"change the world" commit.

After this patch-set the dsi enable / disable code is much easier to
read (IMHO), almost fully matches the spec (with the single exception
documented) and still works (for me).

There are still some possible improvements to consider:

1) intel_dsi_pre_enable starts with enabling the pll, but
   intel_dsi_post_disable disables it half-way through the
   sequence, since then it is no longer necessary. From a
   power-management pov this is good, but it is assymetrical

2) intel_dsi_pre_enable calls intel_dsi_prepare before calling
   intel_dsi_device_ready, so intel_dsi_post_disable should
   call intel_dsi_unprepare *after* intel_dsi_clear_device_ready,
   but it calls it *before*. Because of this intel_dsi_unprepare
   itself temporarily clears device-ready and resets it in the end.
   It would be good to move intel_dsi_unprepare to *after*
   intel_dsi_clear_device_ready and drop its toggling of the
   device-ready bit, but I'm not sure if that is safe. Perhaps
   there is a specific reason why this is done this way?

3) While working on this I found the following patch which maybe
   should be merged to the mainline i915 code ?  :
   
https://github.com/01org/ProductionKernelQuilts/blob/master/uefi/cht-m1stable/patches/0002-FOR_UPSTREAM-VPG-drm-i915-Move-port-enable-to-after-.patch

   The date on this patch is from long after the decision to
   move the intel_dsi_enable_port call to intel_dsi_pre_enable,
   so it seems to superseed that decision. Maybe we should move the
   intel_dsi_port_enable call from intel_dsi_pre_enable back
   to intel_dsi_enable[_nop] ?

Regards,

Hans


*) The root cause of which turns out to be something different, but since
I had done most of this work when I found that out, I decided to not throw
away my work and instead finish this series and post it upstream
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[Intel-gfx] [PATCH 01/18] drm/i915/dsi: Fix swapping of MIPI_SEQ_DEASSERT_RESET / MIPI_SEQ_ASSERT_RESET

[Hans de Goede]

Looking at the ADF code from the Android kernel sources for a
cherrytrail tablet I noticed that it is calling the
MIPI_SEQ_ASSERT_RESET sequence from the panel prepare hook.

Until commit b1cb1bd29189 ("drm/i915/dsi: update reset and power sequences
in panel prepare/unprepare hooks") the mainline i915 code was doing the
same. That commits effectively swaps the calling of MIPI_SEQ_ASSERT_RESET /
MIPI_SEQ_DEASSERT_RESET.

Looking at the naming of the sequences that is the right thing to do,
but the problem is, that the old mainline code and the ADF code was
actually calling the right sequence (tested on a cube iwork8 air tablet),
and the swapping of the calling breaks things.

This breakage was likely not noticed in testing because on cherrytrail,
currently chv_exec_gpio ends up disabling the gpio pins rather then
setting them (this is fixed in the next patch in this patch-set).

This commit fixes the swapping by fixing MIPI_SEQ_ASSERT/DEASSERT_RESET's
places in the enum defining them, so that their (new) names match their
actual use.

Fixes: b1cb1bd29189 ("drm/i915/dsi: update reset and power sequences...")
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_bios.h  | 4 ++--
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.h 
b/drivers/gpu/drm/i915/intel_bios.h
index 8405b5a..642a5eb 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -49,11 +49,11 @@ struct edp_power_seq {
 /* MIPI Sequence Block definitions */
 enum mipi_seq {
MIPI_SEQ_END = 0,
-   MIPI_SEQ_ASSERT_RESET,
+   MIPI_SEQ_DEASSERT_RESET,
MIPI_SEQ_INIT_OTP,
MIPI_SEQ_DISPLAY_ON,
MIPI_SEQ_DISPLAY_OFF,
-   MIPI_SEQ_DEASSERT_RESET,
+   MIPI_SEQ_ASSERT_RESET,
MIPI_SEQ_BACKLIGHT_ON,  /* sequence block v2+ */
MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */
MIPI_SEQ_TEAR_ON,   /* sequence block v2+ */
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 0d8ff00..579d2f5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -376,11 +376,11 @@ static const fn_mipi_elem_exec exec_elem[] = {
  */
 
 static const char * const seq_name[] = {
-   [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
+   [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
[MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
[MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
[MIPI_SEQ_DISPLAY_OFF]  = "MIPI_SEQ_DISPLAY_OFF",
-   [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
+   [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
[MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
[MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
[MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
-- 
2.9.3

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[Intel-gfx] [PATCH 02/18] drm/i915/dsi: Fix chv_exec_gpio disabling the GPIOs it is setting

[Hans de Goede]

Set the CHV_GPIO_GPIOEN bit when updating GPIOs from chv_exec_gpio.

Fixes: a0a6d4ffd2ad ("drm/i915/dsi: add support for gpio elements on CHV")
Cc: sta...@vger.kernel.org
Cc: Jani Nikula 
Cc: Ville Syrjälä 
Signed-off-by: Hans de Goede 
Reviewed-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 579d2f5..47cd1b2 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -300,7 +300,8 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv,
mutex_lock(_priv->sb_lock);
vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
vlv_iosf_sb_write(dev_priv, port, cfg0,
- CHV_GPIO_GPIOCFG_GPO | CHV_GPIO_GPIOTXSTATE(value));
+ CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
+ CHV_GPIO_GPIOTXSTATE(value));
mutex_unlock(_priv->sb_lock);
 }
 
-- 
2.9.3

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[Intel-gfx] [PATCH 03/18] drm/i915/dsi: Move calling of wait_for_dsi_fifo_empty to mipi_exec_send_packet

[Hans de Goede]

Instead of calling wait_for_dsi_fifo_empty on all dsi ports after calling
a drm_panel_foo helper which calls VBT sequences, move it to the VBT
mipi_exec_send_packet helper, which is the one VBT instruction which
actually puts data in the fifo.

This results in a nice cleanup making it clearer what all the steps on
intel_dsi_enable / disable are and this also makes the VBT code properly
wait till a command has actually been send before executing the next
steps (typically a delay) in the VBT sequence.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c   | 12 +---
 drivers/gpu/drm/i915/intel_dsi.h   |  2 ++
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  2 ++
 3 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 3bc6213..587ba07 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -80,7 +80,7 @@ enum mipi_dsi_pixel_format 
pixel_format_from_register_bits(u32 fmt)
}
 }
 
-static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port 
port)
+void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
 {
struct drm_encoder *encoder = _dsi->base.base;
struct drm_device *dev = encoder->dev;
@@ -528,9 +528,6 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 
drm_panel_enable(intel_dsi->panel);
 
-   for_each_dsi_port(port, intel_dsi->ports)
-   wait_for_dsi_fifo_empty(intel_dsi, port);
-
intel_dsi_port_enable(encoder);
}
 
@@ -546,7 +543,6 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
 {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(>base);
-   enum port port;
 
DRM_DEBUG_KMS("\n");
 
@@ -579,9 +575,6 @@ static void intel_dsi_pre_enable(struct intel_encoder 
*encoder,
 
drm_panel_prepare(intel_dsi->panel);
 
-   for_each_dsi_port(port, intel_dsi->ports)
-   wait_for_dsi_fifo_empty(intel_dsi, port);
-
/* Enable port in pre-enable phase itself because as per hw team
 * recommendation, port should be enabled befor plane & pipe */
intel_dsi_enable(encoder);
@@ -652,9 +645,6 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
/* if disable packets are sent before sending shutdown packet then in
 * some next enable sequence send turn on packet error is observed */
drm_panel_disable(intel_dsi->panel);
-
-   for_each_dsi_port(port, intel_dsi->ports)
-   wait_for_dsi_fifo_empty(intel_dsi, port);
 }
 
 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 5967ea6..d567823 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -130,6 +130,8 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct 
drm_encoder *encoder)
return container_of(encoder, struct intel_dsi, base.base);
 }
 
+void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
+
 bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
 int intel_compute_dsi_pll(struct intel_encoder *encoder,
  struct intel_crtc_state *config);
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c 
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 47cd1b2..b5a02c6 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -191,6 +191,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi 
*intel_dsi,
break;
}
 
+   wait_for_dsi_fifo_empty(intel_dsi, port);
+
 out:
data += len;
 
-- 
2.9.3

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[Intel-gfx] [PATCH 08/18] drm/i915/dsi: Document the panel enable / disable sequences from the spec

[Hans de Goede]

Document the DSI panel enable / disable sequences from the spec,
for easy comparison between the code and the spec.

Signed-off-by: Hans de Goede 
---
 drivers/gpu/drm/i915/intel_dsi.c | 64 
 1 file changed, 64 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 229..85b748d 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -555,6 +555,70 @@ static void intel_dsi_prepare(struct intel_encoder 
*intel_encoder,
  struct intel_crtc_state *pipe_config);
 static void intel_dsi_unprepare(struct intel_encoder *encoder);
 
+/*
+ * Panel enable/disable sequences from the spec:
+ *
+ * v2 sequence for video mode:
+ * - power on
+ * - wait t1+t2
+ * - MIPIDeassertResetPin
+ * - clk/data lines to lp-11
+ * - MIPISendInitialDcsCmds
+ * - turn on DPI
+ * - MIPIDisplayOn
+ * - wait t5
+ * - backlight on
+ * ...
+ * - backlight off
+ * - wait t6
+ * - MIPIDisplayOff
+ * - turn off DPI
+ * - clk/data lines to lp-00
+ * - MIPIAssertResetPin
+ * - wait t3
+ * - power off
+ * - wait t4
+ *
+ * v3 sequence for video mode:
+ * - MIPIPanelPowerOn
+ * - MIPIDeassertResetPin
+ * - set clk/data lines to lp-11
+ * - MIPISendInitialDcsCmds (LP)
+ * - turn on DPI
+ * - MIPITearOn (command mode only) + MIPIDisplayOn (LP and HS)
+ * - MIPIBacklightOn
+ * ...
+ * - MIPIBacklightOff
+ * - turn off DPI
+ * - MIPITearOff + MIPIDisplayOff (LP)
+ * - clk/data lines to lp-00
+ * - MIPIAssertResetPin
+ * - MIPIPanelPowerOff
+ *
+ * sequence for command mode:
+ * - power on
+ * - wait t1+t2
+ * - MIPIDeassertResetPin
+ * - clk/data lines to lp-11
+ * - MIPISendInitialDcsCmds
+ * - MIPITearOn
+ * - MIPIDisplayOn
+ * - set pipe to dsr mode
+ * - wait t5
+ * - backlight on
+ * ... issue write_mem_start/write_mem_continue commands ...
+ * - backlight off
+ * - wait t6
+ * - disable pipe dsr mode
+ * - MIPITearOff
+ * - MIPIDisplayOff
+ * - clk/data lines to lp-00
+ * - MIPIAssertResetPin
+ * - wait t3
+ * - power off
+ * - wait t4
+ */
+
 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
 struct intel_crtc_state *pipe_config,
 struct drm_connector_state *conn_state)
-- 
2.9.3

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Re: [Intel-gfx] [PATCH 15/15] drm/i915/glk: Configure number of sprite planes properly

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi 

On Thu, Nov 10, 2016 at 05:23:20PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has 4 planes (3 sprites) per pipe.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/intel_device_info.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 185e3bb..602d761 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -278,7 +278,10 @@ void intel_device_info_runtime_init(struct 
> drm_i915_private *dev_priv)
>* we don't expose the topmost plane at all to prevent ABI breakage
>* down the line.
>*/
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEMINILAKE(dev_priv))
> + for_each_pipe(dev_priv, pipe)
> + info->num_sprites[pipe] = 3;
> + else if (IS_BROXTON(dev_priv)) {
>   info->num_sprites[PIPE_A] = 2;
>   info->num_sprites[PIPE_B] = 2;
>   info->num_sprites[PIPE_C] = 1;
> -- 
> 2.5.5
> 
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Re: [Intel-gfx] [RFC] drm/i915: Provide a hook for selftests

[Chris Wilson]

On Thu, Dec 01, 2016 at 11:32:44PM +, Chris Wilson wrote:
> To facilitate integration with igt, any parameter beginning with
> i915.subtest__ is interpreted as a selftest subtest executable
> independently via igt/drv_selftest.
> 
> +#define selftest(name, func) \
> +module_param_named(subtest__##name, i915_selftests[name].enabled, bool, 
> 0400);
> +#include "i915_selftests.h"
> +#undef selftest

Maybe igt__ is more useful as a prefix for the subtests? Shorter at
least.
-Chris

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[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Provide a hook for selftests

[Patchwork]

== Series Details ==

Series: drm/i915: Provide a hook for selftests
URL   : https://patchwork.freedesktop.org/series/16246/
State : success

== Summary ==

Series 16246v1 drm/i915: Provide a hook for selftests
https://patchwork.freedesktop.org/api/1.0/series/16246/revisions/1/mbox/

Test kms_force_connector_basic:
Subgroup prune-stale-modes:
skip   -> PASS   (fi-snb-2600)

fi-bdw-5557u total:245  pass:230  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:245  pass:205  dwarn:0   dfail:0   fail:0   skip:40 
fi-byt-j1900 total:245  pass:217  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820 total:245  pass:213  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770  total:245  pass:225  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r total:245  pass:225  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650   total:245  pass:192  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m total:245  pass:223  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770  total:245  pass:223  dwarn:0   dfail:0   fail:0   skip:22 
fi-kbl-7500u total:245  pass:223  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u total:245  pass:231  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:245  pass:224  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k total:245  pass:223  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:245  pass:231  dwarn:0   dfail:0   fail:0   skip:14 
fi-snb-2520m total:245  pass:213  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600  total:245  pass:212  dwarn:0   dfail:0   fail:0   skip:33 

7e65fe03f15b05cb579d694c6ff71e09f4e31c8e drm-tip: 2016y-12m-01d-18h-13m-38s UTC 
integration manifest
9ec1d7a drm/i915: Provide a hook for selftests

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3166/
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Re: [Intel-gfx] [PATCH i-g-t 0/4 v7] Convert sh scripts to C variants.

[Chris Wilson]

On Thu, Dec 01, 2016 at 02:23:54PM +0200, Marius Vlad wrote:
> Latest changes include addressing comments from previous version and include
> some notes about driver loading/unloading when using in combination to
> drm_open_driver().

Pushed the first 2 since I had an ulterior motive in writing a i915.ko
selftest runner. I was going to push the 4th (probe timings), but git
refused to apply it.

The actual conversion from sh to C for drv_module_reload_basic needs an
ack from Petri after some soak testing. Please rebase (if required).
-Chris

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Re: [Intel-gfx] [PATCH 14/15] drm/i915/glk: Implement core display init/uninit sequence for geminilake

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi 

On Thu, Nov 10, 2016 at 05:23:19PM +0200, Ander Conselvan de Oliveira wrote:
> The sequence is pretty much the same as broxton, except that bspec
> requires the AUX domains to be enabled. But since those can't be enabled
> before the phys are initialized, we just use the same sequence as
> broxton.
> 
> v2: Don't manually enable AUX domains. (Ander)
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 30d5112..2ee8984 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -2721,7 +2721,7 @@ void intel_power_domains_init_hw(struct 
> drm_i915_private *dev_priv, bool resume)
>  
>   if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
>   skl_display_core_init(dev_priv, resume);
> - } else if (IS_BROXTON(dev_priv)) {
> + } else if (IS_GEN9_LP(dev_priv)) {
>   bxt_display_core_init(dev_priv, resume);
>   } else if (IS_CHERRYVIEW(dev_priv)) {
>   mutex_lock(_domains->lock);
> @@ -2760,7 +2760,7 @@ void intel_power_domains_suspend(struct 
> drm_i915_private *dev_priv)
>  
>   if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
>   skl_display_core_uninit(dev_priv);
> - else if (IS_BROXTON(dev_priv))
> + else if (IS_GEN9_LP(dev_priv))
>   bxt_display_core_uninit(dev_priv);
>  }
>  
> -- 
> 2.5.5
> 
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Re: [Intel-gfx] [PATCH 13/15] drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi 

On Thu, Nov 10, 2016 at 05:23:18PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has double wide pipes so it can output two pixels per CD
> clock.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 62cc390..7763c44 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5830,8 +5830,10 @@ static int intel_compute_max_dotclk(struct 
> drm_i915_private *dev_priv)
>  {
>   int max_cdclk_freq = dev_priv->max_cdclk_freq;
>  
> - if (INTEL_INFO(dev_priv)->gen >= 9 ||
> - IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> + if (IS_GEMINILAKE(dev_priv))
> + return 2 * max_cdclk_freq;
> + else if (INTEL_INFO(dev_priv)->gen >= 9 ||
> +  IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>   return max_cdclk_freq;
>   else if (IS_CHERRYVIEW(dev_priv))
>   return max_cdclk_freq*95/100;
> @@ -6588,9 +6590,9 @@ static int valleyview_calc_cdclk(struct 
> drm_i915_private *dev_priv,
>  
>  static int glk_calc_cdclk(int max_pixclk)
>  {
> - if (max_pixclk > 158400)
> + if (max_pixclk > 2 * 158400)
>   return 316800;
> - else if (max_pixclk > 79200)
> + else if (max_pixclk > 2 * 79200)
>   return 158400;
>   else
>   return 79200;
> -- 
> 2.5.5
> 
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[Intel-gfx] [RFC] drm/i915: Provide a hook for selftests

[Chris Wilson]

Some pieces of code are independent of hardware but are very tricky to
exercise through the normal userspace ABI or via debugfs hooks. Being
able to create mock unit tests and execute them through CI is vital.
Start by adding a central point where we can execute unit tests from and
a parameter to enable them. This is disabled by default as the
expectation is that these tests will occasionally explode.

To facilitate integration with igt, any parameter beginning with
i915.subtest__ is interpreted as a selftest subtest executable
independently via igt/drv_selftest.

Signed-off-by: Chris Wilson 
---
 drivers/gpu/drm/i915/Kconfig.debug| 15 ++
 drivers/gpu/drm/i915/Makefile |  1 +
 drivers/gpu/drm/i915/i915_params.c|  5 ++
 drivers/gpu/drm/i915/i915_params.h|  3 ++
 drivers/gpu/drm/i915/i915_pci.c   |  6 +++
 drivers/gpu/drm/i915/i915_selftest.c  | 92 +++
 drivers/gpu/drm/i915/i915_selftest.h  | 40 +++
 drivers/gpu/drm/i915/i915_selftests.h | 11 +
 8 files changed, 173 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/i915_selftest.c
 create mode 100644 drivers/gpu/drm/i915/i915_selftest.h
 create mode 100644 drivers/gpu/drm/i915/i915_selftests.h

diff --git a/drivers/gpu/drm/i915/Kconfig.debug 
b/drivers/gpu/drm/i915/Kconfig.debug
index a6c69b8cb1d2..b48822288e22 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -23,6 +23,7 @@ config DRM_I915_DEBUG
 select DRM_VGEM # used by igt/prime_vgem (dmabuf interop checks)
 select DRM_DEBUG_MM if DRM=y
 select DRM_I915_SW_FENCE_DEBUG_OBJECTS if DRM_I915=y
+   select DRM_I915_SELFTEST
 default n
 help
   Choose this option to turn on extra driver debugging that may affect
@@ -56,3 +57,17 @@ config DRM_I915_SW_FENCE_DEBUG_OBJECTS
   Recommended for driver developers only.
 
   If in doubt, say "N".
+
+config DRM_I915_SELFTEST
+   bool "Enable selftests upon driver load"
+   depends on DRM_I915
+   default n
+   help
+ Choose this option to allow the driver to perform selftests upon
+ loading; also requires the i915.selftest=1 module parameter. To
+ exit the module after running the selftests (i.e. to prevent normal
+ module initialisation afterwards) use i915.selftest=-1.
+
+ Recommended for driver developers only.
+
+ If in doubt, say "N".
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 3c30916727fb..7c3b4f0c836c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -114,6 +114,7 @@ i915-y += dvo_ch7017.o \
 
 # Post-mortem debug and GPU hang state capture
 i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
+i915-$(CONFIG_DRM_I915_SELFTEST) += i915_selftest.o
 
 # virtual gpu code
 i915-y += i915_vgpu.o
diff --git a/drivers/gpu/drm/i915/i915_params.c 
b/drivers/gpu/drm/i915/i915_params.c
index 0e280fbd52f1..b66e38e66833 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -243,3 +243,8 @@ MODULE_PARM_DESC(enable_dpcd_backlight,
 module_param_named(enable_gvt, i915.enable_gvt, bool, 0400);
 MODULE_PARM_DESC(enable_gvt,
"Enable support for Intel GVT-g graphics virtualization host 
support(default:false)");
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+module_param_named_unsafe(selftest, i915.selftest, int, 0400);
+MODULE_PARM_DESC(selftest, "Run selftests when loading (0:disabled [default], 
1 run tests then load module, -1 run tests then exit module)");
+#endif
diff --git a/drivers/gpu/drm/i915/i915_params.h 
b/drivers/gpu/drm/i915/i915_params.h
index 8e433de04679..49ca8a6f9407 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -28,6 +28,9 @@
 #include  /* for __read_mostly */
 
 struct i915_params {
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+   int selftest;
+#endif
int modeset;
int panel_ignore_lid;
int semaphores;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 389a33090707..1683adb845ee 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -27,6 +27,7 @@
 #include 
 
 #include "i915_drv.h"
+#include "i915_selftest.h"
 
 #define GEN_DEFAULT_PIPEOFFSETS \
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
@@ -496,6 +497,11 @@ static struct pci_driver i915_pci_driver = {
 static int __init i915_init(void)
 {
bool use_kms = true;
+   int ret;
+
+   ret = i915_selftest();
+   if (ret)
+   return ret;
 
/*
 * Enable KMS by default, unless explicitly overriden by
diff --git a/drivers/gpu/drm/i915/i915_selftest.c 
b/drivers/gpu/drm/i915/i915_selftest.c
new file mode 100644
index ..2a8337dd6549
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_selftest.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright © 

Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support

[Srivatsa, Anusha]

>-Original Message-
>From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
>Sent: Thursday, December 1, 2016 5:24 AM
>To: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/huc: Add HuC fw loading support
>
>Hi,
>
>On 30/11/2016 23:31, Anusha Srivatsa wrote:
>> The HuC loading process is similar to GuC. The intel_uc_fw_fetch() is
>> used for both cases.
>>
>> HuC loading needs to be before GuC loading. The WOPCM setting must be
>> done early before loading any of them.
>>
>> v2: rebased on-top of drm-intel-nightly.
>> removed if(HAS_GUC()) before the guc call. (D.Gordon)
>> update huc_version number of format.
>> v3: rebased to drm-intel-nightly, changed the file name format to
>> match the one in the huc package.
>> Changed dev->dev_private to to_i915()
>> v4: moved function back to where it was.
>> change wait_for_atomic to wait_for.
>> v5: rebased + comment changes.
>> v7: rebased.
>> v8: rebased.
>> v9: rebased. Changed the year in the copyright message to reflect the
>> right year.Correct the comments,remove the unwanted WARN message,
>> replace drm_gem_object_unreference() with i915_gem_object_put().Make
>> the prototypes in intel_huc.h non-extern.
>> v10: rebased. Update the file construction done by HuC. It is similar
>> to GuC.Adopted the approach used in-
>> https://patchwork.freedesktop.org/patch/104355/ 
>> v11: Fix warnings remove old declaration
>> v12: Change dev to dev_priv in macro definition.
>> Corrected comments.
>> v13: rebased.
>> v14: rebased on top of drm-tip
>
>I thought we basically agreed to add i915.enable_huc (default=yes) and hide
>i915.enable_guc_loading, making it automatically turn on if either huc or guc
>submission are enabled?
Yes, I will be sending the patch for the same soon.

>Regards,
>
>Tvrtko
>
>>
>> Cc: Tvrtko Ursulin 
>> Tested-by: Xiang Haihao 
>> Signed-off-by: Anusha Srivatsa 
>> Signed-off-by: Alex Dai 
>> Signed-off-by: Peter Antoine 
>> Reviewed-by: Dave Gordon 
>> ---
>>  drivers/gpu/drm/i915/Makefile   |   1 +
>>  drivers/gpu/drm/i915/i915_drv.c |   4 +-
>>  drivers/gpu/drm/i915/i915_drv.h |   4 +-
>>  drivers/gpu/drm/i915/i915_guc_reg.h |   3 +
>>  drivers/gpu/drm/i915/intel_guc_loader.c |   6 +-
>>  drivers/gpu/drm/i915/intel_huc.h|  42 +
>>  drivers/gpu/drm/i915/intel_huc_loader.c | 267
>
>>  drivers/gpu/drm/i915/intel_uc.h |   2 +
>>  8 files changed, 324 insertions(+), 5 deletions(-)  create mode
>> 100644 drivers/gpu/drm/i915/intel_huc.h  create mode 100644
>> drivers/gpu/drm/i915/intel_huc_loader.c
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile
>> b/drivers/gpu/drm/i915/Makefile index 3c30916..01d4f4b 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -57,6 +57,7 @@ i915-y += i915_cmd_parser.o \  # general-purpose
>> microcontroller (GuC) support  i915-y += intel_uc.o \
>>intel_guc_loader.o \
>> +  intel_huc_loader.o \
>>i915_guc_submission.o
>>
>>  # autogenerated null render state
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c index 8dac298..075d9ce 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -603,6 +603,7 @@ static int i915_load_modeset_init(struct drm_device
>*dev)
>>  if (ret)
>>  goto cleanup_irq;
>>
>> +intel_huc_init(dev);
>>  intel_guc_init(dev);
>>
>>  ret = i915_gem_init(dev);
>> @@ -630,6 +631,7 @@ static int i915_load_modeset_init(struct drm_device
>*dev)
>>  DRM_ERROR("failed to idle hardware; continuing to unload!\n");
>>  i915_gem_fini(dev_priv);
>>  cleanup_irq:
>> +intel_huc_fini(dev);
>>  intel_guc_fini(dev);
>>  drm_irq_uninstall(dev);
>>  intel_teardown_gmbus(dev);
>> @@ -1326,7 +1328,7 @@ void i915_driver_unload(struct drm_device *dev)
>>
>>  /* Flush any outstanding unpin_work. */
>>  drain_workqueue(dev_priv->wq);
>> -
>> +intel_huc_fini(dev);
>>  intel_guc_fini(dev);
>>  i915_gem_fini(dev_priv);
>>  intel_fbc_cleanup_cfb(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index 297ad03..8edfae6 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -56,6 +56,7 @@
>>  #include "intel_bios.h"
>>  #include "intel_dpll_mgr.h"
>>  #include "intel_uc.h"
>> +#include "intel_huc.h"
>>  #include "intel_lrc.h"
>>  #include "intel_ringbuffer.h"
>>
>> @@ -1933,6 +1934,7 @@ struct drm_i915_private {
>>
>>  struct intel_gvt *gvt;
>>
>> +struct intel_huc huc;
>>  struct intel_guc guc;
>>
>>  struct intel_csr csr;
>> @@ -2698,7 +2700,7 @@ intel_info(const struct 

Re: [Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct for GuC and HuC

[Srivatsa, Anusha]

>-Original Message-
>From: Hiler, Arkadiusz
>Sent: Thursday, December 1, 2016 4:23 AM
>To: Srivatsa, Anusha 
>Cc: intel-gfx@lists.freedesktop.org; Mcgee, Jeff ;
>Kamble, Sagar A 
>Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/huc: Unified css_header struct 
>for
>GuC and HuC
>
>On Wed, Nov 30, 2016 at 03:31:28PM -0800, Anusha Srivatsa wrote:
>> From: Peter Antoine 
>>
>> HuC firmware css header has almost exactly same definition as GuC
>> firmware except for the sw_version. Also, add a new member fw_type
>> into intel_uc_fw to indicate what kind of fw it is. So, the loader
>> will pull right sw_version from header.
>>
>> v2: rebased on-top of drm-intel-nightly
>> v3: rebased on-top of drm-intel-nightly (again).
>> v4: rebased + spaces.
>> v7: rebased.
>> v8: rebased.
>> v9: rebased. Rename device_id to guc_branch_client_version, make
>> guc_sw_version a union. . Put UC_FW_TYPE_GUC and
>> UC_FW_TYPE_HUC into an enum.
>> v10: rebased.
>> v11: rebased.
>> v12: rebased on top of drm-tip.
>>
>> Tested-by: Xiang Haihao 
>> Signed-off-by: Anusha Srivatsa 
>> Signed-off-by: Alex Dai 
>> Signed-off-by: Peter Antoine 
>> Reviewed-by: Dave Gordon 
>> Reviewed-by: Jeff McGee 
>> ---
>>  drivers/gpu/drm/i915/intel_guc_fwif.h   | 21 +
>>  drivers/gpu/drm/i915/intel_guc_loader.c | 41 ++---
>
>>  drivers/gpu/drm/i915/intel_uc.h |  5 
>>  3 files changed, 50 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> index 00ca0df..c07d9da 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
>> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
>> @@ -154,7 +154,7 @@
>>   * The GuC firmware layout looks like this:
>>   *
>>   * +---+
>> - * |guc_css_header |
>> + * | uc_css_header |
>>   * |   |
>>   * | contains major/minor version  |
>>   * +---+
>> @@ -181,9 +181,16 @@
>>   * 3. Length info of each component can be found in header, in dwords.
>>   * 4. Modulus and exponent key are not required by driver. They may not
>appear
>>   *in fw. So driver will load a truncated firmware in this case.
>> + *
>> + * HuC firmware layout is same as GuC firmware.
>> + *
>> + * HuC firmware css header is different. However, the only difference
>> + is where
>> + * the version information is saved. The uc_css_header is unified to
>> + support
>> + * both. Driver should get HuC version from
>> + uc_css_header.huc_sw_version, while
>> + * uc_css_header.guc_sw_version for GuC.
>>   */
>>
>> -struct guc_css_header {
>> +struct uc_css_header {
>
>I think we should either move most of this stuff to intel_uc.{c,h} or rename 
>the
>file to intel_uc_fwif.h.
>
>Anyway, this file contains information on top that this is automatically 
>generated
>and your changes might be lost...
>
>The file was introduced and then *manually edited* *multiple times* by *many
>people*, without any signs of changes lost or file being regenerated.
>
>I think we can, at least, drop the warning. I am in favor of drooping the file
>completely though.
So, basically move all these struct and union declarations to intel_uc.h?
>If something would change, we can assume it would be done by hand anyway.
>
>Jeff, Sagar: any thought on that?
>
>>  uint32_t module_type;
>>  /* header_size includes all non-uCode bits, including css_header, rsa
>>   * key, modulus key and exponent data. */ @@ -214,8 +221,14 @@
>> struct guc_css_header {
>>
>>  char username[8];
>>  char buildnumber[12];
>> -uint32_t device_id;
>> -uint32_t guc_sw_version;
>> +union {
>> +uint32_t guc_branch_client_version;
>> +uint32_t huc_sw_version;
>> +};
>> +union {
>> +uint32_t guc_sw_version;
>> +uint32_t huc_reserved;
>> +};
>>  uint32_t prod_preprod_fw;
>>  uint32_t reserved[12];
>>  uint32_t header_info;
>> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c
>> b/drivers/gpu/drm/i915/intel_guc_loader.c
>> index e55ec2c..557d4b4 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
>> @@ -593,7 +593,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct
>intel_uc_fw *uc_fw)
>>  struct pci_dev *pdev = dev->pdev;
>>  struct drm_i915_gem_object *obj;
>>  const struct firmware *fw = NULL;
>> -struct guc_css_header *css;
>> +struct uc_css_header *css;
>>  size_t size;
>>  int err;
>>
>> @@ -610,19 +610,19 @@ void intel_uc_fw_fetch(struct drm_device *dev,
>struct intel_uc_fw *uc_fw)
>>  uc_fw->uc_fw_path, 

[Intel-gfx] ✗ Fi.CI.BAT: warning for drm/i915: Calculate common rates and max lane count in Long pulse handler

[Patchwork]

== Series Details ==

Series: drm/i915: Calculate common rates and max lane count in Long pulse 
handler
URL   : https://patchwork.freedesktop.org/series/16250/
State : warning

== Summary ==

Series 16250v1 drm/i915: Calculate common rates and max lane count in Long 
pulse handler
https://patchwork.freedesktop.org/api/1.0/series/16250/revisions/1/mbox/

Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass   -> DMESG-WARN (fi-ivb-3770)
Test kms_force_connector_basic:
Subgroup prune-stale-modes:
skip   -> PASS   (fi-snb-2600)

fi-bdw-5557u total:245  pass:230  dwarn:0   dfail:0   fail:0   skip:15 
fi-bsw-n3050 total:245  pass:205  dwarn:0   dfail:0   fail:0   skip:40 
fi-bxt-t5700 total:245  pass:217  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-j1900 total:245  pass:217  dwarn:0   dfail:0   fail:0   skip:28 
fi-byt-n2820 total:245  pass:213  dwarn:0   dfail:0   fail:0   skip:32 
fi-hsw-4770  total:245  pass:225  dwarn:0   dfail:0   fail:0   skip:20 
fi-hsw-4770r total:245  pass:225  dwarn:0   dfail:0   fail:0   skip:20 
fi-ilk-650   total:245  pass:192  dwarn:0   dfail:0   fail:0   skip:53 
fi-ivb-3520m total:245  pass:223  dwarn:0   dfail:0   fail:0   skip:22 
fi-ivb-3770  total:245  pass:222  dwarn:1   dfail:0   fail:0   skip:22 
fi-kbl-7500u total:245  pass:223  dwarn:0   dfail:0   fail:0   skip:22 
fi-skl-6260u total:245  pass:231  dwarn:0   dfail:0   fail:0   skip:14 
fi-skl-6700hqtotal:245  pass:224  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6700k total:245  pass:223  dwarn:1   dfail:0   fail:0   skip:21 
fi-skl-6770hqtotal:245  pass:231  dwarn:0   dfail:0   fail:0   skip:14 
fi-snb-2520m total:245  pass:213  dwarn:0   dfail:0   fail:0   skip:32 
fi-snb-2600  total:245  pass:212  dwarn:0   dfail:0   fail:0   skip:33 

7e65fe03f15b05cb579d694c6ff71e09f4e31c8e drm-tip: 2016y-12m-01d-18h-13m-38s UTC 
integration manifest
f432c89 drm/i915: Calculate common rates and max lane count in Long pulse 
handler

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3167/
___
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Intel-gfx@lists.freedesktop.org
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[Intel-gfx] [PATCH] drm/i915: Calculate common rates and max lane count in Long pulse handler

[Manasi Navare]

Supported link rate common to source and sink as well as the
maximum supported lane count based on source and sink capabilities should
be set only once on hotplug and then used anytime they are requested.
This patch creates and array of common rates and max lane count as the
intel_dp member. It gets calculated only once in the long pulse handler
and then gets used when requested in compute_config and other functions.

Cc: Jani Nikula 
Cc: Daniel Vetter 
Cc: Ville Syrjala 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/intel_dp.c  | 38 --
 drivers/gpu/drm/i915/intel_drv.h |  5 +
 2 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9dfbde4..de37807 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -274,8 +274,7 @@ static int intersect_rates(const int *source_rates, int 
source_len,
return k;
 }
 
-static int intel_dp_common_rates(struct intel_dp *intel_dp,
-int *common_rates)
+static int intel_dp_common_rates(struct intel_dp *intel_dp)
 {
const int *source_rates, *sink_rates;
int source_len, sink_len;
@@ -285,7 +284,7 @@ static int intel_dp_common_rates(struct intel_dp *intel_dp,
 
return intersect_rates(source_rates, source_len,
   sink_rates, sink_len,
-  common_rates);
+  intel_dp->common_rates);
 }
 
 static enum drm_mode_status
@@ -312,7 +311,7 @@ static int intel_dp_common_rates(struct intel_dp *intel_dp,
}
 
max_link_clock = intel_dp_max_link_rate(intel_dp);
-   max_lanes = intel_dp_max_lane_count(intel_dp);
+   max_lanes = intel_dp->max_lane_count;
 
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(target_clock, 18);
@@ -1430,8 +1429,7 @@ static void snprintf_int_array(char *str, size_t len,
 static void intel_dp_print_rates(struct intel_dp *intel_dp)
 {
const int *source_rates, *sink_rates;
-   int source_len, sink_len, common_len;
-   int common_rates[DP_MAX_SUPPORTED_RATES];
+   int source_len, sink_len;
char str[128]; /* FIXME: too big for stack? */
 
if ((drm_debug & DRM_UT_KMS) == 0)
@@ -1445,8 +1443,8 @@ static void intel_dp_print_rates(struct intel_dp 
*intel_dp)
snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
DRM_DEBUG_KMS("sink rates: %s\n", str);
 
-   common_len = intel_dp_common_rates(intel_dp, common_rates);
-   snprintf_int_array(str, sizeof(str), common_rates, common_len);
+   snprintf_int_array(str, sizeof(str), intel_dp->common_rates,
+  intel_dp->common_len);
DRM_DEBUG_KMS("common rates: %s\n", str);
 }
 
@@ -1495,14 +1493,12 @@ static int rate_to_index(int find, const int *rates)
 int
 intel_dp_max_link_rate(struct intel_dp *intel_dp)
 {
-   int rates[DP_MAX_SUPPORTED_RATES] = {};
-   int len;
+   int len = intel_dp->common_len;
 
-   len = intel_dp_common_rates(intel_dp, rates);
if (WARN_ON(len <= 0))
return 162000;
 
-   return rates[len - 1];
+   return intel_dp->common_rates[len - 1];
 }
 
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
@@ -1550,22 +1546,18 @@ static int intel_dp_compute_bpp(struct intel_dp 
*intel_dp,
struct intel_connector *intel_connector = intel_dp->attached_connector;
int lane_count, clock;
int min_lane_count = 1;
-   int max_lane_count = intel_dp_max_lane_count(intel_dp);
+   int max_lane_count = intel_dp->max_lane_count;
/* Conveniently, the link BW constants become indices with a shift...*/
int min_clock = 0;
int max_clock;
int bpp, mode_rate;
int link_avail, link_clock;
-   int common_rates[DP_MAX_SUPPORTED_RATES] = {};
-   int common_len;
uint8_t link_bw, rate_select;
 
-   common_len = intel_dp_common_rates(intel_dp, common_rates);
-
/* No common link rates between source and sink */
-   WARN_ON(common_len <= 0);
+   WARN_ON(intel_dp->common_len <= 0);
 
-   max_clock = common_len - 1;
+   max_clock = intel_dp->common_len - 1;
 
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -1597,7 +1589,7 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
 
DRM_DEBUG_KMS("DP link computation with max lane count %i "
  "max bw %d pixel clock %iKHz\n",
- max_lane_count, common_rates[max_clock],
+ max_lane_count, intel_dp->common_rates[max_clock],
  adjusted_mode->crtc_clock);
 
/* Walk 

Re: [Intel-gfx] [PATCH 08/15] drm/i915/glk: Add power wells for Geminilake

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi 

On Thu, Nov 10, 2016 at 05:23:13PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has power wells are similar to SKL, but with the misc IO well
> being split into separate AUX IO wells.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   6 ++
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 114 
> +++-
>  2 files changed, 117 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1be2a7d..78a3347 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -708,9 +708,15 @@ enum skl_disp_power_wells {
>   /* These numbers are fixed and must match the position of the pw bits */
>   SKL_DISP_PW_MISC_IO,
>   SKL_DISP_PW_DDI_A_E,
> + GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
>   SKL_DISP_PW_DDI_B,
>   SKL_DISP_PW_DDI_C,
>   SKL_DISP_PW_DDI_D,
> +
> + GLK_DISP_PW_AUX_A = 8,
> + GLK_DISP_PW_AUX_B,
> + GLK_DISP_PW_AUX_C,
> +
>   SKL_DISP_PW_1 = 14,
>   SKL_DISP_PW_2,
>  
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c 
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 697574f..683c15b 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -453,6 +453,45 @@ static void hsw_set_power_well(struct drm_i915_private 
> *dev_priv,
>   BIT(POWER_DOMAIN_AUX_C) |   \
>   BIT(POWER_DOMAIN_INIT))
>  
> +#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS (  \
> + BIT(POWER_DOMAIN_TRANSCODER_A) |\
> + BIT(POWER_DOMAIN_PIPE_B) |  \
> + BIT(POWER_DOMAIN_TRANSCODER_B) |\
> + BIT(POWER_DOMAIN_PIPE_C) |  \
> + BIT(POWER_DOMAIN_TRANSCODER_C) |\
> + BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |\
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |\
> + BIT(POWER_DOMAIN_AUX_B) |   \
> + BIT(POWER_DOMAIN_AUX_C) |   \
> + BIT(POWER_DOMAIN_AUDIO) |   \
> + BIT(POWER_DOMAIN_VGA) | \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_DDI_A_POWER_DOMAINS (\
> + BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |\
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_DDI_B_POWER_DOMAINS (\
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |\
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_DDI_C_POWER_DOMAINS (\
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |\
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_AUX_A_POWER_DOMAINS (\
> + BIT(POWER_DOMAIN_AUX_A) |   \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_AUX_B_POWER_DOMAINS (\
> + BIT(POWER_DOMAIN_AUX_B) |   \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_AUX_C_POWER_DOMAINS (\
> + BIT(POWER_DOMAIN_AUX_C) |   \
> + BIT(POWER_DOMAIN_INIT))
> +#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS (   \
> + GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT(POWER_DOMAIN_MODESET) | \
> + BIT(POWER_DOMAIN_AUX_A) |   \
> + BIT(POWER_DOMAIN_INIT))
> +
>  static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
>  {
>   WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> @@ -694,7 +733,7 @@ gen9_sanitize_power_well_requests(struct drm_i915_private 
> *dev_priv,
>  }
>  
>  static void skl_set_power_well(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well, bool enable)
> +struct i915_power_well *power_well, bool enable)
>  {
>   uint32_t tmp, fuse_status;
>   uint32_t req_mask, state_mask;
> @@ -720,11 +759,14 @@ static void skl_set_power_well(struct drm_i915_private 
> *dev_priv,
>   return;
>   }
>   break;
> - case SKL_DISP_PW_DDI_A_E:
> + case SKL_DISP_PW_MISC_IO:
> + case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A */
>   case SKL_DISP_PW_DDI_B:
>   case SKL_DISP_PW_DDI_C:
>   case SKL_DISP_PW_DDI_D:
> - case SKL_DISP_PW_MISC_IO:
> + case GLK_DISP_PW_AUX_A:
> + case GLK_DISP_PW_AUX_B:
> + case GLK_DISP_PW_AUX_C:
>   break;
>   default:
>   WARN(1, "Unknown power well %lu\n", power_well->id);
> @@ -2150,6 +2192,70 @@ static struct i915_power_well bxt_power_wells[] = {
>   },
>  };
>  
> +static struct i915_power_well glk_power_wells[] = {
> + {
> + .name = "always-on",
> + .always_on = 

Re: [Intel-gfx] [PATCH 07/15] drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too

[Rodrigo Vivi]

This could be squashed to the other bit patch with s/broxton/gen9_lp...

but anyway

Reviewed-by: Rodrigo Vivi 



On Thu, Nov 10, 2016 at 05:23:12PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake uses the same lane latency optimization masks and registers
> as Broxton, so reuse the code with that platform too.
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> b/drivers/gpu/drm/i915/intel_ddi.c
> index dcad209..aec8265 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1429,7 +1429,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder 
> *encoder,
>   DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
>  
>  out:
> - if (ret && IS_BROXTON(dev_priv)) {
> + if (ret && IS_GEN9_LP(dev_priv)) {
>   tmp = I915_READ(BXT_PHY_CTL(port));
>   if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
>   BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
> @@ -2044,7 +2044,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
>  
>   intel_ddi_clock_get(encoder, pipe_config);
>  
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
>   pipe_config->lane_lat_optim_mask =
>   bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
>  }
> @@ -2068,7 +2068,7 @@ static bool intel_ddi_compute_config(struct 
> intel_encoder *encoder,
>   else
>   ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
>  
> - if (IS_BROXTON(dev_priv) && ret)
> + if (IS_GEN9_LP(dev_priv) && ret)
>   pipe_config->lane_lat_optim_mask =
>   bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
>
> pipe_config->lane_count);
> @@ -2225,7 +2225,7 @@ void intel_ddi_init(struct drm_device *dev, enum port 
> port)
>  
>   intel_encoder->compute_config = intel_ddi_compute_config;
>   intel_encoder->enable = intel_enable_ddi;
> - if (IS_BROXTON(dev_priv))
> + if (IS_GEN9_LP(dev_priv))
>   intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
>   intel_encoder->pre_enable = intel_ddi_pre_enable;
>   intel_encoder->disable = intel_disable_ddi;
> -- 
> 2.5.5
> 
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Re: [Intel-gfx] [PATCH 06/15] drm/i915/glk: Force DDI initialization.

[Rodrigo Vivi]

This could also be squashed or reviewed-by you...
either works for me, I just cannot review the patch that I'm listed as author ;)


On Thu, Nov 10, 2016 at 05:23:11PM +0200, Ander Conselvan de Oliveira wrote:
> From: Rodrigo Vivi 
> 
> As for BXT, GLK doesn't support port detection through SFUSE_STRAP, so
> let's force DDI initialization in order to get HDMI and DP.
> 
> v2: Use dev_priv instead of dev. (Tvrtko)
> Signed-off-by: Rodrigo Vivi 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index c6ffe0a..4069a6e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15491,7 +15491,7 @@ static void intel_setup_outputs(struct drm_device 
> *dev)
>   if (intel_crt_present(dev))
>   intel_crt_init(dev);
>  
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
>   /*
>* FIXME: Broxton doesn't support port detection via the
>* DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
> -- 
> 2.5.5
> 
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Re: [Intel-gfx] [PATCH 12/15] drm/i915/glk: Reuse broxton's cdclk code for GLK

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi 

On Thu, Nov 10, 2016 at 05:23:17PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has the same register layout, reference clock and programming
> sequence as broxton. The difference is that it doesn't support the 1.5
> divider and has different ratios, but a lot of code can be shared
> between the two platforms.
> 
> v2: Rebase (s/broxton/bxt).
> 
> v3: Fix vco calculation in glk_de_pll_vco().
> 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/intel_display.c | 73 
> 
>  1 file changed, 65 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index 4069a6e..62cc390 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -124,6 +124,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc);
>  static void intel_modeset_setup_hw_state(struct drm_device *dev);
>  static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
>  static int ilk_max_pixel_rate(struct drm_atomic_state *state);
> +static int glk_calc_cdclk(int max_pixclk);
>  static int bxt_calc_cdclk(int max_pixclk);
>  
>  struct intel_limit {
> @@ -5866,6 +5867,8 @@ static void intel_update_max_cdclk(struct 
> drm_i915_private *dev_priv)
>   max_cdclk = 308571;
>  
>   dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
> + } else if (IS_GEMINILAKE(dev_priv)) {
> + dev_priv->max_cdclk_freq = 316800;
>   } else if (IS_BROXTON(dev_priv)) {
>   dev_priv->max_cdclk_freq = 624000;
>   } else if (IS_BROADWELL(dev_priv))  {
> @@ -5953,6 +5956,26 @@ static int bxt_de_pll_vco(struct drm_i915_private 
> *dev_priv, int cdclk)
>   return dev_priv->cdclk_pll.ref * ratio;
>  }
>  
> +static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> +{
> + int ratio;
> +
> + if (cdclk == dev_priv->cdclk_pll.ref)
> + return 0;
> +
> + switch (cdclk) {
> + default:
> + MISSING_CASE(cdclk);
> + case  79200:
> + case 158400:
> + case 316800:
> + ratio = 33;
> + break;
> + }
> +
> + return dev_priv->cdclk_pll.ref * ratio;
> +}
> +
>  static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
>  {
>   I915_WRITE(BXT_DE_PLL_ENABLE, 0);
> @@ -5994,7 +6017,10 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv, int cdclk)
>   u32 val, divider;
>   int vco, ret;
>  
> - vco = bxt_de_pll_vco(dev_priv, cdclk);
> + if (IS_GEMINILAKE(dev_priv))
> + vco = glk_de_pll_vco(dev_priv, cdclk);
> + else
> + vco = bxt_de_pll_vco(dev_priv, cdclk);
>  
>   DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
>  
> @@ -6007,6 +6033,7 @@ static void bxt_set_cdclk(struct drm_i915_private 
> *dev_priv, int cdclk)
>   divider = BXT_CDCLK_CD2X_DIV_SEL_2;
>   break;
>   case 3:
> + WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
>   divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
>   break;
>   case 2:
> @@ -6116,6 +6143,8 @@ static void bxt_sanitize_cdclk(struct drm_i915_private 
> *dev_priv)
>  
>  void bxt_init_cdclk(struct drm_i915_private *dev_priv)
>  {
> + int cdclk;
> +
>   bxt_sanitize_cdclk(dev_priv);
>  
>   if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
> @@ -6126,7 +6155,12 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
>* - The initial CDCLK needs to be read from VBT.
>*   Need to make this change after VBT has changes for BXT.
>*/
> - bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
> + if (IS_GEMINILAKE(dev_priv))
> + cdclk = glk_calc_cdclk(0);
> + else
> + cdclk = bxt_calc_cdclk(0);
> +
> + bxt_set_cdclk(dev_priv, cdclk);
>  }
>  
>  void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
> @@ -6552,6 +6586,16 @@ static int valleyview_calc_cdclk(struct 
> drm_i915_private *dev_priv,
>   return 20;
>  }
>  
> +static int glk_calc_cdclk(int max_pixclk)
> +{
> + if (max_pixclk > 158400)
> + return 316800;
> + else if (max_pixclk > 79200)
> + return 158400;
> + else
> + return 79200;
> +}
> +
>  static int bxt_calc_cdclk(int max_pixclk)
>  {
>   if (max_pixclk > 576000)
> @@ -6614,15 +6658,27 @@ static int valleyview_modeset_calc_cdclk(struct 
> drm_atomic_state *state)
>  
>  static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>  {
> + struct drm_i915_private *dev_priv = to_i915(state->dev);
>   int max_pixclk = ilk_max_pixel_rate(state);
>   struct intel_atomic_state *intel_state =
>   to_intel_atomic_state(state);
> + int cdclk;
>  
> - 

Re: [Intel-gfx] [PATCH 11/15] drm/i915/glk: Update Port PLL enable sequence for Geminilkae

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi 

On Thu, Nov 10, 2016 at 05:23:16PM +0200, Ander Conselvan de Oliveira wrote:
> From: Madhav Chauhan 
> 
> Add steps for enabling and disabling Port PLL as per bspec.
> 
> Signed-off-by: Madhav Chauhan 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/i915_reg.h   |  2 ++
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 20 
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 88f9f2b..98e24a7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1238,6 +1238,8 @@ enum skl_disp_power_wells {
>  #define   PORT_PLL_ENABLE(1 << 31)
>  #define   PORT_PLL_LOCK  (1 << 30)
>  #define   PORT_PLL_REF_SEL   (1 << 27)
> +#define   PORT_PLL_POWER_ENABLE  (1 << 26)
> +#define   PORT_PLL_POWER_STATE   (1 << 25)
>  #define BXT_PORT_PLL_ENABLE(port)_MMIO_PORT(port, _PORT_PLL_A, 
> _PORT_PLL_B)
>  
>  #define _PORT_PLL_EBB_0_A0x162034
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 24a28b2..35f5f1a 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1381,6 +1381,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private 
> *dev_priv,
>   temp |= PORT_PLL_REF_SEL;
>   I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>  
> + if (IS_GEMINILAKE(dev_priv)) {
> + temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> + temp |= PORT_PLL_POWER_ENABLE;
> + I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
> +
> + if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
> +  PORT_PLL_POWER_STATE), 200))
> + DRM_ERROR("Power state not set for PLL:%d\n", port);
> + }
> +
>   /* Disable 10 bit clock */
>   temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch));
>   temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
> @@ -1486,6 +1496,16 @@ static void bxt_ddi_pll_disable(struct 
> drm_i915_private *dev_priv,
>   temp &= ~PORT_PLL_ENABLE;
>   I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>   POSTING_READ(BXT_PORT_PLL_ENABLE(port));
> +
> + if (IS_GEMINILAKE(dev_priv)) {
> + temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> + temp &= ~PORT_PLL_POWER_ENABLE;
> + I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
> +
> + if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) &
> + PORT_PLL_POWER_STATE), 200))
> + DRM_ERROR("Power state not reset for PLL:%d\n", port);
> + }
>  }
>  
>  static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> -- 
> 2.5.5
> 
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Re: [Intel-gfx] [PATCH v3] drm/i915/glk: Reuse broxton code for geminilake

[Rodrigo Vivi]

A reviewed backwards because I was willing to check if all ifs were in place.

I missed the ones from i915_drv.c

*** i915_drv.c:
i915_drm_suspend_late[1500]fw_csr = !IS_GEN9_LP(dev_priv) &&
i915_drm_suspend_late[1513]if (IS_GEN9_LP(dev_priv))
i915_drm_resume_early[1721]if (IS_GEN9_LP(dev_priv)) {
i915_drm_resume_early[1731]if (IS_GEN9_LP(dev_priv) ||
intel_runtime_suspend[2354]if (IS_GEN9_LP(dev_priv)) {
intel_runtime_resume[2439] if (IS_GEN9_LP(dev_priv)) {

The ones that I had added with the patch
"drm/i915/glk: Add missing bits to allow runtime pm suspend on GLK."

Feel free to squash all those into this patch if you like. However I believe 
that before that one we need Anusha's dmc load patch that is one that I'm also 
missing on this series here, right?

So any option works for me and if you decide to move with this feel free to use
Reviewed-by: Rodrigo Vivi 

And please let me know what are your plans with this runtime_pm related patches 
and if you need anything from me.

Thanks,
Rodrigo.

On Tue, Nov 29, 2016 at 05:47:12PM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake is mostly backwards compatible with broxton, so change most
> of the IS_BROXTON() checks to IS_GEN9_LP(). Differences between the
> platforms will be implemented in follow-up patches.
>
> v2: Don't reuse broxton's path in intel_update_max_cdclk().
> Don't set plane count as in broxton.
>
> v3: Rebase
>
> v4: Include the check intel_bios_is_port_hpd_inverted().
> Commit message.
>
> v5: Leave i915_dmc_info() out; glk's csr version != bxt's. (Rodrigo)
>
> v6: Rebase.
>
> v7: Convert a few mode IS_BROXTON() occurances in pps, ddi, dsi and pll
> code. (Rodrigo)
>
> Cc: Rodrigo Vivi 
> Signed-off-by: Ander Conselvan de Oliveira 
> 
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 10 +-
>  drivers/gpu/drm/i915/i915_gem_gtt.c |  8 
>  drivers/gpu/drm/i915/i915_irq.c | 10 +-
>  drivers/gpu/drm/i915/i915_reg.h |  4 ++--
>  drivers/gpu/drm/i915/intel_bios.c   |  2 +-
>  drivers/gpu/drm/i915/intel_ddi.c| 18 +-
>  drivers/gpu/drm/i915/intel_display.c| 12 ++--
>  drivers/gpu/drm/i915/intel_dp.c | 24 
>  drivers/gpu/drm/i915/intel_dpio_phy.c   |  1 -
>  drivers/gpu/drm/i915/intel_dpll_mgr.c   |  2 +-
>  drivers/gpu/drm/i915/intel_dsi.c| 30 +++---
>  drivers/gpu/drm/i915/intel_dsi_pll.c| 12 ++--
>  drivers/gpu/drm/i915/intel_hdmi.c   |  6 +++---
>  drivers/gpu/drm/i915/intel_i2c.c|  4 ++--
>  drivers/gpu/drm/i915/intel_mocs.c   |  2 +-
>  drivers/gpu/drm/i915/intel_panel.c  |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c |  6 +++---
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  6 +++---
>  18 files changed, 79 insertions(+), 80 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8eb8c29..6c17d39 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1108,7 +1108,7 @@ static int i915_frequency_info(struct seq_file *m, void 
> *unused)
>   int max_freq;
>
>   rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
>   rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
>   gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
>   } else {
> @@ -1204,7 +1204,7 @@ static int i915_frequency_info(struct seq_file *m, void 
> *unused)
>   seq_printf(m, "Down threshold: %d%%\n",
>  dev_priv->rps.down_threshold);
>
> - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
> + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
>   rp_state_cap >> 16) & 0xff;
>   max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
>GEN9_FREQ_SCALER : 1);
> @@ -1217,7 +1217,7 @@ static int i915_frequency_info(struct seq_file *m, void 
> *unused)
>   seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
>  intel_gpu_freq(dev_priv, max_freq));
>
> - max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
> + max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
>   rp_state_cap >> 0) & 0xff;
>   max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
>GEN9_FREQ_SCALER : 1);
> @@ -5169,7 +5169,7 @@ static void gen9_sseu_device_status(struct 
> drm_i915_private *dev_priv,
>   u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
>
>   /* BXT has a single slice and at most 3 subslices. */
> - if (IS_BROXTON(dev_priv)) {
> + if (IS_GEN9_LP(dev_priv)) {
> 

Re: [Intel-gfx] [RFC 2/3] drm: Register drmfs filesystem from drm init

[Daniel Vetter]

On Thu, Dec 01, 2016 at 01:44:16PM +0530, swati.dhin...@intel.com wrote:
> From: Swati Dhingra 
> 
> During drm module initialization, drm_core_init initializes the drmfs
> filesystem and register this with kernel. A driver specific directory is 
> created
> inside drmfs root, and dentry of this directory is saved for subsequent use
> by the driver (e.g. i915). The driver can then create files/directories inside
> this root directory directly.
> In case of i915 driver, the top directory is created at 
> '/sys/kernel/drm/i915'.
> 
> Signed-off-by: Sourab Gupta 
> Signed-off-by: Swati Dhingra 
> ---
>  drivers/gpu/drm/drm_drv.c | 22 ++
>  include/drm/drm_drv.h |  3 +++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
> index 84fcfcb..ead360bd 100644
> --- a/drivers/gpu/drm/drm_drv.c
> +++ b/drivers/gpu/drm/drm_drv.c
> @@ -688,6 +688,14 @@ int drm_dev_register(struct drm_device *dev, unsigned 
> long flags)
>  {
>   int ret;
>  
> +#ifdef CONFIG_DRMFS
> + dev->driver->drmfs_root = drmfs_create_dir(dev->driver->name, NULL);
> + if (IS_ERR(dev->driver->drmfs_root)) {
> + DRM_ERROR("Failed to get drmfs root dentry\n");
> + return PTR_ERR(dev->driver->drmfs_root);
> + }
> +#endif

Don't do #ifdef in the code, instead provide dummy static inline functions
that do nothing in headers when a feature is disabled. For an example see
CONFIG_DRM_FBDEV_EMULATION in drm_fb_helper.[hc].

Also, drmfs here is seriously lacking documentation. E.g. where are we
supposed to put different things related to rendering, modesetting, and
all these issues? You need to add a section in drm-uabi.rst, write
kernel-doc + overview sections for all of this and pull it in.
-Daniel

> +
>   mutex_lock(_global_mutex);
>  
>   ret = drm_minor_register(dev, DRM_MINOR_CONTROL);
> @@ -758,6 +766,9 @@ void drm_dev_unregister(struct drm_device *dev)
>   drm_minor_unregister(dev, DRM_MINOR_PRIMARY);
>   drm_minor_unregister(dev, DRM_MINOR_RENDER);
>   drm_minor_unregister(dev, DRM_MINOR_CONTROL);
> +#ifdef CONFIG_DRMFS
> + drmfs_remove(dev->driver->drmfs_root);
> +#endif
>  }
>  EXPORT_SYMBOL(drm_dev_unregister);
>  
> @@ -825,6 +836,9 @@ static void drm_core_exit(void)
>  {
>   unregister_chrdev(DRM_MAJOR, "drm");
>   debugfs_remove(drm_debugfs_root);
> +#ifdef CONFIG_DRMFS
> + drmfs_fini();
> +#endif
>   drm_sysfs_destroy();
>   idr_destroy(_minors_idr);
>   drm_connector_ida_destroy();
> @@ -845,6 +859,14 @@ static int __init drm_core_init(void)
>   goto error;
>   }
>  
> +#ifdef CONFIG_DRMFS
> + ret = drmfs_init();
> + if (ret < 0) {
> + DRM_ERROR("Cannot create DRM FS: %d\n", ret);
> + goto error;
> + }
> +#endif
> +
>   drm_debugfs_root = debugfs_create_dir("dri", NULL);
>   if (!drm_debugfs_root) {
>   ret = -ENOMEM;
> diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
> index aad8bba..34804de 100644
> --- a/include/drm/drm_drv.h
> +++ b/include/drm/drm_drv.h
> @@ -403,6 +403,9 @@ struct drm_driver {
>  
>   /* List of devices hanging off this driver with stealth attach. */
>   struct list_head legacy_dev_list;
> +
> + /* drmfs parent directory dentry for this driver */
> + struct dentry *drmfs_root;
>  };
>  
>  extern __printf(6, 7)
> -- 
> 2.7.4
> 
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-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH] drm/i915: Fix intel_psr_init() kerneldoc

[Conselvan De Oliveira, Ander]

On Tue, 2016-11-29 at 13:48 +0200, Ander Conselvan de Oliveira wrote:
> In commit c39055b072f8 ("drm/i915: Pass dev_priv to
> intel_setup_outputs()"), I forgot to update the kerneldoc for
> intel_psr_init() init, leading to warnings when building the
> documentation:
> 
> drivers/gpu/drm/i915/intel_psr.c:822: warning: No description found for 
> parameter 'dev_priv'
> drivers/gpu/drm/i915/intel_psr.c:822: warning: Excess function parameter 
> 'dev' description in 'intel_psr_init'
> 
> Fixes: c39055b072f8 ("drm/i915: Pass dev_priv to intel_setup_outputs()")
> Cc: Ander Conselvan de Oliveira 
> Cc: Ville Syrjälä 
> Cc: Daniel Vetter 
> Cc: Jani Nikula 
> Cc: intel-gfx@lists.freedesktop.org
> Signed-off-by: Ander Conselvan de Oliveira 
> 

Pushed with Daniel's irc r-b.

Ander

> ---
>  drivers/gpu/drm/i915/intel_psr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 5c3616e..d5f8d03 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -813,7 +813,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>  
>  /**
>   * intel_psr_init - Init basic PSR work and mutex.
> - * @dev: DRM device
> + * @dev_priv: i915 device private
>   *
>   * This function is  called only once at driver load to initialize basic
>   * PSR stuff.
-
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Re: [Intel-gfx] [RFC 1/3] fs: Introduce drmfs pseudo filesystem interfaces

[Daniel Vetter]

On Thu, Dec 01, 2016 at 01:44:15PM +0530, swati.dhin...@intel.com wrote:
> From: Swati Dhingra 
> 
> The patch introduces a new pseudo filesystem type, named 'drmfs' which is
> intended to house the files for the data generated by drm subsystem that
> cannot be accommodated by any of the existing filesystems.
> The filesystem is modelled on the lines of existing pseudo-filesystems such
> as debugfs/tracefs, and borrows ideas from their implementation.
> This filesystem will be appearing at sys/kernel/drm.
> 
> A new config 'CONFIG_DRMFS' is introduced to enable/disable the filesystem,
> which is dependent on CONFIG_DRM.
> The filesystem will not be registered standalone during kernel init time,
> instead it is intended to be initialized/registered during drm initialization.
> 
> The intent for introduction of the filesystem is to act as a location to hold
> various kinds of data output from Linux DRM subsystems, which can't really fit
> anywhere else into the existing filesystems such as debugfs/sysfs etc. All 
> these
> filesystems have their own constraints and are intended to output a particular
> type of data such as attributes and small debug parameter data. Due to these
> constraints, there is a need for a new pseudo filesytem, customizable to DRM
> specific requirements and catering to the needs to DRM subsystem components
> 
> Signed-off-by: Sourab Gupta 
> Signed-off-by: Swati Dhingra 

I thought review feedback was to put that into drm, not under fs/? Also,
needs proper ccing.
-Daniel

> ---
>  drivers/gpu/drm/drm_drv.c  |   1 +
>  fs/Kconfig |   9 +
>  fs/Makefile|   1 +
>  fs/drmfs/Makefile  |   3 +
>  fs/drmfs/inode.c   | 561 
> +
>  include/linux/drmfs.h  |  56 +
>  include/uapi/linux/magic.h |   3 +
>  7 files changed, 634 insertions(+)
>  create mode 100644 fs/drmfs/Makefile
>  create mode 100644 fs/drmfs/inode.c
>  create mode 100644 include/linux/drmfs.h
> 
> diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
> index 6dbb986..84fcfcb 100644
> --- a/drivers/gpu/drm/drm_drv.c
> +++ b/drivers/gpu/drm/drm_drv.c
> @@ -27,6 +27,7 @@
>   */
>  
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> diff --git a/fs/Kconfig b/fs/Kconfig
> index 4bd03a2..7d0ac20 100644
> --- a/fs/Kconfig
> +++ b/fs/Kconfig
> @@ -200,6 +200,15 @@ config HUGETLBFS
>  config HUGETLB_PAGE
>   def_bool HUGETLBFS
>  
> +config DRMFS
> + bool "Drmfs file system support"
> + depends on DRM
> + help
> +   Drmfs is a pseudo file system for drm subsystem output data.
> +
> +   drmfs is a filesystem to hold miscellaneous output data from drm
> +   subsystems.
> +
>  config ARCH_HAS_GIGANTIC_PAGE
>   bool
>  
> diff --git a/fs/Makefile b/fs/Makefile
> index ed2b632..b34a96e 100644
> --- a/fs/Makefile
> +++ b/fs/Makefile
> @@ -120,6 +120,7 @@ obj-$(CONFIG_BEFS_FS) += befs/
>  obj-$(CONFIG_HOSTFS) += hostfs/
>  obj-$(CONFIG_CACHEFILES) += cachefiles/
>  obj-$(CONFIG_DEBUG_FS)   += debugfs/
> +obj-$(CONFIG_DRMFS)  += drmfs/
>  obj-$(CONFIG_TRACING)+= tracefs/
>  obj-$(CONFIG_OCFS2_FS)   += ocfs2/
>  obj-$(CONFIG_BTRFS_FS)   += btrfs/
> diff --git a/fs/drmfs/Makefile b/fs/drmfs/Makefile
> new file mode 100644
> index 000..ac87e497
> --- /dev/null
> +++ b/fs/drmfs/Makefile
> @@ -0,0 +1,3 @@
> +drmfs-objs   := inode.o
> +
> +obj-$(CONFIG_DRMFS)  += drmfs.o
> diff --git a/fs/drmfs/inode.c b/fs/drmfs/inode.c
> new file mode 100644
> index 000..9220705
> --- /dev/null
> +++ b/fs/drmfs/inode.c
> @@ -0,0 +1,561 @@
> +/*
> + * Copyright © 2014 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + *
> + * 

Re: [Intel-gfx] [RFC 0/3] Introduce drmfs pseudo filesystem for drm subsystem

[Daniel Vetter]

On Thu, Dec 01, 2016 at 01:44:14PM +0530, swati.dhin...@intel.com wrote:
> From: Swati Dhingra 
> 
> Currently, for the purpose of providing output debug/loggging/crc and various
> other kinds of data from DRM layer to userspace, we don't have a standard
> filesystem, which would suffice for all the usecases. The filesystems used
> currently such as debugfs/sysfs have their own constraints and are intended
> to output a particular type of data. For instance, sysfs is suitable for
> exporting only small data in form of attributes, thus not suitable to export
> large data such as error states/logs/crc etc. Likewise for debugfs, which is
> not available in production kernels, and may not be best place to hold certain
> kinds of data. As a result, we currently are creating certain files in these
> filesystems, which are not particularly suited there (For, i915, guc_log is a
> case in point, which is currently created in debugfs, but not particularly
> suited there).
> 
> Due to these constraints, there is a need for a new pseudo filesytem,
> customizable to DRM specific requirements and catering to the needs to DRM
> subsystem components. This will provide a unified location to hold various
> kinds of data from Linux DRM subsystems, for the files which can't really fit
> anywhere else into the existing filesystems.
> 
> In this patch series, we have introduced a pseudo filesystem named as 'drmfs'
> for now. The filesystem is introduced in the first patch, and the subsequent
> patches make use of the filesystem interfaces, in drm driver, and making them
> available for use by the drm subsystem components, one of which is i915.
> We've moved the location of i915 GuC logs from debugfs to drmfs in the third
> patch. Subsequently, more such files such as pipe_crc, error states, memory
> stats, etc. can be move to this filesystem, if the idea introduced here is
> acceptable per se. The filesystem introduced is being used to house the data
> generated by i915 driver in this patch series, but will hopefully be generic
> enough to provide scope for usage by any other drm subsystem component.
> 
> The patch series is being floated as RFC to gather feedback on the idea and
> infrastructure proposed here and it's suitability to address the specific
> problem statement/use case.
> 
> v2: fix the bat failures caused due to missing config check

This needs to be cc'ed to dri-devel for discussion of the drmfs part.
Please cc the entire patch series so that everyone has the full context.
-Daniel

> 
> Swati Dhingra (3):
>   fs: Introduce drmfs pseudo filesystem interfaces
>   drm: Register drmfs filesystem from drm init
>   drm/i915: Creating guc log file in drmfs instead of debugfs
> 
>  drivers/gpu/drm/drm_drv.c  |  23 ++
>  drivers/gpu/drm/i915/i915_guc_submission.c |  31 +-
>  fs/Kconfig |   9 +
>  fs/Makefile|   1 +
>  fs/drmfs/Makefile  |   4 +
>  fs/drmfs/inode.c   | 561 
> +
>  include/drm/drm_drv.h  |   3 +
>  include/linux/drmfs.h  |  56 +++
>  include/uapi/linux/magic.h |   3 +
>  9 files changed, 670 insertions(+), 21 deletions(-)
>  create mode 100644 fs/drmfs/Makefile
>  create mode 100644 fs/drmfs/inode.c
>  create mode 100644 include/linux/drmfs.h
> 
> -- 
> 2.7.4
> 
> ___
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 3/6] drm/i915: rename BROADWATER and CRESTLINE to I965G and I965GM, respectively

[Joonas Lahtinen]

On ke, 2016-11-30 at 17:43 +0200, Jani Nikula wrote:
> Add more consistency to our naming. Pineview remains the outlier. Keep
> using code names for gen5+.
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Joonas Lahtinen 

Regards, Joonas
-- 
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Open Source Technology Center
Intel Corporation
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Re: [Intel-gfx] [RFC 1/3] fs: Introduce drmfs pseudo filesystem interfaces

[sourab gupta]

On Thu, 2016-12-01 at 00:07 -0800, Chris Wilson wrote:
> On Thu, Dec 01, 2016 at 12:32:31PM +0530, swati.dhin...@intel.com wrote:
> > +int drmfs_init(void)
> > +{
> > +   int retval;
> > +
> > +   retval = sysfs_create_mount_point(kernel_kobj, "drm");
> > +   if (retval)
> > +   return -EINVAL;
> > +
> > +   retval = register_filesystem(_fs_type);
> > +   if (!retval)
> > +   drmfs_registered = true;
> > +
> > +   return retval;
> > +}
> > +EXPORT_SYMBOL(drmfs_init);
> > +
> > +int drmfs_fini(void)
> > +{
> > +   int retval;
> > +
> > +   retval = unregister_filesystem(_fs_type);
> > +   if (retval)
> > +   return retval;
> > +
> > +   drmfs_registered = false;
> > +
> > +   sysfs_remove_mount_point(kernel_kobj, "drm");
> > +}
> > +EXPORT_SYMBOL(drmfs_fini);
> 
> This needs to act like a singleton for multiple DRM drivers, i.e.
> add a mutex and use drmfs_registered as a reference count (also then
> don't call the entrypoint init/fini). Or alternatively (and probably
> better?), simply do init/fini from the DRM module init.
> -Chris
> 
Hi Chris,

In the second patch, drmfs_init is called by drm_core_init, which should
thus be called only once (i.e. during drm module init), and likewise for
drmfs_fini which is called during drm_core_exit.
Am I missing something here?



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Re: [Intel-gfx] [PATCH]i915: use WARN_ON_ONCE in intel_dp_aux_transfer

[Dave Young]

On 11/30/16 at 03:25pm, Ville Syrjälä wrote:
> On Thu, Nov 24, 2016 at 05:03:20PM +0800, Dave Young wrote:
> > On 11/24/16 at 10:53am, Jani Nikula wrote:
> > > On Thu, 24 Nov 2016, Dave Young  wrote:
> > > > I see a lot of below warning:
> > > 
> > > No, we must not hide this under the carpet. There's a bug at fdo about
> > > this, and we need to fix it.
> > 
> > It is not hiding it, just not repeating the warnings. But anyway I do
> > not have strong opinion. I'm building my kernel with this patch until
> > there is a real fix in upstream.
> 
> We already have a patch to reduce it a single WARN:
> d4cb3fd9b548 ("drm/i915/dp: add lane_count check in 
> intel_dp_check_link_status")

It works for me, thanks

> 
> Do we need to get that backported to stable?

Personally I think it should but I'm not sure the policy of stable for i915 
though.

Thanks
Dave
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Re: [Intel-gfx] [RFC 1/3] fs: Introduce drmfs pseudo filesystem interfaces

[Chris Wilson]

On Thu, Dec 01, 2016 at 12:32:31PM +0530, swati.dhin...@intel.com wrote:
> +int drmfs_init(void)
> +{
> + int retval;
> +
> + retval = sysfs_create_mount_point(kernel_kobj, "drm");
> + if (retval)
> + return -EINVAL;
> +
> + retval = register_filesystem(_fs_type);
> + if (!retval)
> + drmfs_registered = true;
> +
> + return retval;
> +}
> +EXPORT_SYMBOL(drmfs_init);
> +
> +int drmfs_fini(void)
> +{
> + int retval;
> +
> + retval = unregister_filesystem(_fs_type);
> + if (retval)
> + return retval;
> +
> + drmfs_registered = false;
> +
> + sysfs_remove_mount_point(kernel_kobj, "drm");
> +}
> +EXPORT_SYMBOL(drmfs_fini);

This needs to act like a singleton for multiple DRM drivers, i.e.
add a mutex and use drmfs_registered as a reference count (also then
don't call the entrypoint init/fini). Or alternatively (and probably
better?), simply do init/fini from the DRM module init.
-Chris

-- 
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[Intel-gfx] [RFC 1/3] fs: Introduce drmfs pseudo filesystem interfaces

[swati . dhingra]

From: Swati Dhingra 

The patch introduces a new pseudo filesystem type, named 'drmfs' which is
intended to house the files for the data generated by drm subsystem that
cannot be accommodated by any of the existing filesystems.
The filesystem is modelled on the lines of existing pseudo-filesystems such
as debugfs/tracefs, and borrows ideas from their implementation.
This filesystem will be appearing at sys/kernel/drm.

A new config 'CONFIG_DRMFS' is introduced to enable/disable the filesystem,
which is dependent on CONFIG_DRM.
The filesystem will not be registered standalone during kernel init time,
instead it is intended to be initialized/registered during drm initialization.

The intent for introduction of the filesystem is to act as a location to hold
various kinds of data output from Linux DRM subsystems, which can't really fit
anywhere else into the existing filesystems such as debugfs/sysfs etc. All these
filesystems have their own constraints and are intended to output a particular
type of data such as attributes and small debug parameter data. Due to these
constraints, there is a need for a new pseudo filesytem, customizable to DRM
specific requirements and catering to the needs to DRM subsystem components

Signed-off-by: Sourab Gupta 
Signed-off-by: Swati Dhingra 
---
 drivers/gpu/drm/drm_drv.c  |   1 +
 fs/Kconfig |   9 +
 fs/Makefile|   1 +
 fs/drmfs/Makefile  |   3 +
 fs/drmfs/inode.c   | 561 +
 include/linux/drmfs.h  |  56 +
 include/uapi/linux/magic.h |   3 +
 7 files changed, 634 insertions(+)
 create mode 100644 fs/drmfs/Makefile
 create mode 100644 fs/drmfs/inode.c
 create mode 100644 include/linux/drmfs.h

diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 6dbb986..84fcfcb 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -27,6 +27,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
diff --git a/fs/Kconfig b/fs/Kconfig
index 4bd03a2..7d0ac20 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -200,6 +200,15 @@ config HUGETLBFS
 config HUGETLB_PAGE
def_bool HUGETLBFS
 
+config DRMFS
+   bool "Drmfs file system support"
+   depends on DRM
+   help
+ Drmfs is a pseudo file system for drm subsystem output data.
+
+ drmfs is a filesystem to hold miscellaneous output data from drm
+ subsystems.
+
 config ARCH_HAS_GIGANTIC_PAGE
bool
 
diff --git a/fs/Makefile b/fs/Makefile
index ed2b632..b34a96e 100644
--- a/fs/Makefile
+++ b/fs/Makefile
@@ -120,6 +120,7 @@ obj-$(CONFIG_BEFS_FS)   += befs/
 obj-$(CONFIG_HOSTFS)   += hostfs/
 obj-$(CONFIG_CACHEFILES)   += cachefiles/
 obj-$(CONFIG_DEBUG_FS) += debugfs/
+obj-$(CONFIG_DRMFS)+= drmfs/
 obj-$(CONFIG_TRACING)  += tracefs/
 obj-$(CONFIG_OCFS2_FS) += ocfs2/
 obj-$(CONFIG_BTRFS_FS) += btrfs/
diff --git a/fs/drmfs/Makefile b/fs/drmfs/Makefile
new file mode 100644
index 000..ac87e497
--- /dev/null
+++ b/fs/drmfs/Makefile
@@ -0,0 +1,3 @@
+drmfs-objs := inode.o
+
+obj-$(CONFIG_DRMFS)+= drmfs.o
diff --git a/fs/drmfs/inode.c b/fs/drmfs/inode.c
new file mode 100644
index 000..9220705
--- /dev/null
+++ b/fs/drmfs/inode.c
@@ -0,0 +1,561 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ * Swati Dhingra 
+ * Sourab Gupta 
+ * Akash Goel 
+ */
+
+/*
+ * drmfs is the filesystem used for output of drm subsystem data
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRMFS_DEFAULT_MODE 0700
+
+static struct vfsmount 

[Intel-gfx] [RFC 0/3] Introduce drmfs pseudo filesystem for drm subsystem

[swati . dhingra]

From: Swati Dhingra 

Currently, for the purpose of providing output debug/loggging/crc and various
other kinds of data from DRM layer to userspace, we don't have a standard
filesystem, which would suffice for all the usecases. The filesystems used
currently such as debugfs/sysfs have their own constraints and are intended
to output a particular type of data. For instance, sysfs is suitable for
exporting only small data in form of attributes, thus not suitable to export
large data such as error states/logs/crc etc. Likewise for debugfs, which is
not available in production kernels, and may not be best place to hold certain
kinds of data. As a result, we currently are creating certain files in these
filesystems, which are not particularly suited there (For, i915, guc_log is a
case in point, which is currently created in debugfs, but not particularly
suited there).

Due to these constraints, there is a need for a new pseudo filesytem,
customizable to DRM specific requirements and catering to the needs to DRM
subsystem components. This will provide a unified location to hold various
kinds of data from Linux DRM subsystems, for the files which can't really fit
anywhere else into the existing filesystems.

In this patch series, we have introduced a pseudo filesystem named as 'drmfs'
for now. The filesystem is introduced in the first patch, and the subsequent
patches make use of the filesystem interfaces, in drm driver, and making them
available for use by the drm subsystem components, one of which is i915.
We've moved the location of i915 GuC logs from debugfs to drmfs in the third
patch. Subsequently, more such files such as pipe_crc, error states, memory
stats, etc. can be move to this filesystem, if the idea introduced here is
acceptable per se. The filesystem introduced is being used to house the data
generated by i915 driver in this patch series, but will hopefully be generic
enough to provide scope for usage by any other drm subsystem component.

The patch series is being floated as RFC to gather feedback on the idea and
infrastructure proposed here and it's suitability to address the specific
problem statement/use case.

v2: fix the bat failures caused due to missing config check

Swati Dhingra (3):
  fs: Introduce drmfs pseudo filesystem interfaces
  drm: Register drmfs filesystem from drm init
  drm/i915: Creating guc log file in drmfs instead of debugfs

 drivers/gpu/drm/drm_drv.c  |  23 ++
 drivers/gpu/drm/i915/i915_guc_submission.c |  31 +-
 fs/Kconfig |   9 +
 fs/Makefile|   1 +
 fs/drmfs/Makefile  |   4 +
 fs/drmfs/inode.c   | 561 +
 include/drm/drm_drv.h  |   3 +
 include/linux/drmfs.h  |  56 +++
 include/uapi/linux/magic.h |   3 +
 9 files changed, 670 insertions(+), 21 deletions(-)
 create mode 100644 fs/drmfs/Makefile
 create mode 100644 fs/drmfs/inode.c
 create mode 100644 include/linux/drmfs.h

-- 
2.7.4

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[Intel-gfx] [RFC 2/3] drm: Register drmfs filesystem from drm init

[swati . dhingra]

From: Swati Dhingra 

During drm module initialization, drm_core_init initializes the drmfs
filesystem and register this with kernel. A driver specific directory is created
inside drmfs root, and dentry of this directory is saved for subsequent use
by the driver (e.g. i915). The driver can then create files/directories inside
this root directory directly.
In case of i915 driver, the top directory is created at '/sys/kernel/drm/i915'.

Signed-off-by: Sourab Gupta 
Signed-off-by: Swati Dhingra 
---
 drivers/gpu/drm/drm_drv.c | 22 ++
 include/drm/drm_drv.h |  3 +++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 84fcfcb..ead360bd 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -688,6 +688,14 @@ int drm_dev_register(struct drm_device *dev, unsigned long 
flags)
 {
int ret;
 
+#ifdef CONFIG_DRMFS
+   dev->driver->drmfs_root = drmfs_create_dir(dev->driver->name, NULL);
+   if (IS_ERR(dev->driver->drmfs_root)) {
+   DRM_ERROR("Failed to get drmfs root dentry\n");
+   return PTR_ERR(dev->driver->drmfs_root);
+   }
+#endif
+
mutex_lock(_global_mutex);
 
ret = drm_minor_register(dev, DRM_MINOR_CONTROL);
@@ -758,6 +766,9 @@ void drm_dev_unregister(struct drm_device *dev)
drm_minor_unregister(dev, DRM_MINOR_PRIMARY);
drm_minor_unregister(dev, DRM_MINOR_RENDER);
drm_minor_unregister(dev, DRM_MINOR_CONTROL);
+#ifdef CONFIG_DRMFS
+   drmfs_remove(dev->driver->drmfs_root);
+#endif
 }
 EXPORT_SYMBOL(drm_dev_unregister);
 
@@ -825,6 +836,9 @@ static void drm_core_exit(void)
 {
unregister_chrdev(DRM_MAJOR, "drm");
debugfs_remove(drm_debugfs_root);
+#ifdef CONFIG_DRMFS
+   drmfs_fini();
+#endif
drm_sysfs_destroy();
idr_destroy(_minors_idr);
drm_connector_ida_destroy();
@@ -845,6 +859,14 @@ static int __init drm_core_init(void)
goto error;
}
 
+#ifdef CONFIG_DRMFS
+   ret = drmfs_init();
+   if (ret < 0) {
+   DRM_ERROR("Cannot create DRM FS: %d\n", ret);
+   goto error;
+   }
+#endif
+
drm_debugfs_root = debugfs_create_dir("dri", NULL);
if (!drm_debugfs_root) {
ret = -ENOMEM;
diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h
index aad8bba..34804de 100644
--- a/include/drm/drm_drv.h
+++ b/include/drm/drm_drv.h
@@ -403,6 +403,9 @@ struct drm_driver {
 
/* List of devices hanging off this driver with stealth attach. */
struct list_head legacy_dev_list;
+
+   /* drmfs parent directory dentry for this driver */
+   struct dentry *drmfs_root;
 };
 
 extern __printf(6, 7)
-- 
2.7.4

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[Intel-gfx] [RFC 3/3] drm/i915: Creating guc log file in drmfs instead of debugfs

[swati . dhingra]

From: Swati Dhingra 

In the current scenario, the relay API fit well only with debugfs, due to
availability of parent dentry. Any other existing filesystem was not feasible 
for
holding guc logs, due to incompatibility with relay. But this makes the  guc_log
file unavailable on the production kernels.

GuC log file can therefore be one of candidates for movement to the drmfs
filesystem, which can satisfy all the requirements needed by relay API, and can
house any relayfs based output file.

The patch moves the parent directory of guc 'log_dir' from debugfs_root to
drmfs_root, while using the drmfs api's to create the requisite files.

Signed-off-by: Sourab Gupta 
Signed-off-by: Swati Dhingra 
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 26 +-
 1 file changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c 
b/drivers/gpu/drm/i915/i915_guc_submission.c
index 4462112..cd2e8ed 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -24,6 +24,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include "i915_drv.h"
 #include "intel_guc.h"
@@ -923,7 +924,7 @@ static int subbuf_start_callback(struct rchan_buf *buf,
 }
 
 /*
- * file_create() callback. Creates relay file in debugfs.
+ * file_create() callback. Creates relay file.
  */
 static struct dentry *create_buf_file_callback(const char *filename,
   struct dentry *parent,
@@ -949,17 +950,26 @@ static struct dentry *create_buf_file_callback(const char 
*filename,
 * dentry of the file associated with the channel buffer and that file's
 * name need not be same as the filename passed as an argument.
 */
+#if defined(CONFIG_DRMFS)
+   buf_file = drmfs_create_file("guc_log", mode,
+  parent, buf, _file_operations);
+#else
buf_file = debugfs_create_file("guc_log", mode,
   parent, buf, _file_operations);
+#endif
return buf_file;
 }
 
 /*
- * file_remove() default callback. Removes relay file in debugfs.
+ * file_remove() default callback. Removes relay file.
  */
 static int remove_buf_file_callback(struct dentry *dentry)
 {
+#if defined(CONFIG_DRMFS)
+   drmfs_remove(dentry);
+#else
debugfs_remove(dentry);
+#endif
return 0;
 }
 
@@ -1009,6 +1019,10 @@ static int guc_log_create_relay_file(struct intel_guc 
*guc)
struct dentry *log_dir;
int ret;
 
+#if defined(CONFIG_DRMFS)
+   /* Create the log file in drmfs dir: /sys/kernel/drm/i915/ */
+   log_dir = dev_priv->drm.driver->drmfs_root;
+#else
/* For now create the log file in /sys/kernel/debug/dri/0 dir */
log_dir = dev_priv->drm.primary->debugfs_root;
 
@@ -1021,10 +1035,12 @@ static int guc_log_create_relay_file(struct intel_guc 
*guc)
 *  relay channel.
 * ii)  Should be able to use 'relay_file_operations' fops for the file.
 * iii) Set the 'i_private' field of file's inode to the pointer of
-*  relay channel buffer.
+*  relay channel buffer.
 */
+#endif
+
if (!log_dir) {
-   DRM_ERROR("Debugfs dir not available yet for GuC log file\n");
+   DRM_ERROR("Root dir not available yet for GuC log file\n");
return -ENODEV;
}
 
@@ -1265,7 +1281,7 @@ static int guc_log_create_extras(struct intel_guc *guc)
if (!guc->log.relay_chan) {
/* Create a relay channel, so that we have buffers for storing
 * the GuC firmware logs, the channel will be linked with a file
-* later on when debugfs is registered.
+* later on when debugfs/drmfs is registered.
 */
ret = guc_log_create_relay_channel(guc);
if (ret)
-- 
2.7.4

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Re: [Intel-gfx] drm-intel split-up and new dim script

[Daniel Vetter]

Ok, transition is over, old drm-intel-nightly and rerere-cache is removed.
I hope that's enough of a hint to everyone else who missed the memo ;-)
-Daniel

On Thu, Nov 24, 2016 at 11:48:47AM +0100, Daniel Vetter wrote:
> Hi all,
> 
> So it's finally done, drm-misc is split out into a separate repo:
> 
> https://cgit.freedesktop.org/drm-misc
> 
> The integration tree and rerere-cache was also split out, so that both
> groups can update it:
> 
> https://cgit.freedesktop.org/drm-tip
> 
> To get there you need to update dim and re-run the setup steps:
> 
> 1. Grab latest dim (if you have already, just update the maintainer-tools
> checkout) and store it somewhere temporarily.  2. Delete the old auxiliary
> directories:
> 
> $ cd $DIM_PREFIX $ rm drm-intel-rerere drm-intel-nightly maintainer-tools
> -Rf
> 
> 3. Make sure you have a recent enough git with worktree support. It's not
> required, but if you have one it's automatically used, and it save a pile
> of disk space.
> 
> 4. Re-run
> 
> $ dim setup
> 
> Note that for those who start fresh with dim, there's manpages and
> quickstart guides in dim itself, just run
> 
> $ dim help
> 
> from a checkout of the maintainer-tools branch from
> 
> https://cgit.freedesktop.org/drm-intel
> 
> Or take a look at
> https://01.org/linuxgraphics/gfx-docs/maintainer-tools/drm-intel.html
> 
> For drm-misc the new branch is drm-misc-next, topic/drm-misc is dead
> effective immediate (and I'll ping people on irc who still push patches).
> The other tree that changes is drm-intel-nightly, new drm-tip, and I plan
> to keep both places roughly in sync for at least a week.
> 
> Cheers, Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [RFC 1/3] fs: Introduce drmfs pseudo filesystem interfaces

[Chris Wilson]

On Thu, Dec 01, 2016 at 12:32:31PM +0530, swati.dhin...@intel.com wrote:
> diff --git a/fs/Kconfig b/fs/Kconfig
> index 4bd03a2..7d0ac20 100644
> --- a/fs/Kconfig
> +++ b/fs/Kconfig
> @@ -200,6 +200,15 @@ config HUGETLBFS
>  config HUGETLB_PAGE
>   def_bool HUGETLBFS
>  
> +config DRMFS
> + bool "Drmfs file system support"
> + depends on DRM
> + help
> +   Drmfs is a pseudo file system for drm subsystem output data.
> +
> +   drmfs is a filesystem to hold miscellaneous output data from drm
> +   subsystems.
> +
>  config ARCH_HAS_GIGANTIC_PAGE
>   bool
>  
> diff --git a/fs/Makefile b/fs/Makefile
> index ed2b632..b34a96e 100644
> --- a/fs/Makefile
> +++ b/fs/Makefile
> @@ -120,6 +120,7 @@ obj-$(CONFIG_BEFS_FS) += befs/
>  obj-$(CONFIG_HOSTFS) += hostfs/
>  obj-$(CONFIG_CACHEFILES) += cachefiles/
>  obj-$(CONFIG_DEBUG_FS)   += debugfs/
> +obj-$(CONFIG_DRMFS)  += drmfs/

A filesystem does not have to live under fs/. Since this is dedicated
and tied to the lifetime of drivers/gpu/drm/drm.ko, we will be happier
with not adding a new MAINTAINERS entry.
-Chris

-- 
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Re: [Intel-gfx] [RFC 1/3] fs: Introduce drmfs pseudo filesystem interfaces

[sourab gupta]

On Thu, 2016-12-01 at 00:11 -0800, Chris Wilson wrote:
> On Thu, Dec 01, 2016 at 12:32:31PM +0530, swati.dhin...@intel.com wrote:
> > diff --git a/fs/Kconfig b/fs/Kconfig
> > index 4bd03a2..7d0ac20 100644
> > --- a/fs/Kconfig
> > +++ b/fs/Kconfig
> > @@ -200,6 +200,15 @@ config HUGETLBFS
> >  config HUGETLB_PAGE
> > def_bool HUGETLBFS
> >  
> > +config DRMFS
> > +   bool "Drmfs file system support"
> > +   depends on DRM
> > +   help
> > + Drmfs is a pseudo file system for drm subsystem output data.
> > +
> > + drmfs is a filesystem to hold miscellaneous output data from drm
> > + subsystems.
> > +
> >  config ARCH_HAS_GIGANTIC_PAGE
> > bool
> >  
> > diff --git a/fs/Makefile b/fs/Makefile
> > index ed2b632..b34a96e 100644
> > --- a/fs/Makefile
> > +++ b/fs/Makefile
> > @@ -120,6 +120,7 @@ obj-$(CONFIG_BEFS_FS)   += befs/
> >  obj-$(CONFIG_HOSTFS)   += hostfs/
> >  obj-$(CONFIG_CACHEFILES)   += cachefiles/
> >  obj-$(CONFIG_DEBUG_FS) += debugfs/
> > +obj-$(CONFIG_DRMFS)+= drmfs/
> 
> A filesystem does not have to live under fs/. Since this is dedicated
> and tied to the lifetime of drivers/gpu/drm/drm.ko, we will be happier
> with not adding a new MAINTAINERS entry.
> -Chris
> 
Ok, agreed.
So, should we have the drmfs/ source directory (with its associated
files) under drivers/gpu/drm/?
Can you please suggest where should the associated 'DRMFS' config be
defined? Should drm/Kconfig be a good place?

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