On Tue, May 5, 2015 at 4:33 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
Which brings another point to mind. Should we define a new property type
for color data? Would make it easier to pretty-print in userland.
Using decimal for color data isn't very useful after all.
Maybe a hex
On Tue, 05 May 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com
wrote:
missed the changes attached. so adding rb tag
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
Pardon my stubbornness, and thanks for the review! Pushed to
drm-intel-fixes.
BR,
Jani.
On
On Tue, May 05, 2015 at 06:30:50PM -0300, Paulo Zanoni wrote:
2015-04-07 10:44 GMT-03:00 Daniel Vetter dan...@ffwll.ch:
On Tue, Apr 07, 2015 at 11:12:09AM +0100, Chris Wilson wrote:
On Tue, Apr 07, 2015 at 11:07:07AM +0200, Daniel Vetter wrote:
On Tue, Apr 07, 2015 at 09:36:37AM +0100,
Currently we have race between request-list addition
and hangcheck inspecting that list. It leads to hangcheck
concluding that ring is idle, even if its not.
Demote the error to a info message until the issue with
race is fixed.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89493
On Wed, 06 May 2015, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Apr 30, 2015 at 01:07:33PM +0530, Vandana Kannan wrote:
Changes based on future platform readiness patches related to
HAS_PCH_SPLIT(). Use HAS_GMCH_DISPLAY() instead of HAS_PCH_SPLIT
Signed-off-by: Vandana Kannan
This provides an option to override the value set by VBT
for selecting edp Vswing Pre-emph setting table.
v2: Adding comment about this being a temporary workaround and
making the parameter read-only (Jani)
https://bugs.freedesktop.org/show_bug.cgi?id=89554
Signed-off-by: Sonika Jindal
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
Extend the drm_i915_gem_create structure to add support for
creating Stolen memory backed objects. Added a new flag through
which user can specify the preference to allocate the object from
stolen memory, which if set, an attempt will be
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds support for extending the pread/pwrite functionality
for objects not backed by shmem. The access will be made through
gtt interface.
This will cover prime objects as well as stolen memory backed objects
but for userptr
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds support for clearing buffer objects via blitter
engines. This is particularly useful for clearing out the memory
from stolen region.
v2: Add support for using execlists PPGTT
v3: Fix issues in legacy ringbuffer submission
From: Chris Wilson chris at chris-wilson.co.uk
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough
On Wed, 06 May 2015, Sonika Jindal sonika.jin...@intel.com wrote:
This provides an option to override the value set by VBT
for selecting edp Vswing Pre-emph setting table.
v2: Adding comment about this being a temporary workaround and
making the parameter read-only (Jani)
On 05/05/2015 06:22 PM, Konduru, Chandra wrote:
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Tuesday, May 05, 2015 2:53 AM
To: Intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko; Konduru, Chandra; Wood, Thomas
Subject: [PATCH i-g-t 4/4]
On Thu, Apr 30, 2015 at 04:06:51PM +0100, Michel Thierry wrote:
The patch 69876bed7e008f5fe01538a2d47c09f2862129d0: drm/i915/gen8:
page directories rework allocation added an overflow warning, but the
mask had an extra 0. Use typo-prone option suggested by Dave instead,
I inserted the less
On Wed, May 06, 2015 at 12:40:40PM +0300, Mika Kuoppala wrote:
Currently we have race between request-list addition
and hangcheck inspecting that list. It leads to hangcheck
concluding that ring is idle, even if its not.
Demote the error to a info message until the issue with
race is fixed.
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch series adds support for creating/using Stolen memory backed
objects.
Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory,
Hi Dave,
rc2 is out, time to open drm-next. Bunch of drm_irq.c patches from
Mariome, magic/auth removal from David and a few other oddball things.
Cheers, Daniel
The following changes since commit 2b1193d5287004edfbf89407149a3159656f47f1:
drm: fix trivial typo mistake (2015-04-14 12:41:03
On Tue, May 05, 2015 at 11:57:42AM -0400, Peter Hurley wrote:
On 05/05/2015 11:42 AM, Daniel Vetter wrote:
On Tue, May 05, 2015 at 10:36:24AM -0400, Peter Hurley wrote:
On 05/04/2015 12:52 AM, Mario Kleiner wrote:
On 04/16/2015 03:03 PM, Daniel Vetter wrote:
On Thu, Apr 16, 2015 at
On Tue, May 05, 2015 at 01:12:41PM +0530, Deepak S wrote:
On Monday 04 May 2015 08:58 PM, Ville Syrjälä wrote:
On Mon, May 04, 2015 at 10:12:23AM +0200, Daniel Vetter wrote:
On Mon, May 04, 2015 at 10:58:02AM +0530, Deepak S wrote:
On Wednesday 29 April 2015 02:59 PM, Ville Syrjälä
On Mon, Apr 13, 2015 at 11:26:56AM +0300, Jani Nikula wrote:
Because they can be.
Signed-off-by: Jani Nikula jani.nik...@intel.com
Queued for -next, thanks for the patch.
-Daniel
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Thu, Apr 30, 2015 at 01:54:41PM +0100, Dave Gordon wrote:
On 29/04/15 17:10, yu@intel.com wrote:
From: Alex Dai yu@intel.com
This is to avoid bad IO access caused by writing NOOP to wrap the
ring buffer whilst ring is unpinned.
Signed-off-by: Alex Dai yu@intel.com
On Thu, Apr 30, 2015 at 11:02:31AM +0300, Mika Kuoppala wrote:
Unbinding doesn't always lead to unconditional destruction
of vma. This destruction avoidance happens if vma is part of
execbuffer relocation list or if vma is being considered for
eviction in i915_gem_evict_something().
For
A those typos ...
Signed-off-by: Daniel Vetter daniel.vet...@intel.com
---
lib/intel_mmio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c
index 2fdb2b05de69..b16a35d9f40f 100644
--- a/lib/intel_mmio.c
+++ b/lib/intel_mmio.c
@@ -278,7
On Wed, Apr 29, 2015 at 11:56:41AM +0530, Sivakumar Thulasimani wrote:
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 4/29/2015 11:47 AM, Mika Kahola wrote:
This is a first of series patches that optimize DP link
training. The first patch is for eDP only where we reuse
On Thu, Apr 30, 2015 at 01:07:33PM +0530, Vandana Kannan wrote:
Changes based on future platform readiness patches related to
HAS_PCH_SPLIT(). Use HAS_GMCH_DISPLAY() instead of HAS_PCH_SPLIT
Signed-off-by: Vandana Kannan vandana.kan...@intel.com
Signed-off-by: A.Sunil Kamath
On Mon, May 04, 2015 at 11:40:49PM +, Konduru, Chandra wrote:
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
Vetter
Sent: Monday, May 04, 2015 8:01 AM
To: Konduru, Chandra
Cc: intel-gfx@lists.freedesktop.org; Vetter, Daniel;
On Thu, Apr 30, 2015 at 01:16:30PM +0100, Tvrtko Ursulin wrote:
On 04/30/2015 12:20 PM, Joonas Lahtinen wrote:
@@ -495,7 +503,10 @@ i915_ggtt_view_equal(const struct i915_ggtt_view *a,
if (WARN_ON(!a || !b))
return false;
-return a-type == b-type;
+if (a-type !=
On Tue, 2015-05-05 at 15:08 +0530, Shobhit Kumar wrote:
The Crystalcove PMIC controls PWM signals and this driver exports that
capability as a PWM chip driver. This is platform device implementtaion
of the drivers/mfd cell device for CRC PMIC
v2: Use the existing config callback with duty_ns
On Wed, 06 May 2015, Jindal, Sonika sonika.jin...@intel.com wrote:
On 5/5/2015 7:28 PM, Jani Nikula wrote:
On Tue, 05 May 2015, Damien Lespiau damien.lesp...@intel.com wrote:
On Tue, May 05, 2015 at 02:39:48PM +0300, Jani Nikula wrote:
There's still the question whether we can default to using
On Thu, Apr 30, 2015 at 04:39:23PM +0100, Damien Lespiau wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
On Wed, May 06, 2015 at 12:53:14PM +0200, Daniel Vetter wrote:
On Thu, Apr 30, 2015 at 04:39:22PM +0100, Damien Lespiau wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Why? I.e. way too terse commit message.
Because I couldn't get the PCU to answer to the handcheck we should
On 05/06/2015 12:35 PM, Joonas Lahtinen wrote:
Partial view type allows manipulating parts of huge BOs through the GGTT,
which was not previously possible due to constraint that whole object had
to be mapped for any access to it through GGTT.
v2:
- Retain error value from sg_alloc_table
I merged all the preceding patches to dinq. This one starts to conflict,
since dmc code landed meanwhile.
On Thu, Apr 30, 2015 at 04:39:21PM +0100, Damien Lespiau wrote:
We need to re-init the display hardware when going out of suspend. This
includes:
- Hooking the PCH to the reset logic
On Mon, May 04, 2015 at 05:44:11PM +0300, Mika Kuoppala wrote:
wa_batchbuffer is part of some error states. Make sure it
is freed.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
Queued for -next, thanks for the patch.
-Daniel
---
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
1 file
On Tue, May 05, 2015 at 09:56:02PM +0300, Ville Syrjälä wrote:
On Thu, Apr 30, 2015 at 04:39:21PM +0100, Damien Lespiau wrote:
+static void
+skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int
required_vco)
+{
+ unsigned int min_freq;
+ u32 val;
+
+ /* select
On Thu, Apr 30, 2015 at 04:39:22PM +0100, Damien Lespiau wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
Why? I.e. way too terse commit message.
-Daniel
---
drivers/gpu/drm/i915/intel_display.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
On Tue, May 05, 2015 at 02:33:39PM +0300, Jani Nikula wrote:
On Tue, 05 May 2015, Vandana Kannan vandana.kan...@intel.com wrote:
Enabling BLC on BXT.
Includes register definition, and new functions for BXT.
In BXT, there are 2 sets of registers for BLC. Until there is clarity
about
On Tue, May 05, 2015 at 05:17:32PM +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Use POSTING_READ() in intel_sdvo_write_sdvox() as appropriate.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
Queued for -next, thanks for the patch.
On ti, 2015-05-05 at 15:24 +0100, Nick Hoath wrote:
On 29/04/2015 13:26, Deak, Imre wrote:
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c
On ke, 2015-05-06 at 14:28 +0300, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after the register write has
happened.
Spotted while reviewing
On 05/06/2015 12:36 PM, Joonas Lahtinen wrote:
Use partial view for huge BOs (bigger than half the mappable aperture)
in fault handler so that they can be accessed withough trying to make
room for them by evicting other objects.
v2:
- Only use partial views in the case where early rejection
On Tue, May 05, 2015 at 11:03:28AM +0530, Sivakumar Thulasimani wrote:
Reviewed-by: Sivakumar Thulasimani sivakumar.thulasim...@intel.com
On 5/4/2015 7:50 PM, Jani Nikula wrote:
We should no longer enter the codec enable/disable functions in question
with port A anyway, but to err on the
On ke, 2015-05-06 at 12:20 +0200, Daniel Vetter wrote:
On Thu, Apr 30, 2015 at 01:16:30PM +0100, Tvrtko Ursulin wrote:
On 04/30/2015 12:20 PM, Joonas Lahtinen wrote:
@@ -495,7 +503,10 @@ i915_ggtt_view_equal(const struct i915_ggtt_view *a,
if (WARN_ON(!a || !b))
return
Use pread right after moving out of CPU domain to verify all
writes flushed correctly.
Due to extended usage, add own buffer.
Signed-off-by: Joonas Lahtinen joonas.lahti...@linux.intel.com
---
tests/gem_mmap_gtt.c | 28 +---
1 file changed, 21 insertions(+), 7
Do no expose invalid gmbus pins as i2c devices to userspace.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_i2c.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index
Do no expose invalid gmbus pins as i2c devices to userspace.
Signed-off-by: Jani Nikula jani.nik...@intel.com
---
drivers/gpu/drm/i915/intel_i2c.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index
On Tue, May 05, 2015 at 04:32:12PM +0300, Jani Nikula wrote:
On Tue, 05 May 2015, Sivakumar Thulasimani sivakumar.thulasim...@intel.com
wrote:
two points
1) The eDP spec says Audio is optional so it is allowed to have audio,
but i am yet to come across any eDP panel that supports Audio.
From: Ville Syrjälä ville.syrj...@linux.intel.com
Do a POSTING_READ() between the DBUF_CTL register write and the
udelay() to make sure we really wait after the register write has
happened.
Spotted while reviewing Damien's SKL cdclk patch which had the
POSTING_READ()s.
Cc: Imre Deak
Do not skip special GGTT views when considering whether an object
is pinned or not.
Wrong behaviour was introduced in;
commit ec7adb6ee79c8c9fe64d63ad638a31cd62e55515
Author: Joonas Lahtinen joonas.lahti...@linux.intel.com
Date: Mon Mar 16 14:11:13 2015 +0200
drm/i915: Do not use
Use partial view for huge BOs (bigger than half the mappable aperture)
in fault handler so that they can be accessed withough trying to make
room for them by evicting other objects.
v2:
- Only use partial views in the case where early rejection was
previously done.
- Account variable type
GGTT VMA sizes might be smaller than the whole object size due to
different GGTT views.
v2:
- Separate GGTT view constraint calculations from normal view
constraint calculations (Chris Wilson)
v3:
- Do not bother with debug wording. (Tvrtko Ursulin)
v4:
- Clearer logic for calculating
On to, 2015-04-30 at 13:03 +0100, Tvrtko Ursulin wrote:
On 04/30/2015 12:19 PM, Joonas Lahtinen wrote:
GGTT VMA sizes might be smaller than the whole object size due to
different GGTT views.
v2:
- Separate GGTT view constraint calculations from normal view
constraint calculations
On Tue, May 05, 2015 at 03:04:18PM +0530, Shobhit Kumar wrote:
In case some drivers are unloading, they can remove lookup tables which
they would have registered during their load time to avoid redundant
entries if loaded again
v2: Ccing maintainers
v3: Correct the subject line (Lee jones)
On ke, 2015-05-06 at 14:15 +0100, Chris Wilson wrote:
On Wed, May 06, 2015 at 03:31:10PM +0300, Joonas Lahtinen wrote:
Use pread right after moving out of CPU domain to verify all
writes flushed correctly.
Wrong test, see gem_pread. Adding extra work may have the unintended
On Wed, May 06, 2015 at 02:36:27PM +0100, Damien Lespiau wrote:
Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
masked register. Re-oops.
A wonder if went through 2 people while having roughly a
On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote:
On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote:
The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned. This restriction was added as part of converting the BLT to
use 48-bit addressing.
From: Daniele Ceraolo Spurio daniele.ceraolospu...@intel.com
Using imported objects should not leak i915 vmas (and vms).
In practice this simulates Xorg importing fbcon and leaking (or not) one vma
per Xorg startup cycle.
v2: use low-level ioctl wrappers and bo offset to check the leak (Chris)
On Wed, May 06, 2015 at 02:51:47PM +0300, Imre Deak wrote:
On ti, 2015-05-05 at 15:24 +0100, Nick Hoath wrote:
On 29/04/2015 13:26, Deak, Imre wrote:
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
On 05/06/2015 12:34 PM, Joonas Lahtinen wrote:
Do not skip special GGTT views when considering whether an object
is pinned or not.
Wrong behaviour was introduced in;
commit ec7adb6ee79c8c9fe64d63ad638a31cd62e55515
Author: Joonas Lahtinen joonas.lahti...@linux.intel.com
Date: Mon Mar 16
On Wed, May 06, 2015 at 03:31:10PM +0300, Joonas Lahtinen wrote:
Use pread right after moving out of CPU domain to verify all
writes flushed correctly.
Wrong test, see gem_pread. Adding extra work may have the unintended
side-effects of masking bugs. If you want to mix access modes, call it a
On Wed, May 06, 2015 at 02:04:50PM +0100, Damien Lespiau wrote:
Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
The problem was introduced in the original patch:
commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
Author: Damien Lespiau damien.lesp...@intel.com
On Wed, May 06, 2015 at 04:22:23PM +0300, Joonas Lahtinen wrote:
On ke, 2015-05-06 at 14:15 +0100, Chris Wilson wrote:
On Wed, May 06, 2015 at 03:31:10PM +0300, Joonas Lahtinen wrote:
Use pread right after moving out of CPU domain to verify all
writes flushed correctly.
Wrong
On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote:
The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned. This restriction was added as part of converting the BLT to
use 48-bit addressing.
intel_emit_linear_blit needs to handle blits that are not cacheline
On Wed, May 06, 2015 at 05:35:48PM +0530, Sonika Jindal wrote:
This provides an option to override the value set by VBT
for selecting edp Vswing Pre-emph setting table.
v2: Adding comment about this being a temporary workaround and
making the parameter read-only (Jani)
v3: Changing mode to
On Wed, May 06, 2015 at 04:11:11PM +0300, Jani Nikula wrote:
On Wed, 29 Apr 2015, Shobhit Kumar shobhit.ku...@intel.com wrote:
The CRC (Crystal Cove) PMIC, controls the panel enable and disable
signals for BYT for dsi panels. This is indicated in the VBT fields. Use
that to initialize and
On Thu, Mar 26, 2015 at 02:17:25PM +, Damien Lespiau wrote:
On Wed, Mar 25, 2015 at 07:27:16PM +0200, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Replace the hardcoded 9 with a call to intel_freq_opcode(450).
Signed-off-by: Ville Syrjälä
On Wed, May 06, 2015 at 04:44:13PM +0300, Ville Syrjälä wrote:
On Wed, May 06, 2015 at 02:36:27PM +0100, Damien Lespiau wrote:
Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
Ville noticed that the write was wrong since FF_SLICE_CS_CHICKEN2 is a
masked register.
This patch set aims to make strace more useful when tracing i915 ioctls.
The ioctl type is first checked for being drm and then the driver
backing the opened device is identified by looking at sysfs. Other
drivers than i915 can easily be added.
Only a subset of the i915 ioctls are included. I
This adds a dispatcher for extending drm ioctl debugging info and adds
the i915 ioctls to the xlat framework.
Signed-off-by: Patrik Jakobsson patrik.jakobs...@linux.intel.com
---
Makefile.am | 2 +
defs.h | 2 +
drm.c | 104
Signed-off-by: Patrik Jakobsson patrik.jakobs...@linux.intel.com
---
drm_i915.c | 235 +
xlat/drm_i915_getparams.in | 28 ++
xlat/drm_i915_setparams.in | 4 +
3 files changed, 267 insertions(+)
create mode 100644
On Wed, Apr 29, 2015 at 3:59 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
In case we unload and load a driver module again that is registering a
lookup table, without this it will result in multiple entries. Provide
an option to remove the lookup table on driver unload
v2: Ccing
On Wed, Apr 29, 2015 at 4:00 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
v2: Make the lookup table
On Fri, Apr 24, 2015 at 5:33 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
On some Intel SoC platforms, the panel enable/disable signals are
controlled by CRC PMIC. Add those control as a new GPIO in a lookup
table for gpio-crystalcove chip during CRC driver load
v2: Make the lookup table
On Fri, Apr 24, 2015 at 5:33 PM, Shobhit Kumar shobhit.ku...@intel.com wrote:
The CRC (Crystal Cove) PMIC, controls the panel enable and disable
signals for BYT for dsi panels. This is indicated in the VBT fields. Use
that to initialize and use GPIO based control for these signals.
v2: Use
On Wed, 29 Apr 2015, Shobhit Kumar shobhit.ku...@intel.com wrote:
The CRC (Crystal Cove) PMIC, controls the panel enable and disable
signals for BYT for dsi panels. This is indicated in the VBT fields. Use
that to initialize and use GPIO based control for these signals.
v2: Use the newer
On Wed, 29 Apr 2015, Shobhit Kumar shobhit.ku...@intel.com wrote:
Use the CRC PWM device in intel_panel.c and add new MIPI backlight
specififc callbacks
v2: Modify to use pwm_config callback
CC: Samuel Ortiz sa...@linux.intel.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Alexandre
From: Ankitprasad Sharma ankitprasad.r.sha...@intel.com
This patch adds the testcases for verifying the new extended
gem_create ioctl. By means of this extended ioctl, memory
placement of the GEM object can be specified, i.e. either
shmem or stolen memory.
These testcases include functional tests
On Wed, May 06, 2015 at 12:54:23PM +0200, Daniel Vetter wrote:
On Thu, Apr 30, 2015 at 04:39:23PM +0100, Damien Lespiau wrote:
Signed-off-by: Damien Lespiau damien.lesp...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
Adding Chandra, who's implemented skl scaler code.
-Daniel
On Sat, May 02, 2015 at 10:05:42AM +0900, Sergey Senozhatsky wrote:
Hi,
linux-next 20150501
[1.968953] [drm:check_crtc_state [i915]] *ERROR* mismatch in
scaler_state.scaler_id (expected 0, found -1)
[1.968953]
On Tue, May 05, 2015 at 09:17:29AM +0100, Chris Wilson wrote:
[ 1572.417121] BUG: unable to handle kernel NULL pointer dereference at
(null)
[ 1572.421010] IP: [a00b2514]
ftrace_raw_event_i915_context+0x5d/0x70 [i915]
[ 1572.424970] PGD 1766a3067 PUD 1767a2067 PMD 0
[
Partial view type allows manipulating parts of huge BOs through the GGTT,
which was not previously possible due to constraint that whole object had
to be mapped for any access to it through GGTT.
v2:
- Retain error value from sg_alloc_table (Tvrtko Ursulin)
- Do not zero already zeroed variable
On ti, 2015-05-05 at 10:07 +0100, Tvrtko Ursulin wrote:
On 05/04/2015 12:51 PM, Joonas Lahtinen wrote:
On to, 2015-04-30 at 15:54 +0100, Tvrtko Ursulin wrote:
On 04/30/2015 12:21 PM, Joonas Lahtinen wrote:
Use partial view for huge BOs (bigger than the mappable aperture)
in fault
On Tue, May 05, 2015 at 03:08:36PM +0530, Shobhit Kumar wrote:
The Crystalcove PMIC controls PWM signals and this driver exports that
You say signal_s_ here, but you only expose a single PWM device. Does
the PMIC really control more than one? If it isn't, this should probably
become: controls a
This provides an option to override the value set by VBT
for selecting edp Vswing Pre-emph setting table.
v2: Adding comment about this being a temporary workaround and
making the parameter read-only (Jani)
v3: Changing mode to 0400 instead of 0 (Jani)
On 05/06/2015 12:33 PM, Joonas Lahtinen wrote:
GGTT VMA sizes might be smaller than the whole object size due to
different GGTT views.
v2:
- Separate GGTT view constraint calculations from normal view
constraint calculations (Chris Wilson)
v3:
- Do not bother with debug wording. (Tvrtko
Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
The problem was introduced in the original patch:
commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
Author: Damien Lespiau damien.lesp...@intel.com
Date: Mon Feb 9 19:33:20 2015 +
drm/i915/skl: Implement
On Mon, May 4, 2015 at 7:19 PM, Paulo Zanoni przan...@gmail.com wrote:
It seems the problem is happening because we're now trying 12bpc
instead of 8bpc, and 12bpc is broken for HDMI. In fact, 12bpc was
already broken before this patch, the problem is that this patch is
now trying to use it. It
On ke, 2015-05-06 at 14:29 +0100, Chris Wilson wrote:
On Wed, May 06, 2015 at 04:22:23PM +0300, Joonas Lahtinen wrote:
On ke, 2015-05-06 at 14:15 +0100, Chris Wilson wrote:
On Wed, May 06, 2015 at 03:31:10PM +0300, Joonas Lahtinen wrote:
Use pread right after moving out of CPU
On Wed, 2015-05-06 at 17:01 +0100, Nick Hoath wrote:
On 29/04/2015 14:02, Deak, Imre wrote:
On pe, 2015-04-10 at 13:12 +0100, Nick Hoath wrote:
Signed-off-by: Nick Hoath nicholas.ho...@intel.com
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +
1 file changed, 5 insertions(+)
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Tuesday, May 05, 2015 2:53 AM
To: Intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko; Konduru, Chandra; Wood, Thomas
Subject: [PATCH v2 i-g-t 1/4] igt_kms: Avoid NULL ptr deref when commiting
@@ -1765,14 +1765,6 @@ void igt_plane_set_fb(igt_plane_t *plane, struct
igt_fb *fb)
plane-fb = fb;
/* hack to keep tests working that don't call igt_plane_set_size() */
if (fb) {
- plane-crtc_w = fb-width;
- plane-crtc_h = fb-height;
- } else
On Sun, Dec 21, 2014 at 14:47:58 +, Chris Wilson wrote:
Snapshot 2.99.917 (2014-12-21)
==
3 months drifted by whilst I looked elsewhere for bugs.. The highlight of
bugs fixed here are a couple of workarounds required for Broadwell and
making sure that the
-Original Message-
From: Tvrtko Ursulin [mailto:tvrtko.ursu...@linux.intel.com]
Sent: Wednesday, May 06, 2015 2:29 AM
To: Konduru, Chandra; Intel-gfx@lists.freedesktop.org
Cc: Ursulin, Tvrtko; Wood, Thomas
Subject: Re: [PATCH i-g-t 4/4] kms_plane_scaling: Find the image regardless
diff --git a/lib/igt_kms.c b/lib/igt_kms.c index b5ba273..0665d70 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -1765,9 +1765,7 @@ void igt_plane_set_fb(igt_plane_t *plane, struct
igt_fb *fb)
plane-fb = fb;
/* hack to keep tests working that don't call igt_plane_set_size()
Chris Wilson ch...@chris-wilson.co.uk writes:
On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote:
On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote:
The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned. This restriction was added as part of
On Wednesday, May 06, 2015 08:25:28 PM Mika Kuoppala wrote:
Chris Wilson ch...@chris-wilson.co.uk writes:
On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote:
On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote:
The BLT engine on Gen8+ requires linear surfaces to be
On 5/6/2015 8:35 PM, Jani Nikula wrote:
On Mon, 04 May 2015, Vandana Kannan vandana.kan...@intel.com wrote:
Changes based on future platform readiness patches related to
HAS_PCH_SPLIT(). Use HAS_GMCH_DISPLAY() instead of HAS_PCH_SPLIT.
This needs an update to reflect the patch.
BXT does
Hi,
This error happens when crtc_state in driver not matching with hardware
registers.
On skylake board that I have, I am not able to reproduce the issue.
Can you send the system configuration and steps to reproduce the issue?
Also can you send the full dmesg.log file?
-Chandra
-Original
We never removed the sprite watermark updates from our low-level
foo_update_plane() functions; since our hardware updates happen under
vblank evasion, we're not supposed to be calling potentially sleeping
functions there (since interrupts are disabled). Ensure that we
properly set the
The values that ultimately get passed to
intel_update_sprite_watermarks() are pulled out of the plane state
(which has already been swapped into plane-state) as we update the
plane programming. Drop the function parameters and just pull the
relevant values out of the state structure inside the
Our atomic transaction maintains a bitmask of planes that we need to
update sprite watermarks for once vblank evasion is complete. When we
actually go to make use of that bitmask, we've been comparing against
the plane index rather than the plane mask; we need to update our
comparison to check
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