This initializes power wells within the modeset_init_hw routine.
Testing has shown that this works for both driver load time and for
suspend-resume code paths.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 5 +
drivers/gpu/drm/i915
On 07/04/2012 03:21 PM, Paulo Zanoni wrote:
It looks like the check above could go on a separate commit. The first
commit just moves code around, the second one adds the check.
This patch attempts to reset cpt_pch_enable to what ironlake_pch_enable
was before we added LPT support into it; and
Noticed by Chris Wilson, this got through in the last iteration of the rps
for Haswell patch.
CC: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 07/04/2012 05:35 PM, Daniel Vetter wrote:
On Wed, Jul 04, 2012 at 05:07:39PM -0300, Paulo Zanoni wrote:
2012/6/28 Eugeni Dodonov eugeni.dodo...@intel.com:
This is necessary for the modesetting to work correctly after a
suspend-resume cycle. Without this, the pipes and clocks got the correct
This is required for a stable FDI connection.
v2: fix and simplify the FDI_RX_MISC bits as noticed by Paulo Zanoni.
CC: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ddi.c | 9
On 07/04/2012 02:41 PM, Paulo Zanoni wrote:
2012/6/28 Eugeni Dodonov eugeni.dodo...@intel.com:
This pollutes dmesg output even if we do not have FBC for the device, so
move the DRM_DEBUG_KMS statement lower.
v2: just kill the message as suggested by Daniel.
Signed-off-by: Eugeni Dodonov
On 07/03/12 17:24, Daniel Vetter wrote:
On Mon, Jul 02, 2012 at 11:51:09AM -0300, Eugeni Dodonov wrote:
This is based on Ivy Bridge clock gating for now, but is subject to
changes in the future.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
This copy of presumeably the ivb clock
- move all those changes into intel_pm module to leave i915_drv cleaner
Eugeni
Chris Wilson (2):
drm/i915: Group the GT routines together in both code and vtable
drm/i915: Implement w/a for sporadic read failures on waking from rc6
Eugeni Dodonov (8):
drm/i915: support Haswell force waking
-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 101 ++-
drivers/gpu/drm/i915/i915_drv.h | 17 +++---
drivers/gpu/drm/i915
There is a different ACK register for force wake on Haswell, so account
for that.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 22 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 4 deletions
thresholds, but those are ignored on Haswell.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 37 +
2 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm
* use wait_for_atomic for polling.
References: https://bugs.freedesktop.org/show_bug.cgi?id=50243
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 22 ++
drivers/gpu/drm/i915
Just a cosmetic change to simplify the if statement.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index
It should be working so let's turn it on by default and catch any possible
issues faster.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers
We weren't disabling RC6 bits when bringing down RPS.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b00df1f..5ea8319 100644
This is based on Ivy Bridge clock gating for now, but is subject to
changes in the future.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 54 -
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git
For Haswell, on some of the early hardware revisions, it is possible to
run into issues when RC6 state is enabled and when pipes change state.
v2: add comment saying that this is for early revisions only.
v3: beautify as suggested by Daniel Vetter.
Signed-off-by: Eugeni Dodonov eugeni.dodo
This commit moves force wake support routines into intel_pm modules, and
exports the gen6_gt_check_fifodbg routine (used in I915_READ).
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 191 ---
drivers/gpu/drm/i915
On 07/02/2012 02:49 PM, Ben Widawsky wrote:
On Mon, 2 Jul 2012 11:51:05 -0300
Eugeni Dodonov eugeni.dodo...@intel.com wrote:
Most of the RPS and RC6 enabling functionality is similar to what we had
on Gen6/Gen7, so we preserve most of the registers.
Note that Haswell only has RC6, so
On Haswell, there is a different register for reading force wake ACKs.
v2: simplify forcewake dance and therefore the commit message as suggested by
Daniel Vetter.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 10 --
drivers/gpu/drm/i915
We weren't disabling RC6 bits when bringing down RPS.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cf4dd16..64c02bc 100644
This is based on Ivy Bridge clock gating for now, but is subject to
changes in the future.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 54 -
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git
For Haswell, on some of the early hardware revisions, it is possible to
run into issues when RC6 state is enabled and when pipes change state.
v2: add comment saying that this is for early revisions only.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h
at the end of the series
Chris Wilson (2):
drm/i915: Group the GT routines together in both code and vtable
drm/i915: Implement w/a for sporadic read failures on waking from rc6
Eugeni Dodonov (7):
drm/i915: support Haswell force waking
drm/i915: add RPS configuration for Haswell
drm
There is a different ACK register for force wake on Haswell, so account
for that.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 11 +--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git
: https://bugs.freedesktop.org/show_bug.cgi?id=50243
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 22 ++
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 26 insertions
According to the latest documentation, this additional bit is not needed
anymore.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915
This is based on Ivy Bridge clock gating for now, but is subject to
changes in the future.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 54 -
1 file changed, 53 insertions(+), 1 deletion(-)
diff --git
For Haswell, on some of the early hardware revisions, it is possible to
run into issues when RC6 state is enabled and when pipes change state.
v2: add comment saying that this is for early revisions only.
v3: beautify as suggested by Daniel Vetter.
Signed-off-by: Eugeni Dodonov eugeni.dodo
This moves the force wake support routines into intel_pm and exports the
gen6_gt_check_fifodbg routine as we also need it for I915_READ calls.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 184 ---
drivers/gpu
indeed, so use it on Haswell as well.
v3: further simplify the rps sequence for Haswell.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 77 ++---
2 files changed, 51
We weren't disabling RC6 bits when bringing down RPS.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 40837d8..e3ac748 100644
-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 101 ++-
drivers/gpu/drm/i915/i915_drv.h | 17 +++---
drivers/gpu/drm/i915
* use wait_for_atomic for polling.
References: https://bugs.freedesktop.org/show_bug.cgi?id=50243
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 22 ++
drivers/gpu/drm/i915
This moves the force wake support routines into intel_pm and exports the
gen6_gt_check_fifodbg routine as we also need it for I915_READ calls.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 184 ---
drivers/gpu
There is a different ACK register for force wake on Haswell, so account
for that.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915
ironlake RC6 directly instead?
Something like
intel_disable_gt_powersave(struct drm_device *dev, bool teardown_context);
maybe?
Apart from that,
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
Eugeni
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Intel-gfx
on
IVB should be available on HSW - and if they don't work it is probably a bug,
so please let me know about it.
As usual, bikesheds, comments and suggestions are highly welcome :).
Eugeni
Eugeni Dodonov (10):
drm/i915: re-initialize DDI buffer translations after resume
drm/i915: simplify FDI
and pre-emphashis values. This
is now done for DDI_BUF_CTL which now has common bits indicating a
combination of voltage and pre-emphasis values
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
Reviewed-by: Eugeni Dodonov eugeni.dodo
From: Shobhit Kumar shobhit.ku...@intel.com
In Haswell while disabling a pipe, we need to disable the DDI control as
well along with the PIPECONF. Otherwise we will hit assertions during crtc
disable
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo
on DDIC.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm
On LPT onwards, there is only one FDI receiver, but any pipe can drive it.
For now, we consider that only pipeA can work in CRT mode, so if any other
pipe attempts to enable FDI receiver it is considered invalid behavior.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm
CPT/PPT and LPT have different functionality. So we introduce specific
functions to handle each of them instead of using multiple if..
statements.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 70
1 file
This is necessary for the modesetting to work correctly after a
suspend-resume cycle. Without this, the pipes and clocks got the correct
configuration, but the underlying DDI buffers configuration was lost.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915
This is required for a stable FDI connection.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_ddi.c | 10 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm
the queue.
So we properly check those bits as well, to ensure we won't end up in
half-woken situation.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 36 +++-
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm
Split Haswell-specific GT algorithms into its own function.
Note that Haswell only has RC6, so account for that as well.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 160
From: Shobhit Kumar shobhit.ku...@intel.com
PIPE EDP registers and timing registers are different for EDP on HSW
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Sateesh Kavuri sateesh.kav...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm
From: Shobhit Kumar shobhit.ku...@intel.com
v2: simplify horizontal and vertical timings calculations
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Sateesh Kavuri sateesh.kav...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915
From: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Shobhit Kumar shobhit.ku...@intel.com
Signed-off-by: Sateesh Kavuri sateesh.kav...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_ddi.c | 3 +--
drivers/gpu/drm/i915/intel_dp.c | 1 +
2
From: Paulo Zanoni paulo.r.zan...@intel.com
Looks like a copy/paste error.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
For Haswell, on some of the early hardware revisions, it is possible to
run into issues when RC6 state is enabled and when pipes change state.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/intel_pm.c | 9 +
2
+
gtt
stuff to drm/i915 and implementing some neat new cool things.
As usual, flamesbikesheds highly welcome.
I cannot think on a less invasive way to do so, so, for the series:
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
With just one tiny bikeshed on patch2.
Eugeni
On 06/24/2012 03:51 PM, Daniel Vetter wrote:
+ /* Only enable AGP support for gen 3. */
+ if (intel_info-gen != 3) {
+ driver.driver_features =
+ ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
+ } else if (!intel_agp_enabled) {
+
as static and hide them in
intel_pm.c
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
I have very similar patch for this as well (for HSW patches to come
somewhat later this week), you beat me on sending it by a few days. So:
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
Just one
consistent.
Originally this was prep work for future patches, but I've chased down
a totally wrong alley. Still, I think this is a sensible
clarification.
Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
Eugeni
(Ben)
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
(Assuming I haven't checked all the magic register values but I trust
that they work):
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
Eugeni
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Intel-gfx
On 06/24/2012 07:01 AM, Daniel Vetter wrote:
On Fri, Jun 22, 2012 at 07:04:29PM -0700, Ben Widawsky wrote:
On Wed, 20 Jun 2012 14:48:58 -0700
Jesse Barnes jbar...@virtuousgeek.org wrote:
+static struct attribute *gt_attrs[] = {
+ dev_attr_gt_energy_uJ.attr,
+ NULL,
+};
I think
Hi folks,
Intel Open Source HD Graphics Programmer's Reference Manuals (PRMs)
for 2012 Intel Core Processor Family (codenamed Ivy Bridge) are now
available at http://intellinuxgraphics.org/documentation.html.
Have fun :).
--
Eugeni Dodonov
http://eugeni.dodonov.net
On 06/20/2012 12:59 PM, Daniel Vetter wrote:
On Wed, Jun 20, 2012 at 5:53 PM, Chris Wilson ch...@chris-wilson.co.uk
wrote:
On Wed, 20 Jun 2012 08:32:59 -0700, Jesse Barnes jbar...@virtuousgeek.org
wrote:
On Wed, 20 Jun 2012 09:38:25 +0200
Daniel Vetter dan...@ffwll.ch wrote:
And from the
doesn't need them (Eugeni)
References: https://bugs.freedesktop.org/show_bug.cgi?id=50251
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Better late than never :):
For the series:
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
Eugeni
We should not hit this under any sane conditions, but still, this does not
looks right.
CC: Chris Wilson ch...@chris-wilson.co.uk
CC: Daniel Vetter daniel.vet...@ffwll.ch
CC: sta...@vger.kernel.org
Reported-by: Herton Ronaldo Krzesinski herton.krzesin...@canonical.com
Signed-off-by: Eugeni
weird reason intellinuxgraphics.org sometimes lists
its pages as unchanged if you have it in your cache. So if it still shows
Keith's repo there, just reload it with shift-reload :).
--
Eugeni Dodonov
http://eugeni.dodonov.net/
___
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On 06/13/2012 04:47 PM, Chris Wilson wrote:
On Wed, 13 Jun 2012 12:07:19 -0700, Ben Widawsky b...@bwidawsk.net wrote:
On Wed, 13 Jun 2012 18:29:51 +0100
Chris Wilson ch...@chris-wilson.co.uk wrote:
Tidy up the routines for interacting with the GT (in particular the
forcewake dance) which are
-wilson.co.uk
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
I think that this patch could solve some of the RC6-related issues which
are still out there. So the ones of you affected by random GPU hangs or
dropped writes, could you please give this patch a try?
Eugeni
On 06/12/2012 11:35 AM, Paulo Zanoni wrote:
My crystal ball tells me a check for IS_HASWELL_OR_NEWER would prevent
more changes to this code in the future.
I think that a .has_ddi (or similar) flag would be better than checking
for post-Haswell variants, as not necessarily all of them could
*/
reg = DDI_FUNC_CTL(pipe);
val = I915_READ(reg);
cur_state = !!(val PIPE_DDI_FUNC_ENABLE);
...
I missed this in the initial enabling and Shobhit has catched this - thanks!
So you can also add:
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
For this patch
Somehow this went unnoticed in the past reviews, but the condition would
never timeout properly.
This was initially introduced in the v2 of original SBI enabling patch.
Highly embarrassing.
Reported-by: Dan Carpenter dan.carpen...@oracle.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
Somehow this went unnoticed in the past reviews, but the condition would
never timeout properly.
This was initially introduced in the v2 of original SBI enabling patch.
Highly embarrassing.
Reported-by: Dan Carpenter dan.carpen...@oracle.com
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
Prevent possible uninitialized return value from intel_sbi_read call.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm
This seems to come on Gigabyte H55M-S2V and was discovered through the
https://bugs.freedesktop.org/show_bug.cgi?id=50381 debugging.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50381
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/char/agp/intel-agp.c |1
This seems to come on Gigabyte H55M-S2V and was discovered through the
https://bugs.freedesktop.org/show_bug.cgi?id=50381 debugging.
CC: sta...@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50381
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/char/agp
...
Signed-off-by: Adam Jackson a...@redhat.com
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
For the record and for future enabling efforts, for LPT, bits 28-31 and
1-14 are gone since CPT/PPT (e.g., those must be zero). And there is the
bit 15 as a new addition, but we are not using
),
without this patch the flip_test hangs when running on 3rd pipe, and
with this patch it proceeds and finishes correctly.
So this patch fixes this test case, and as far I can see it is correct.
Tested-by: Eugeni Dodonov eugeni.dodo...@intel.com
Eugeni
On 06/05/2012 03:52 PM, Eugeni Dodonov wrote:
On 06/05/2012 05:56 AM, Daniel Vetter wrote:
On Wed, May 23, 2012 at 02:02:00PM +0200, Daniel Vetter wrote:
Or at least plug another gapping hole. Apparrently hw desingers only
moved the bit field, but did not bother ot re-enumerate the planes
when
nice! Just one very tiny bikeshed below :).
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
@@ -285,6 +285,7 @@ struct intel_device_info {
u8 is_ivybridge:1;
u8 is_valleyview:1;
u8 has_pch_split:1;
+ u8 has_force_wake:1;
u8 is_haswell:1;
u8
the ironlake specific code.
Cc: Eugeni Dodonoveugeni.dodo...@intel.com
Signed-Off-by: Daniel Vetterdaniel.vet...@ffwll.ch
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
The code newer got called anyway since the last patch, so let's put it
to rest
.
Cc: sta...@vger.kernel.org.
Tested-by: Joe Bloggsian joebloggs...@gmail.com
Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
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= val / 50;
I guess the comment here is meant to say that turbo won't go below the set
value.
But other than that,
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
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itself:
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
(But I haven't tested it myself as I don't have such a machine).
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contains the right libdrm directory? I915_EXEC_GEN7_SOL_RESET should be
defined in /usr/include/libdrm/i915_drm.h.
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On Mon, May 14, 2012 at 5:12 PM, Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Both the control and data registers are completely different now.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
Both patches are:
Reviewed-by: Eugeni Dodonov
Class 0300: 8086:0be2
So, is it something that has been addressed already of is it a bug?
This is a different Cedartrail GPU, which should be supported by the gma500
kernel driver. It is not supported by the i915 one, sorry.
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and such), no?
But other than that, very nice!
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
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used only to retrieve struct intel_crtc
Signed-off-by: Paulo Zanonipaulo.r.zan...@intel.com
Except for the comments I had on the other patch:
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
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On 05/11/2012 05:54 PM, Ben Widawsky wrote:
Wait request is poorly named IMO. After working with these functions for
some time, I feel it's much clearer to name the functions more
appropriately.
Of course we must update the callers to use the new name as well.
This leaves room within our
On 05/11/2012 05:54 PM, Ben Widawsky wrote:
@@ -1800,6 +1800,7 @@ struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs,
DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey,
a couple of warnings (Ben)
Signed-off-by: Ben Widawskyb...@bwidawsk.net
I couldn't find much to bikeshed here except for question on patch 3 and
one small typo on Patch 4. So for the series:
Reviewed-by: Eugeni Dodonov eugeni.dodo...@intel.com
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message, proper support will
be added via a patch from Paulo Zanoni later.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 36
drivers/gpu/drm/i915/intel_hdmi.c | 19 +++
2 files changed, 55
On 05/10/2012 11:48 AM, Daniel Vetter wrote:
On Wed, May 09, 2012 at 08:29:57PM -0300, Eugeni Dodonov wrote:
This attempts to enable all the available power wells during the
initialization.
Those power wells can be enabled in parallel or on-demand, and disabled
when no longer needed
merged to drm-intel-next, for wider testing and
availability!
Thanks,
Eugeni Dodonov (25):
drm/i915: add new Haswell DIP controls registers
drm/i915: reuse Ivy Bridge interrupts code for Haswell
drm/i915: add support for SBI ops
drm/i915: calculate watermarks for devices that have 3 pipes
Haswell has different DIP control registers and offsets which we need to
use for infoframes, which this patch adds.
Note that this does not adds full DIP frames support, but only the basic
functionality necessary for HDMI to work in early enablement.
Signed-off-by: Eugeni Dodonov eugeni.dodo
Haswell interrupts are mostly similar with Ivy Bridge, so we share same
routines with it.
This patch also simplifies the vblank counter handling for all the Gen5+
architectures.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 11 +--
1 file
: decrease paranoia a bit, as noticed by Chris Wilson
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 63 ++
1
This adds proper support for calculating those watermarks, checking for
number of available pipes instead of specific GPU variants when deciding
if watermarks for 3rd pipe are necessary.
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
: Daniel Vetter daniel.vet...@ffwll.ch
CC: Chris Wilson ch...@chris-wilson.co.uk
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 14 --
1 file changed, 4 insertions(+), 10 deletions
This will throw a BUG() message when an unknown sdvox register is
given to intel_hdmi_init. When this happens, things could going to be pretty
much broken afterwards, so we better detect this as soon as possible.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915
that
things could go wrong.
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index f809d6a..96933cc
a considerable rework of our display handling, so we just leave them all
enabled when the driver is loaded for now.
v2: use more generic and future-proof code
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_pm.c | 36
1 file
This should be already configured when FDI auto-negotiation is done.
Reviewed-by: Rodrigo Vivi rodrigo.v...@gmail.com
Reviewed-by: Jesse Barnes jbar...@virtuousgeek.org
Signed-off-by: Eugeni Dodonov eugeni.dodo...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |3 ++-
1 file changed, 2
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