[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/2] drm/i915/perf: store the associated engine of a stream

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [CI,1/2] drm/i915/perf: store the associated engine of a stream URL : https://patchwork.freedesktop.org/series/67857/ State : success == Summary == CI Bug Log - changes from CI_DRM_7056_full -> Patchwork_14753_full

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly

2019-10-11 Thread Martin Peres
On 10/10/2019 23:18, Patchwork wrote: > == Series Details == > > Series: series starting with [1/4] drm/i915/display: Handle fused off display > correctly > URL : https://patchwork.freedesktop.org/series/67872/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7058 ->

Re: [Intel-gfx] [RFC PATCH] iommu/vt-d: Fix IOMMU field not populated on device hot re-plug

2019-10-11 Thread Lu Baolu
Hi Janusz, On 9/3/19 3:41 PM, Janusz Krzysztofik wrote: Hi Baolu, On Tuesday, September 3, 2019 3:29:40 AM CEST Lu Baolu wrote: Hi Janusz, On 9/2/19 4:37 PM, Janusz Krzysztofik wrote: I am not saying that keeping data is not acceptable. I just want to check whether there are any other

[Intel-gfx] [PATCH i-g-t] i915: Use O_NONBLOCK for faster ringsize probing

2019-10-11 Thread Chris Wilson
When the kernel supports O_NONBLOCK reporting of a full execbuf queue, take advantage of that to immediately report when the output would block due to the ring being full. Signed-off-by: Chris Wilson --- lib/i915/gem_ring.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-)

Re: [Intel-gfx] [PATCH 01/10] drm/i915: Note the addition of timeslicing to the pretend scheduler

2019-10-11 Thread Tvrtko Ursulin
On 10/10/2019 08:14, Chris Wilson wrote: Since writing the comment that the scheduler is entirely passive, we've added minimal timeslicing which adds the most primitive of active elements (a timeout and reschedule). Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Ramalingam C ---

[Intel-gfx] [PATCH V3 0/7] mdev based hardware virtio offloading support

2019-10-11 Thread Jason Wang
Hi all: There are hardware that can do virtio datapath offloading while having its own control path. This path tries to implement a mdev based unified API to support using kernel virtio driver to drive those devices. This is done by introducing a new mdev transport for virtio (virtio_mdev) and

[Intel-gfx] [PATCH V3 6/7] virtio: introduce a mdev based transport

2019-10-11 Thread Jason Wang
This patch introduces a new mdev transport for virtio. This is used to use kernel virtio driver to drive the mediated device that is capable of populating virtqueue directly. A new virtio-mdev driver will be registered to the mdev bus, when a new virtio-mdev device is probed, it will register the

Re: [Intel-gfx] [PATCH] drm/i915: Honour O_NONBLOCK before throttling execbuf submissions

2019-10-11 Thread Tvrtko Ursulin
On 10/10/2019 14:48, Chris Wilson wrote: Check the user's flags on the struct file before deciding whether or not to stall before submitting a request. This allows us to reasonably cheaply honour O_NONBLOCK without checking at more critical phases during request submission. Suggested-by:

Re: [Intel-gfx] [PATCH 03/10] drm/i915: Expose engine properties via sysfs

2019-10-11 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-10-11 09:44:16) > > On 10/10/2019 08:14, Chris Wilson wrote: > > Preliminary stub to add engines underneath /sys/class/drm/cardN/, so > > that we can expose properties on each engine to the sysadmin. > > > > To start with we have basic analogues of the i915_query

[Intel-gfx] [PATCH V3 1/7] mdev: class id support

2019-10-11 Thread Jason Wang
Mdev bus only supports vfio driver right now, so it doesn't implement match method. But in the future, we may add drivers other than vfio, the first driver could be virtio-mdev. This means we need to add device class id support in bus match method to pair the mdev device and mdev driver correctly.

[Intel-gfx] [PATCH V3 3/7] modpost: add support for mdev class id

2019-10-11 Thread Jason Wang
Add support to parse mdev class id table. Signed-off-by: Jason Wang --- drivers/vfio/mdev/vfio_mdev.c | 2 ++ scripts/mod/devicetable-offsets.c | 3 +++ scripts/mod/file2alias.c | 10 ++ 3 files changed, 15 insertions(+) diff --git a/drivers/vfio/mdev/vfio_mdev.c

[Intel-gfx] [PATCH V3 2/7] mdev: bus uevent support

2019-10-11 Thread Jason Wang
This patch adds bus uevent support for mdev bus in order to allow cooperation with userspace. Signed-off-by: Jason Wang --- drivers/vfio/mdev/mdev_driver.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/vfio/mdev/mdev_driver.c b/drivers/vfio/mdev/mdev_driver.c index

[Intel-gfx] [PATCH V3 5/7] mdev: introduce virtio device and its device ops

2019-10-11 Thread Jason Wang
This patch implements basic support for mdev driver that supports virtio transport for kernel virtio driver. Signed-off-by: Jason Wang --- include/linux/mdev.h| 1 + include/linux/virtio_mdev.h | 148 2 files changed, 149 insertions(+) create mode

[Intel-gfx] [PATCH V3 4/7] mdev: introduce device specific ops

2019-10-11 Thread Jason Wang
Currently, except for the create and remove, the rest of mdev_parent_ops is designed for vfio-mdev driver only and may not help for kernel mdev driver. With the help of class id, this patch introduces device specific callbacks inside mdev_device structure. This allows different set of callback to

Re: [Intel-gfx] [PATCH] drm/i915: Honour O_NONBLOCK before throttling execbuf submissions

2019-10-11 Thread Tvrtko Ursulin
On 10/10/2019 14:58, Chris Wilson wrote: Quoting Chris Wilson (2019-10-10 14:48:49) Check the user's flags on the struct file before deciding whether or not to stall before submitting a request. This allows us to reasonably cheaply honour O_NONBLOCK without checking at more critical phases

[Intel-gfx] [PATCH V3 7/7] docs: sample driver to demonstrate how to implement virtio-mdev framework

2019-10-11 Thread Jason Wang
This sample driver creates mdev device that simulate virtio net device over virtio mdev transport. The device is implemented through vringh and workqueue. A device specific dma ops is to make sure HVA is used directly as the IOVA. This should be sufficient for kernel virtio driver to work. Only

Re: [Intel-gfx] [PATCH i-g-t] i915: Use O_NONBLOCK for faster ringsize probing

2019-10-11 Thread Tvrtko Ursulin
On 11/10/2019 09:06, Chris Wilson wrote: When the kernel supports O_NONBLOCK reporting of a full execbuf queue, take advantage of that to immediately report when the output would block due to the ring being full. Signed-off-by: Chris Wilson --- lib/i915/gem_ring.c | 13 ++--- 1

Re: [Intel-gfx] [PATCH] drm/i915: Honour O_NONBLOCK before throttling execbuf submissions

2019-10-11 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-10-11 09:20:12) > > On 10/10/2019 14:58, Chris Wilson wrote: > > Quoting Chris Wilson (2019-10-10 14:48:49) > >> Check the user's flags on the struct file before deciding whether or not > >> to stall before submitting a request. This allows us to reasonably > >>

Re: [Intel-gfx] [PATCH 02/10] drm/i915/execlists: Leave tell-tales as to why pending[] is bad

2019-10-11 Thread Tvrtko Ursulin
On 10/10/2019 08:14, Chris Wilson wrote: Before we BUG out with bad pending state, leave a telltale as to which test failed. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_lrc.c | 30 -

Re: [Intel-gfx] [PATCH 03/10] drm/i915: Expose engine properties via sysfs

2019-10-11 Thread Tvrtko Ursulin
On 10/10/2019 08:14, Chris Wilson wrote: Preliminary stub to add engines underneath /sys/class/drm/cardN/, so that we can expose properties on each engine to the sysadmin. To start with we have basic analogues of the i915_query ioctl so that we can pretty print engine discovery from the shell,

Re: [Intel-gfx] [PATCH 05/10] drm/i915: Mark up "sentinel" requests

2019-10-11 Thread Tvrtko Ursulin
On 10/10/2019 08:14, Chris Wilson wrote: Sometimes we want to emit a terminator request, a request that flushes the pipeline and allows no request to come after it. This can be used for a "preempt-to-idle" to ensure that upon processing the context-switch to that request, all other active

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/selftests: Check known register values within the context

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [1/2] drm/i915/selftests: Check known register values within the context URL : https://patchwork.freedesktop.org/series/67862/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7057_full -> Patchwork_14754_full

Re: [Intel-gfx] [PATCH 03/10] drm/i915: Expose engine properties via sysfs

2019-10-11 Thread Tvrtko Ursulin
On 11/10/2019 09:49, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-10-11 09:44:16) On 10/10/2019 08:14, Chris Wilson wrote: Preliminary stub to add engines underneath /sys/class/drm/cardN/, so that we can expose properties on each engine to the sysadmin. To start with we have basic

Re: [Intel-gfx] [PATCH 06/10] drm/i915/gt: Introduce barrier pulses along engines

2019-10-11 Thread Tvrtko Ursulin
On 10/10/2019 08:14, Chris Wilson wrote: To flush idle barriers, and even inflight requests, we want to send a preemptive 'pulse' along an engine. We use a no-op request along the pinned kernel_context at high priority so that it should run or else kick off the stuck requests. We can use this

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for mdev based hardware virtio offloading support (rev4)

2019-10-11 Thread Patchwork
== Series Details == Series: mdev based hardware virtio offloading support (rev4) URL : https://patchwork.freedesktop.org/series/66989/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1c00a9513524 mdev: class id support ca514b262666 mdev: bus uevent support 136343b6a2ec modpost:

Re: [Intel-gfx] [PATCH 09/10] drm/i915: Replace hangcheck by heartbeats

2019-10-11 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-10-11 15:24:21) > > On 10/10/2019 08:14, Chris Wilson wrote: > > +config DRM_I915_HEARTBEAT_INTERVAL > > + int "Interval between heartbeat pulses (ms)" > > + default 2500 # milliseconds > > + help > > + While active the driver uses a periodic

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate URL : https://patchwork.freedesktop.org/series/67912/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9438571a7abe drm/i915/tgl: Include ro parts of l3 to invalidate -:21:

Re: [Intel-gfx] [PATCH] drm/i915/ehl: Port C's hotplug interrupt is associated with TC1 bits

2019-10-11 Thread Souza, Jose
On Thu, 2019-10-10 at 17:26 -0700, Vivek Kasireddy wrote: > On some platforms that have the MCC PCH, Port C's hotplug interrupt Some? > bits are mapped to TC1 bits. > > Suggested-by: Matt Roper > Signed-off-by: Vivek Kasireddy > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ >

Re: [Intel-gfx] [PATCH 1/7] drm/i915: simplify setting of ddi_io_power_domain

2019-10-11 Thread Souza, Jose
On Thu, 2019-10-10 at 18:09 -0700, Lucas De Marchi wrote: > Instead of the ever growing switch, just compute the ddi io power > domain > based on the port number. Reviewed-by: José Roberto de Souza > > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 43

Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate

2019-10-11 Thread Chris Wilson
Quoting Mika Kuoppala (2019-10-11 14:39:09) > Aim for completeness and invalidate also the ro parts > in l3 cache. This might allow to get rid of the preparser > disable/enable workaround on invalidation path. > > Cc: Chris Wilson > Signed-off-by: Mika Kuoppala > --- >

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Serialise write to scratch with its vma binding

2019-10-11 Thread Matthew Auld
On Fri, 11 Oct 2019 at 20:36, Chris Wilson wrote: > > Add the missing serialisation on the request for a write into a vma to > wait until that vma is bound before being executed by the GPU. > > Signed-off-by: Chris Wilson > Cc: Matthew Auld Reviewed-by: Matthew Auld

Re: [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Add extra hdc flush workaround

2019-10-11 Thread Chris Wilson
Quoting Mika Kuoppala (2019-10-11 14:39:11) > In order to ensure constant caches are invalidated > properly with a0, we need extra hdc flush after invalidation. > > References: HSDES#1604544889 > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++ >

[Intel-gfx] [intel-gfx] [PATCH] drm/i915: coffeelake supports hdcp2.2

2019-10-11 Thread Juston Li
This includes other platforms that utilize the same gen graphics as CFL: AML, WHL and CML. Signed-off-by: Juston Li --- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add an rcu_barrier option to i915_drop_caches

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: Add an rcu_barrier option to i915_drop_caches URL : https://patchwork.freedesktop.org/series/67922/ State : success == Summary == CI Bug Log - changes from CI_DRM_7065 -> Patchwork_14770 Summary

Re: [Intel-gfx] [PATCH i-g-t] debugfs: Define DROP_RCU

2019-10-11 Thread Matthew Auld
On Fri, 11 Oct 2019 at 19:37, Chris Wilson wrote: > > Corresponding kernel commit 54895010a893 ("drm/i915: Add an rcu_barrier > option to i915_drop_caches") > > Signed-off-by: Chris Wilson > Cc: Matthew Auld Reviewed-by: Matthew Auld ___ Intel-gfx

[Intel-gfx] [CI 3/9] drm/i915/perf: allow for CS OA configs to be created lazily

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin Here we introduce a mechanism by which the execbuf part of the i915 driver will be able to request that a batch buffer containing the programming for a particular OA config be created. We'll execute these OA configuration buffers right before executing a set of userspace

[Intel-gfx] [CI 6/9] drm/i915/perf: execute OA configuration from command stream

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin We haven't run into issues with programming the global OA/NOA registers configuration from CPU so far, but HW engineers actually recommend doing this from the command streamer. On TGL in particular one of the clock domain in which some of that programming goes might not

[Intel-gfx] [PATCH 8/8] drm/i915: Nuke skl wm.dirty_pipes bitmask

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä The dirty_pipes bitmask is now unused. Get rid of it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 35 + 2 files changed, 1 insertion(+), 35 deletions(-) diff --git

[Intel-gfx] [PATCH 5/8] drm/i915: Streamline skl_commit_modeset_enables()

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä skl_commit_modeset_enables() is a bit of mess. Let's streamline it by simply tracking which pipes still need to be updated. As a bonus we get rid of the state->wm_results.dirty_pipes usage. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 39

[Intel-gfx] [PATCH 0/8] drm/i915: Some cleanup near the SKL wm/ddb area

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä Made the mistake of looking at some skl+ wm/ddb stuff, and then proceeded to throw out a bunch of useless things. I stopped when I saw struct skl_ddb_allocation and decided that maybe that starts to cut a bit too close to the dbuf slice stuff. Ville Syrjälä (8): drm/i915:

[Intel-gfx] [PATCH 7/8] drm/i915: Move linetime wms into the crtc state

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä The linetime watermarks really have very little in common with the plane watermarks. It looks to be cleaner to simply track them in the crtc_state and program them from the normal modeset/fastset paths. The only dark cloud comes from the fact that the register is still

[Intel-gfx] [PATCH 6/8] drm/i915: Polish WM_LINETIME register stuff

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä Let's store the normal and IPS linetime watermarks individually, and while at it we'll pimp the register definitions as well. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_types.h| 3 +- drivers/gpu/drm/i915/i915_reg.h | 14 ++--

[Intel-gfx] [PATCH 4/8] drm/i915: Don't set undefined bits in dirty_pipes

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä skl_commit_modeset_enables() straight up compares dirty_pipes with a bitmask of already committed pipes. If we set bits in dirty_pipes for non-existent pipes that comparison will never work right. So let's limit ourselves to bits that exist. And we'll do the same for the

[Intel-gfx] [PATCH 1/8] drm/i915: Nuke the useless changed param from skl_ddb_add_affected_pipes()

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä changed==true just means we have some crtcs in the state. All the stuff following this only operates on crtcs in the state anyway so there is no point in having this bool. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 30 --

[Intel-gfx] [PATCH 2/8] drm/i915: Nuke 'realloc_pipes'

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä The 'realloc_pipes' bitmask is pointless. It is either: a) the set of pipes which are already part of the state, in which case adding them again is entirely redundant b) the set of all pipes which we then add to the state Also the fact that 'realloc_pipes' uses the crtc

[Intel-gfx] [PATCH 3/8] drm/i915: Make dirty_pipes refer to pipes

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä Despite the its name dirty_pipes refers to crtc indexes. Let's change its behaviout to match the name. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++-- drivers/gpu/drm/i915/intel_pm.c | 13 ++--- 2 files

Re: [Intel-gfx] [PATCH] drm/i915: Add an rcu_barrier option to i915_drop_caches

2019-10-11 Thread Matthew Auld
On Fri, 11 Oct 2019 at 18:38, Chris Wilson wrote: > > Sometimes a test has to wait for RCU to complete a grace period and > perform its callbacks, for example waiting for a close(fd) to actually > perform the fput(filp) and so trigger all the callbacks such as closing > GEM contexts. There is no

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly

2019-10-11 Thread Souza, Jose
On Fri, 2019-10-11 at 10:16 +0300, Martin Peres wrote: > On 10/10/2019 23:18, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [1/4] drm/i915/display: Handle fused > > off display correctly > > URL : https://patchwork.freedesktop.org/series/67872/ > > State :

Re: [Intel-gfx] Does the i915 VBT tell us if a panel is an OLED panel?

2019-10-11 Thread Sean Paul
On Thu, Oct 10, 2019 at 04:35:56PM +0300, Jani Nikula wrote: > On Thu, 10 Oct 2019, Hans de Goede wrote: > > Hi Jani, > > > > During plumbers I had some discussions with Daniel about supporting > > OLED screens. Userspace may need to know that a panel is OLED for 2 > > reasons: > > > > 1) To

[Intel-gfx] [PATCH] drm/i915: Favor last VBT child device with conflicting AUX ch/DDC pin

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä The first come first served apporoach to handling the VBT child device AUX ch conflicts has backfired. We have machines in the wild where the VBT specifies both port A eDP and port E DP (in that order) with port E being the real one. So let's try to flip the preference

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Serialise write to scratch with its vma binding

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915/selftests: Serialise write to scratch with its vma binding URL : https://patchwork.freedesktop.org/series/67928/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14773

Re: [Intel-gfx] [PATCH 7/7] drm/dp-mst: fix warning on unused var

2019-10-11 Thread Souza, Jose
Reviewed-by: José Roberto de Souza On Thu, 2019-10-10 at 18:09 -0700, Lucas De Marchi wrote: > Fixes: 83fa9842afe7 ("drm/dp-mst: Drop connection_mutex check") > Signed-off-by: Lucas De Marchi > --- > drivers/gpu/drm/drm_dp_mst_topology.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git

[Intel-gfx] [PATCH i-g-t] debugfs: Define DROP_RCU

2019-10-11 Thread Chris Wilson
Corresponding kernel commit 54895010a893 ("drm/i915: Add an rcu_barrier option to i915_drop_caches") Signed-off-by: Chris Wilson Cc: Matthew Auld --- lib/igt_debugfs.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/lib/igt_debugfs.h b/lib/igt_debugfs.h index 36b638177..a56f09dd2

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm URL : https://patchwork.freedesktop.org/series/67927/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9446e81d2ad5 drm/i915/perf: Replace global wakeref

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Favor last VBT child device with conflicting AUX ch/DDC pin

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: Favor last VBT child device with conflicting AUX ch/DDC pin URL : https://patchwork.freedesktop.org/series/67931/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14775

Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush

2019-10-11 Thread Chris Wilson
Quoting Mika Kuoppala (2019-10-11 14:39:10) > Add hdc pipeline flush to ensure memory state is coherent > in L3 when we are done. > > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + > drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + > 2 files changed,

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm URL : https://patchwork.freedesktop.org/series/67927/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14772

Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush

2019-10-11 Thread Chris Wilson
Quoting Mika Kuoppala (2019-10-11 14:39:10) > Add hdc pipeline flush to ensure memory state is coherent > in L3 when we are done. > > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + > drivers/gpu/drm/i915/gt/intel_lrc.c | 1 + > 2 files changed,

[Intel-gfx] [CI 5/9] drm/i915/perf: implement active wait for noa configurations

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin NOA configuration take some amount of time to apply. That amount of time depends on the size of the GT. There is no documented time for this. For example, past experimentations with powergating configuration changes seem to indicate a 60~70us delay. We go with 500us as

[Intel-gfx] [CI 8/9] drm/i915/perf: allow holding preemption on filtered ctx

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin We would like to make use of perf in Vulkan. The Vulkan API is much lower level than OpenGL, with applications directly exposed to the concept of command buffers (pretty much equivalent to our batch buffers). In Vulkan, queries are always limited in scope to a command

[Intel-gfx] [CI 9/9] drm/i915/execlists: Prevent merging requests with conflicting flags

2019-10-11 Thread Chris Wilson
We set out-of-bound parameters inside the i915_requests.flags field, such as disabling preemption or marking the end-of-context. We should not coalesce consecutive requests if they have differing instructions as we only inspect the last active request in a context. Thus if we allow a later request

[Intel-gfx] [CI 7/9] drm/i915/perf: Allow dynamic reconfiguration of the OA stream

2019-10-11 Thread Chris Wilson
Introduce a new perf_ioctl command to change the OA configuration of the active stream. This allows the OA stream to be reconfigured between batch buffers, giving greater flexibility in sampling. We inject a request into the OA context to reconfigure the stream asynchronously on the GPU in between

[Intel-gfx] [CI 4/9] drm/i915: add support for perf configuration queries

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin Listing configurations at the moment is supported only through sysfs. This might cause issues for applications wanting to list configurations from a container where sysfs isn't available. This change adds a way to query the number of configurations and their content

[Intel-gfx] [CI 1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm

2019-10-11 Thread Chris Wilson
As we now have a specific engine to use OA on, exchange the top-level runtime-pm wakeref with the engine-pm. This still results in the same top-level runtime-pm, but with more nuances to keep the engine and its gt awake. Signed-off-by: Chris Wilson Reviewed-by: Lionel Landwerlin ---

[Intel-gfx] [CI 2/9] drm/i915/perf: introduce a versioning of the i915-perf uapi

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin Reporting this version will help application figure out what level of the support the running kernel provides. v2: Add i915_perf_ioctl_version() (Chris) Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson ---

[Intel-gfx] [PATCH] drm/i915/selftests: Serialise write to scratch with its vma binding

2019-10-11 Thread Chris Wilson
Add the missing serialisation on the request for a write into a vma to wait until that vma is bound before being executed by the GPU. Signed-off-by: Chris Wilson Cc: Matthew Auld --- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 8 1 file changed, 8 insertions(+) diff --git

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: coffeelake supports hdcp2.2

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: coffeelake supports hdcp2.2 URL : https://patchwork.freedesktop.org/series/67925/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14771 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Some cleanup near the SKL wm/ddb area

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: Some cleanup near the SKL wm/ddb area URL : https://patchwork.freedesktop.org/series/67930/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h

Re: [Intel-gfx] [PATCH] drm/i915: Expose engine properties via sysfs

2019-10-11 Thread Chris Wilson
Quoting Summers, Stuart (2019-10-11 16:14:07) > On Fri, 2019-10-11 at 12:36 +0100, Chris Wilson wrote: > > +void intel_engines_add_sysfs(struct drm_i915_private *i915) > > +{ > > + static const struct attribute *files[] = { > > + _attr.attr, > > + _attr.attr, > > +

Re: [Intel-gfx] [PATCH 7/7] drm/dp-mst: fix warning on unused var

2019-10-11 Thread Lucas De Marchi
+dri, +Daniel On Thu, Oct 10, 2019 at 06:09:07PM -0700, Lucas De Marchi wrote: Fixes: 83fa9842afe7 ("drm/dp-mst: Drop connection_mutex check") Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/drm_dp_mst_topology.c | 2 -- 1 file changed, 2 deletions(-) diff --git

Re: [Intel-gfx] [PATCH 10/10] drm/i915: Flush idle barriers when waiting

2019-10-11 Thread Tvrtko Ursulin
On 10/10/2019 08:14, Chris Wilson wrote: If we do find ourselves with an idle barrier inside our active while waiting, attempt to flush it by emitting a pulse using the kernel context. The point of this one completely escapes me at the moment. Idle barriers are kept in there to be consumed

Re: [Intel-gfx] [PATCH 6/7] drm/i915: prettify MST debug message

2019-10-11 Thread Ville Syrjälä
On Fri, Oct 11, 2019 at 10:08:32AM -0700, Lucas De Marchi wrote: > On Fri, Oct 11, 2019 at 03:08:50PM +0300, Ville Syrjälä wrote: > >On Thu, Oct 10, 2019 at 06:09:06PM -0700, Lucas De Marchi wrote: > >> s/?/:/ so it's get correctly colored by dmesg. > > > >What do you mean correctly? > > > >The

Re: [Intel-gfx] [PATCH 10/10] drm/i915: Flush idle barriers when waiting

2019-10-11 Thread Chris Wilson
Quoting Tvrtko Ursulin (2019-10-11 15:56:35) > > On 10/10/2019 08:14, Chris Wilson wrote: > > If we do find ourselves with an idle barrier inside our active while > > waiting, attempt to flush it by emitting a pulse using the kernel > > context. > > The point of this one completely escapes me at

[Intel-gfx] [PATCH] drm/i915: Add an rcu_barrier option to i915_drop_caches

2019-10-11 Thread Chris Wilson
Sometimes a test has to wait for RCU to complete a grace period and perform its callbacks, for example waiting for a close(fd) to actually perform the fput(filp) and so trigger all the callbacks such as closing GEM contexts. There is no trivial means of triggering an RCU barrier from userspace, so

[Intel-gfx] ✓ Fi.CI.IGT: success for mdev based hardware virtio offloading support (rev4)

2019-10-11 Thread Patchwork
== Series Details == Series: mdev based hardware virtio offloading support (rev4) URL : https://patchwork.freedesktop.org/series/66989/ State : success == Summary == CI Bug Log - changes from CI_DRM_7061_full -> Patchwork_14764_full

Re: [Intel-gfx] [PATCH 6/7] drm/i915: prettify MST debug message

2019-10-11 Thread Lucas De Marchi
On Fri, Oct 11, 2019 at 03:08:50PM +0300, Ville Syrjälä wrote: On Thu, Oct 10, 2019 at 06:09:06PM -0700, Lucas De Marchi wrote: s/?/:/ so it's get correctly colored by dmesg. What do you mean correctly? The debug message was asking the question "(is) MST supported?" After this it just

Re: [Intel-gfx] [PATCH 1/4] drm/i915/display: Handle fused off display correctly

2019-10-11 Thread Souza, Jose
On Fri, 2019-10-11 at 15:25 +0300, Ville Syrjälä wrote: > On Thu, Oct 10, 2019 at 12:32:38PM -0700, José Roberto de Souza > wrote: > > If all pipes are fused off it means that display is disabled, > > similar > > like we handle for GEN 7 and 8 right above. > > > > On GEN 9 the bit 31 is "Internal

Re: [Intel-gfx] [PATCH] drm/i915: Expose engine properties via sysfs

2019-10-11 Thread Summers, Stuart
On Fri, 2019-10-11 at 12:36 +0100, Chris Wilson wrote: > Preliminary stub to add engines underneath /sys/class/drm/cardN/, so > that we can expose properties on each engine to the sysadmin. > > To start with we have basic analogues of the i915_query ioctl so that > we > can pretty print engine

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate URL : https://patchwork.freedesktop.org/series/67912/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7064 -> Patchwork_14769

Re: [Intel-gfx] [PATCH 08/10] drm/i915: Cancel non-persistent contexts on close

2019-10-11 Thread Chris Wilson
Quoting Chris Wilson (2019-10-11 15:22:17) > Quoting Tvrtko Ursulin (2019-10-11 14:55:00) > > > > On 10/10/2019 08:14, Chris Wilson wrote: > > > + if (engine) > > > + active |= engine->mask; > > > + > > > + dma_fence_put(fence); > > > + } > > > + >

Re: [Intel-gfx] [PATCH v7 0/3] CRTC background color

2019-10-11 Thread Sean Paul
On Wed, Oct 09, 2019 at 02:27:41PM -0700, Matt Roper wrote: > On Wed, Oct 09, 2019 at 05:01:20PM -0400, Daniele Castagna wrote: > > On Wed, Oct 9, 2019 at 1:34 PM Matt Roper wrote: > > > > > > The previous version of this series was posted in February here: > > > > > >

Re: [Intel-gfx] [PATCH 6/7] drm/i915: prettify MST debug message

2019-10-11 Thread Lucas De Marchi
On Fri, Oct 11, 2019 at 08:14:32PM +0300, Ville Syrjälä wrote: On Fri, Oct 11, 2019 at 10:08:32AM -0700, Lucas De Marchi wrote: On Fri, Oct 11, 2019 at 03:08:50PM +0300, Ville Syrjälä wrote: >On Thu, Oct 10, 2019 at 06:09:06PM -0700, Lucas De Marchi wrote: >> s/?/:/ so it's get correctly

Re: [Intel-gfx] [PATCH v3] drm/i915: Restrict qgv points which don't have enough bandwidth.

2019-10-11 Thread James Ausmus
On Wed, Sep 25, 2019 at 03:17:37PM +0300, Stanislav Lisovskiy wrote: > According to BSpec 53998, we should try to > restrict qgv points, which can't provide > enough bandwidth for desired display configuration. > > Currently we are just comparing against all of > those and take minimum(worst

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: coffeelake supports hdcp2.2

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: coffeelake supports hdcp2.2 URL : https://patchwork.freedesktop.org/series/67925/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067_full -> Patchwork_14771_full Summary ---

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add an rcu_barrier option to i915_drop_caches

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: Add an rcu_barrier option to i915_drop_caches URL : https://patchwork.freedesktop.org/series/67922/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7065_full -> Patchwork_14770_full

Re: [Intel-gfx] Kernel crash on 4.19.77-1-lts (Arch Linux / ThinkPad T470p)

2019-10-11 Thread John Maguire
> Just use Cc. We want all replies to go to the list(s) as well. Sorry, I wasn't sure and wanted to err on the side of not spamming the wrong people. > Oct 10 12:53:30 scorpion kernel: RIP: 0010:dma_fence_signal_locked+0x30/0xe0 > > Looks like it could be >

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm URL : https://patchwork.freedesktop.org/series/67927/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067_full -> Patchwork_14772_full

[Intel-gfx] [PATCH v2] drm/i915: Expose engine properties via sysfs

2019-10-11 Thread Chris Wilson
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so that we can expose properties on each engine to the sysadmin. To start with we have basic analogues of the i915_query ioctl so that we can pretty print engine discovery from the shell, and flesh out the directory structure.

[Intel-gfx] [PATCH v2] drm/i915/execlists: Cancel banned contexts on schedule-out

2019-10-11 Thread Chris Wilson
On schedule-out (CS completion) of a banned context, scrub the context image so that we do not replay the active payload. The intent is that we skip banned payloads on request submission so that the timeline advancement continues on in the background. However, if we are returning to a preempted

Re: [Intel-gfx] [PATCH v2] drm/i915/execlists: Cancel banned contexts on schedule-out

2019-10-11 Thread Tvrtko Ursulin
On 11/10/2019 12:16, Chris Wilson wrote: On schedule-out (CS completion) of a banned context, scrub the context image so that we do not replay the active payload. The intent is that we skip banned payloads on request submission so that the timeline advancement continues on in the background.

Re: [Intel-gfx] [PATCH i-g-t] Check all sysfs entries are readable without dmesg spam

2019-10-11 Thread Tvrtko Ursulin
On 11/10/2019 13:43, Chris Wilson wrote: We already check that debugfs do not cause spam (and they tend to be more heavyhanded and so more likely to break), but that does not excuse not checking our sysfs directory! Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- tests/debugfs_test.c |

Re: [Intel-gfx] [PATCH] drm/i915/perf: Allow dynamic reconfiguration of the OA stream

2019-10-11 Thread Lionel Landwerlin
On 11/10/2019 00:23, Chris Wilson wrote: Introduce a new perf_ioctl command to change the OA configuration of the active stream. This allows the OA stream to be reconfigured between batch buffers, giving greater flexibility in sampling. We inject a request into the OA context to reconfigure the

[Intel-gfx] [PATCH 3/3] drm/i915/tgl: Add extra hdc flush workaround

2019-10-11 Thread Mika Kuoppala
In order to ensure constant caches are invalidated properly with a0, we need extra hdc flush after invalidation. References: HSDES#1604544889 Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++ 1 file changed, 18 insertions(+) diff --git

[Intel-gfx] [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate

2019-10-11 Thread Mika Kuoppala
Aim for completeness and invalidate also the ro parts in l3 cache. This might allow to get rid of the preparser disable/enable workaround on invalidation path. Cc: Chris Wilson Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +

[Intel-gfx] ✓ Fi.CI.IGT: success for Small fixes before fixing MST

2019-10-11 Thread Patchwork
== Series Details == Series: Small fixes before fixing MST URL : https://patchwork.freedesktop.org/series/67883/ State : success == Summary == CI Bug Log - changes from CI_DRM_7060_full -> Patchwork_14763_full Summary ---

Re: [Intel-gfx] Kernel crash on 4.19.77-1-lts (Arch Linux / ThinkPad T470p)

2019-10-11 Thread Ville Syrjälä
On Thu, Oct 10, 2019 at 01:15:09PM -0400, John Maguire wrote: > Hi there, > > I wasn't sure which mailing list to use so I BCC'd > intel-gfx@lists.freedesktop.org and dri-de...@lists.freedesktop.org Just use Cc. We want all replies to go to the list(s) as well. > > I'm using a Lenovo Thinkpad

Re: [Intel-gfx] [PATCH 07/10] drm/i915/execlists: Cancel banned contexts on schedule-out

2019-10-11 Thread Chris Wilson
Quoting Chris Wilson (2019-10-11 11:15:58) > Quoting Tvrtko Ursulin (2019-10-11 10:47:26) > > > + if (unlikely(i915_gem_context_is_banned(ce->gem_context))) > > > + cancel_active(rq, engine); > > > > Or you are counting this is already the last runnable request from this > >

[Intel-gfx] [bug report] drm/i915/selftests: Exercise context switching in parallel

2019-10-11 Thread Dan Carpenter
Hello Chris Wilson, This is a semi-automatic email about new static checker warnings. The patch 50d16d44cce4: "drm/i915/selftests: Exercise context switching in parallel" from Sep 30, 2019, leads to the following Smatch complaint: drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c:349

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Only mark incomplete requests as -EIO on cancelling

2019-10-11 Thread Tvrtko Ursulin
On 11/10/2019 11:33, Chris Wilson wrote: Only the requests that have not completed do we want to change the status of to signal the -EIO when cancelling the inflight set of requests upon wedging. Reported-by: Tvrtko Ursulin Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin ---

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Expose engine properties via sysfs (rev3)

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: Expose engine properties via sysfs (rev3) URL : https://patchwork.freedesktop.org/series/66849/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7061 -> Patchwork_14768 Summary ---

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