From: Andrew Lunn
> On Wed, Jun 26, 2019 at 03:47:44PM +0200, Jose Abreu wrote:
> > On PCI based setups that are connected to C45 PHY we won't have DT
> > bindings specifying what's the correct PHY type.
>
> You can associate a DT node to a PCI device. The driver
From: Andrew Lunn
> > +
> > + if (priv->dma_cap.addr64) {
> > + ret = dma_set_mask_and_coherent(device,
> > + DMA_BIT_MASK(priv->dma_cap.addr64));
> > + if (!ret)
> > + dev_info(priv->device, "Using %d bits DMA width\n",
> > +
From: Voon Weifeng
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dw_tsn_lib.c
> b/drivers/net/ethernet/stmicro/stmmac/dw_tsn_lib.c
> new file mode 100644
> index ..cba27c604cb1
> --- /dev/null
> +++ b/drivers/net/ethernet/stmicro/stmmac/dw_tsn_lib.c
XGMAC also supports TSN feat
From: Andrew Lunn
> There have been some drivers gaining patches for ACPI. That is
> probably the better long term solution, ask ACPI where is the PHY and
> what MDIO protocol to use to talk to it.
Hmmm, I'm not sure this is going to work that way ...
My setup is a PCI EP which is hot-pluggable
Fainelli
Cc: Heiner Kallweit
Jose Abreu (3):
net: stmmac: Prepare to convert to phylink
net: stmmac: Start adding phylink support
net: stmmac: Convert to phylink and remove phylib logic
drivers/net/ethernet/stmicro/stmmac/Kconfig | 3 +-
drivers/net/ethernet/stmicro/stmmac/stmmac.h
In preparation for the convertion, split the adjust_link function into
mac_config and add the mac_link_up and mac_link_down functions.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Russell King
Cc: Andrew Lunn
Cc: Florian
Convert everything to phylink.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Russell King
Cc: Andrew Lunn
Cc: Florian Fainelli
Cc: Heiner Kallweit
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 2 -
drivers/net
Start adding the phylink callbacks.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Russell King
Cc: Andrew Lunn
Cc: Florian Fainelli
Cc: Heiner Kallweit
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net
From: Russell King - ARM Linux admin
> If this is not used, I don't really see the point of splitting this from
> the rest of the patch. Also, I don't see the point of all those NULL
> initialisers either.
Thanks for the feedback. Please see previous discussion here that lead
to the introducti
We support many speeds and it doesn't make much sense to list them all
in the Kconfig. Let's just call it Multi-Gigabit.
Suggested-by: David S. Miller
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethern
set lower and upper value of descriptors address when initializing DMA
channels.
Luckly, this was working for me because I was assigning CMA to < 4GB
address space for performance reasons.
Fixes: a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in
XGMAC")
Signed-off
Add support for coalescing RX path by specifying number of frames which
don't need to have interrupt on completion bit set.
This is only available when RX Watchdog is enabled.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: M
Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next.
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Maxime Coquelin
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Jose Abreu (3):
net: stmmac: Implement RX Coalesce Frames setting
net
- XGMAC: 9.22 Gbps
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Maxime Coquelin
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac
++ Jesper: Who is most active committer of page pool API (?) ... Can you
please help review this ?
From: Jose Abreu
> Mapping and unmapping DMA region is an high bottleneck in stmmac driver,
> specially in the RX path.
>
> This commit introduces support for Page Pool API and uses
Suzuki
Tested-by: Katsuhiro Suzuki
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Sergei Shtylyov
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --gi
From: Andrew Lunn
> On Thu, Jun 27, 2019 at 01:33:59PM +0000, Jose Abreu wrote:
> > From: Andrew Lunn
> >
> > > There have been some drivers gaining patches for ACPI. That is
> > > probably the better long term solution, ask ACPI where is the PHY and
> >
For performance reasons decrease the default RX Watchdog value for the
minimum allowed.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/common.h | 2 +-
drivers/net/ethernet/stmicro/stmmac
XGMAC supports following speeds:
- 10G XGMII
- 5G XGMII
- 2.5G XGMII
- 2.5G GMII
- 1G GMII
- 100M MII
- 10M MII
Add them to the stmmac driver.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc
] 0.00-600.00 sec 643 GBytes 9.21 Gbits/sec1 sender
[ 5] 0.00-600.00 sec 643 GBytes 9.21 Gbits/sec receiver
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Jose Abreu (10):
net: stmmac: dwxgmac: Enable EDMA by default
This is a performance killer and anyways the interrupts are being
disabled by RX NAPI so no need to disable them again.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8
Undefined burst shall only be set if pdata asks to.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a
We support more speeds now. Update the Kconfig entry.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net
Currently, stmmac only supports 32 bits addressing for SKB. Enable the
support for upto 48 bits addressing in XGMAC core.
This avoids the use of bounce buffers and increases performance.
Changes from v1:
- Fallback to 32 bits in failure (Andrew)
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Update the RX Tail Pointer to the last available SKB entry.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net
Enable the EDMA feature by default which gives higher performance.
Changes from v1:
- Do not use magic values (David)
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 4
Do not enable EEE feature in the PHY if MAC does not support it.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
Only disable the interrupts if RX NAPI gets to be scheduled. Also,
schedule the TX NAPI only when the interrupts are disabled.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 10
From: Willem de Bruijn
> By the
>
> if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
> stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
> napi_schedule_irqoff(&ch->rx_napi);
> }
>
> branch directly above? If so, is it possible
From: David Miller
> About the Kconfig change, maybe it just doesn't make sense to list all
> of the various speeds the chip supports... just a thought.
What about: "STMicroelectronics Multi-Gigabit Ethernet driver" ?
Or, just "STMicroelectronics Ethernet driver" ?
From: Jesper Dangaard Brouer
> The page_pool DMA mapping cannot be "kept" when page traveling into the
> network stack attached to an SKB. (Ilias and I have a long term plan[1]
> to allow this, but you cannot do it ATM).
The reason I recycle the page is this previous call to:
skb_copy_
Thank you all for your review comments !
From: Ilias Apalodimas
> That's why i was concerned on what will happen on > 1000b frames and what the
> memory pressure is going to be.
> The trade off here is copying vs mapping/unmapping.
Well, the performance numbers I mentioned are for TSO with def
From: Jesper Dangaard Brouer
> The page_pool_request_shutdown() API return indication if there are any
> in-flight frames/pages, to know when it is safe to call
> page_pool_free(), which you are also missing a call to.
>
> This page_pool_request_shutdown() is only intended to be called from
> xd
set lower and upper value of descriptors address when initializing DMA
channels.
Luckly, this was working for me because I was assigning CMA to < 4GB
address space for performance reasons.
Fixes: a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in
XGMAC")
Signed-off
Add support for coalescing RX path by specifying number of frames which
don't need to have interrupt on completion bit set.
This is only available when RX Watchdog is enabled.
Acked-by: Jakub Kicinski
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallar
Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next.
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Jose Abreu (3):
net: stmmac: Implement RX Coalesce Frames setting
net: stmmac: Fix descriptors address being in > 32 b
- XGMAC: 9.22 Gbps
Changes from v1:
- Use page_pool_get_dma_addr() (Jesper)
- Add a comment (Jesper)
- Add page_pool_free() call (Jesper)
- Reintroduce sync_single_for_device (Arnd / Ilias)
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc
From: Jesper Dangaard Brouer
> You can just use page_pool_free() (p.s I'm working on reintroducing
> page_pool_destroy wrapper). As you say, you will not have in-flight
> frames/pages in this driver use-case.
Well, if I remove the request_shutdown() it will trigger the "API usage
violation" WA
From: Andrew Lunn
> Yes, that is all clear. The stmmac_mdio_c45_setup() does part of this
> setup. There is also a write to mii_address which i snipped out when
> replying. But why do you need to write to the data registers during a
> read? C22 does not need this write. Are there some bits in the
From: Jesper Dangaard Brouer
> This code is okay, but I would likely write it as:
>
> if (rx_q->page_pool) {
> page_pool_request_shutdown(rx_q->page_pool));
> page_pool_free(rx_q->page_pool);
> }
>
> Because (as you noticed) page_pool_free() have some API misuse checks,
> that w
/ Ilias)
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Ilias Apalodimas
Cc: Jesper Dangaard Brouer
Cc: Arnd Bergmann
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac/stmmac.h
Add support for coalescing RX path by specifying number of frames which
don't need to have interrupt on completion bit set.
This is only available when RX Watchdog is enabled.
Acked-by: Jakub Kicinski
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallar
set lower and upper value of descriptors address when initializing DMA
channels.
Luckly, this was working for me because I was assigning CMA to < 4GB
address space for performance reasons.
Fixes: a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in
XGMAC")
Signed-off
Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next.
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Jose Abreu (3):
net: stmmac: Implement RX Coalesce Frames setting
net: stmmac: Fix descriptors address being in > 32 b
From: Ilias Apalodimas
> I think this look ok for now. One request though, on page_pool_free
Thanks for the review!
> A patch currently under review will slightly change that [1] and [2]
> Can you defer this a bit till that one gets merged?
> The only thing you'll have to do is respin this and
should be reverted upstream and in all
stable branches. Instead, the driver should implement the
ndo_select_queue operation and override the queue mapping there."
Fixes: c5acdbee22a1 ("net: stmmac: Send TSO packets always from Queue 0")
Suggested-by: Ben Hutchings
From: Ilias Apalodimas | Date: Fri, Jul
05, 2019 at 16:24:53
> Well ideally we'd like to get the change in before the merge window ourselves,
> since we dont want to remove->re-add the same function in stable kernels. If
> that doesn't go in i am fine fixing it in the next merge window i guess,
From: Jon Hunter
Date: Jul/18/2019, 10:16:20 (UTC+00:00)
> Have you tried using NFS on a board with this ethernet controller?
I'm having some issues setting up the NFS server in order to replicate
so this may take some time.
Are you able to add some debug in stmmac_init_rx_buffers() to see wha
From: Jon Hunter
Date: Jul/19/2019, 09:37:49 (UTC+00:00)
>
> On 19/07/2019 08:51, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/18/2019, 10:16:20 (UTC+00:00)
> >
> >> Have you tried using NFS on a board with this ethernet controller?
> >
> &
From: Jon Hunter
Date: Jul/19/2019, 09:49:10 (UTC+00:00)
>
> On 19/07/2019 09:44, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/19/2019, 09:37:49 (UTC+00:00)
> >
> >>
> >> On 19/07/2019 08:51, Jose Abreu wrote:
> >>> From: Jo
From: Jose Abreu
Date: Jul/19/2019, 11:25:41 (UTC+00:00)
> Thanks. Can you add attached patch and check if WARN is triggered ?
BTW, also add the attached one in this mail. The WARN will probably
never get triggered without it.
Can you also print "buf->addr" after the WARN_
From: Jon Hunter
Date: Jul/19/2019, 13:30:10 (UTC+00:00)
> I booted the board without using NFS and then started used dhclient to
> bring up the network interface and it appears to be working fine. I can
> even mount the NFS share fine. So it does appear to be particular to
> using NFS to mount t
From: Jon Hunter
Date: Jul/19/2019, 14:35:52 (UTC+00:00)
>
> On 19/07/2019 13:32, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/19/2019, 13:30:10 (UTC+00:00)
> >
> >> I booted the board without using NFS and then started used dhclient to
> >
Two fixes targeting -net.
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose Abreu
Cc: "David S. Miller"
Cc: Maxime Coquelin
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
---
RX Descriptors are being cleaned after setting the buffers which may
lead to buffer addresses being wiped out.
Fix this by clearing earlier the RX Descriptors.
Fixes: 2af6106ae949 ("net: stmmac: Introducing support for Page Pool")
Signed-off-by: Jose Abreu
---
Cc: Giuseppe Cav
We need the memory to be zeroed upon allocation so use kcalloc()
instead.
Signed-off-by: Jose Abreu
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose Abreu
Cc: "David S. Miller"
Cc: Maxime Coquelin
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stormreply.com
Cc:
From: Jon Hunter
Date: Jul/22/2019, 10:37:18 (UTC+00:00)
>
> On 22/07/2019 08:23, Jose Abreu wrote:
> > From: Jon Hunter
> > Date: Jul/19/2019, 14:35:52 (UTC+00:00)
> >
> >>
> >> On 19/07/2019 13:32, Jose Abreu wrote:
> >>> From: Jo
From: Jose Abreu
Date: Jul/22/2019, 10:47:44 (UTC+00:00)
> From: Jon Hunter
> Date: Jul/22/2019, 10:37:18 (UTC+00:00)
>
> >
> > On 22/07/2019 08:23, Jose Abreu wrote:
> > > From: Jon Hunter
> > > Date: Jul/19/2019, 14:35:52 (UTC+00:00)
> > >
From: Lars Persson
Date: Jul/22/2019, 12:11:50 (UTC+00:00)
> On Mon, Jul 22, 2019 at 12:18 PM Ilias Apalodimas
> wrote:
> >
> > On Thu, Jul 18, 2019 at 07:48:04AM +, Jose Abreu wrote:
> > > From: Jon Hunter
> > > Date: Jul/17/2019, 19:58:53 (UTC+00:00)
&
From: Ondřej Jirman
Date: Jul/22/2019, 13:42:40 (UTC+00:00)
> Hello Jose,
>
> On Tue, Jun 11, 2019 at 05:18:44PM +0200, Jose Abreu wrote:
> > [ Hope this diff looks better (generated with --minimal) ]
> >
> > This converts stmmac to use phylink. Besides the code redu
From: Andrew Lunn
Date: Jul/22/2019, 14:40:23 (UTC+00:00)
> Does this mean that all stmmac variants support 1G? There are none
> which just support Fast Ethernet?
This glue logic drivers sometimes reflect a custom IP that's Synopsys
based but modified by customer, so I can't know before-hand wh
From: Jon Hunter
Date: Jul/22/2019, 13:05:38 (UTC+00:00)
>
> On 22/07/2019 12:39, Jose Abreu wrote:
> > From: Lars Persson
> > Date: Jul/22/2019, 12:11:50 (UTC+00:00)
> >
> >> On Mon, Jul 22, 2019 at 12:18 PM Ilias Apalodimas
> >> wrote:
> >&
Some glue logic drivers support 1G without having GMAC/GMAC4/XGMAC.
Let's allow this speed by default.
Reported-by: Ondrej Jirman
Tested-by: Ondrej Jirman
Fixes: 5b0d7d7da64b ("net: stmmac: Add the missing speeds that XGMAC supports")
Signed-off-by: Jose Abreu
---
Cc: Giusepp
From: Andrew Lunn
Date: Jul/22/2019, 15:19:43 (UTC+00:00)
> On Mon, Jul 22, 2019 at 01:58:20PM +0000, Jose Abreu wrote:
> > From: Andrew Lunn
> > Date: Jul/22/2019, 14:40:23 (UTC+00:00)
> >
> > > Does this mean that all stmmac variants support 1G? There are none
From: Ilias Apalodimas | Date: Tue, Jul 09, 2019
at 08:23:56
> The patch from Ivan did get merged, can you change the free call to
> page_pool_destroy and re-spin? You can add my acked-by
Yes, I will re-spin then. Thanks!
---
Thanks,
Jose Miguel Abreu
Some performace improvements (01/03 and 03/03) and a fix (02/03), all for -next.
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose Abreu
Cc: "David S. Miller"
Cc: Maxime Coquelin
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: net...@vger.kernel.org
Cc: linux-s
Add support for coalescing RX path by specifying number of frames which
don't need to have interrupt on completion bit set.
This is only available when RX Watchdog is enabled.
Acked-by: Jakub Kicinski
Signed-off-by: Jose Abreu
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose
)
- Reintroduce sync_single_for_device (Arnd / Ilias)
Signed-off-by: Jose Abreu
Acked-by: Ilias Apalodimas
---
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Cc: Jose Abreu
Cc: "David S. Miller"
Cc: Maxime Coquelin
Cc: net...@vger.kernel.org
Cc: linux-st...@st-md-mailman.stor
set lower and upper value of descriptors address when initializing DMA
channels.
Luckly, this was working for me because I was assigning CMA to < 4GB
address space for performance reasons.
Fixes: a993db88d17d ("net: stmmac: Enable support for > 32 Bits addressing in
XGMAC")
Signed-of
From: Joe Perches
Date: Jul/10/2019, 06:04:21 (UTC+00:00)
> Arguments are supposed to be ordered high then low.
>
> Signed-off-by: Joe Perches
If you submit another version please add:
Fixes: 293e4365a1ad ("stmmac: change descriptor layout")
Fixes: 9f93ac8d4085 ("net-next: stmmac: Add dwmac-s
en TX is still not done it
will return 0 budget).
Fix this by looking at all TX channels in NAPI poll function.
Signed-off-by: Jose Abreu
Fixes: 8fce33317023 ("net: stmmac: Rework coalesce timer and fix multi-queue
races")
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
instances per each TX and RX queue, as
suggested by Florian.
Changes from v1:
- Pass entire ring size to TX clean path (Florian)
Signed-off-by: Jose Abreu
Cc: Florian Fainelli
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet
interrupts that are enabled so, no event will
be missed.
In my tests withe XGMAC2 this increased performance.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 4 +++-
d
Tested in XGMAC2 and GMAC5.
Cc: Florian Fainelli
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
Jose Abreu (3):
net: stmmac: Fix NAPI poll in TX path when in multi-queue
net: stmmac: dwmac4: Also use TBU interrupt to clean TX path
net: stmmac: dwxgmac2
interrupts that are enabled so, no event will be
missed.
In my tests with GMAC5 this increased performance.
Signed-off-by: Jose Abreu
Cc: Joao Pinto
Cc: David S. Miller
Cc: Giuseppe Cavallaro
Cc: Alexandre Torgue
---
drivers/net/ethernet/stmicro/stmmac/dwmac4_
We are saving the status of EEE even before we try to enable it. This
leads to a race with XMIT function that tries to arm EEE timer before we
set it up.
Fix this by only saving the EEE parameters after all operations are
performed with success.
Signed-off-by: Jose Abreu
Fixes: d765955d2ae0
On 2/18/2019 8:49 AM, Jose Abreu wrote:
> #define XGMAC_DMA_INT_DEFAULT_EN (XGMAC_NIE | XGMAC_AIE | XGMAC_RBUE | \
> - XGMAC_RIE | XGMAC_TIE)
> + XGMAC_RIE | XGMAC_TBUE | XGMAC_TIE)
This is wrong and was a left-
Hi Andrew,
On 3/1/2019 1:53 PM, Andrew Lunn wrote:
> On Fri, Mar 01, 2019 at 11:54:24AM +0100, Jose Abreu wrote:
>> +static inline int phy_update_link(struct phy_device *phydev)
>> +{
>> +if (!phydev->drv)
>> +return -EIO;
>> +
Hi Ville,
On 04-01-2017 16:36, Ville Syrjälä wrote:
> On Wed, Jan 04, 2017 at 04:15:01PM +0000, Jose Abreu wrote:
>>
[snip]
>>> Why does userspace need to know this? My thinking has been that the
>>> driver would do the right thing automagically.
>>>
Hi Ville,
On 05-01-2017 11:46, Ville Syrjälä wrote:
> On Thu, Jan 05, 2017 at 10:07:45AM +0000, Jose Abreu wrote:
>> Hi Ville,
>>
>>
>> On 04-01-2017 16:36, Ville Syrjälä wrote:
>>> On Wed, Jan 04, 2017 at 04:15:01PM +, Jose Abreu wrote:
>>
>
to say that you should make sure the output
colorspace is RGB or else DVI will fail to work, but I just
noticed the output colorspace is fixed in the code to RGB.
Though, that may change in the future.
Reviewed-by: Jose Abreu
Best regards,
Jose Miguel Abreu
> ---
> drivers/gpu/drm/bridge/dw
Hi Neil,
On 17-01-2017 12:31, Neil Armstrong wrote:
> Some display pipelines can only provide non-RBG input pixels to the HDMI TX
> Controller, this patch takes the pixel format from the plat_data if provided.
>
> Signed-off-by: Neil Armstrong
> ---
> drivers/gpu/drm/bridge/dw-hdmi.c | 7 +-
Hi Neil,
On 17-01-2017 12:31, Neil Armstrong wrote:
> @@ -1434,9 +1434,18 @@ static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct
> drm_display_mode *mode)
> hdmi_av_composer(hdmi, mode);
>
> /* HDMI Initializateion Step B.2 */
> - ret = dw_hdmi_phy_init(hdmi);
> - if (ret
Hi Neil,
On 18-01-2017 11:20, Neil Armstrong wrote:
>
> It's the idea we discussed with Laurent.
> Keeping the Synopsys PHY code inside the dw-hdmi driver would be simpler.
>
> But don't you think adding a proper "ops" structure apart from the plat_data
> should be necessary ?
>
> Neil
>
An "ops
Hi Laurent,
On 18-01-2017 20:49, Laurent Pinchart wrote:
>
> Ideally the bridge mode set operation should be extended to take format and
> colorspace information (or another bridge operation should be created for
> that
> purpose, I'm still undecided). As that's quite a big change, I'm fine if
Hi Ville,
Sorry for the late reply.
On 11-01-2017 11:36, Ville Syrjälä wrote:
> On Wed, Jan 11, 2017 at 10:27:03AM +0000, Jose Abreu wrote:
>> Hi Ville,
>>
>>
>> On 10-01-2017 17:21, Ville Syrjälä wrote:
>>
>> [snip]
>>
>>>> Bu
Hi Shashank,
Thanks for the review.
On 09-01-2017 05:22, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 12/30/2016 10:23 PM, Jose Abreu wrote:
>> HDMI 2.0 introduces a new sampling mode called YCbCr 4:2:0.
>> According to the spec the EDID may contain
Hi Shashank,
On 09-01-2017 12:45, Sharma, Shashank wrote:
> Regards
>
> Shashank
>
>
> On 1/9/2017 4:41 PM, Jose Abreu wrote:
>> Hi Shashank,
>>
>>
>> Thanks for the review.
>>
>>
>> On 09-01-2017 05:22, Sharma, Shashank wrote:
>
SDP platform.
Jose Abreu (2):
ASoC: dwc: Add record capability in PIO mode
ASoC: dwc: Enable 24 bit sample size in PIO mode
sound/soc/dwc/designware_i2s.c | 9 +++-
sound/soc/dwc/designware_pcm.c | 99 +-
sound/soc/dwc/local.h | 9 +++-
3
platform and in ARC AXS101 SDP platform.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Liam Girdwood
Cc: Mark Brown
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Cc: alsa-de...@alsa-project.org
Cc: linux-kernel@vger.kernel.org
---
sound/soc/dwc/designware_i2s.c | 9 +++-
sound/soc/dwc/designware_pcm.c
Sample size of 24 bits use in reality 32 bits for storage. We
can safelly enable this sample size and treat the data as
32 bits.
Tested in a x86_64 platform and in ARC AXS101 SDP platform.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Liam Girdwood
Cc: Mark Brown
Cc: Jaroslav Kysela
Cc
Hi Ville,
On 10-01-2017 11:16, Ville Syrjälä wrote:
> On Thu, Jan 05, 2017 at 02:46:06PM +0000, Jose Abreu wrote:
>>
[snip]
>> The pixel clock rate is half of the TMDS character rate in 4:2:0
>> (in 24 bit), but for example in deep color 48 bit it will be the
>>
Hi Ville,
[snip]
>> Are you going to update all the userspace clients? Exposing HDMI 2.0
>> modes only for your favorite client doesn't sound like a good plan to
>> me.
>>
>> If we simply compute from a specific modeline whether it needs to be
>> transmitted as 4:2:0, I suppose we could simply l
A parameter description for the interruptions of the
I2S controller was added.
Signed-off-by: Jose Abreu
Acked-by: Rob Herring
Cc: Carlos Palminha
Cc: Mark Brown
Cc: Liam Girdwood
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Cc: Rob Herring
Cc: Alexey Brodkin
Cc: linux-snps
gs entries (as suggested by Alexey Brodkin)
Cc: Carlos Palminha
Cc: Mark Brown
Cc: Liam Girdwood
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Cc: Rob Herring
Cc: Alexey Brodkin
Cc: linux-snps-...@lists.infradead.org
Cc: alsa-de...@alsa-project.org
Cc: linux-kernel@vger.kernel.org
Jose Abreu (2):
the reason why this extension was added.
Signed-off-by: Jose Abreu
Cc: Carlos Palminha
Cc: Mark Brown
Cc: Liam Girdwood
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Cc: Rob Herring
Cc: Alexey Brodkin
Cc: linux-snps-...@lists.infradead.org
Cc: alsa-de...@alsa-project.org
Cc: linux-kernel
Hi Daniel,
On 30-05-2016 10:36, Daniel Vetter wrote:
> On Mon, May 30, 2016 at 10:00:56AM +0100, Jose Abreu wrote:
>> ++ Daniel
>>
>>
>> On 30-05-2016 09:44, Jose Abreu wrote:
>>> Hi Daniel,
>>>
>>> Thanks for your answer.
>>>
&g
Hi Daniel,
On 15-06-2016 09:52, Daniel Vetter wrote:
> On Tue, Jun 14, 2016 at 1:19 PM, Jose Abreu wrote:
>>> I assume that xilinx VDMA is the only way to feed pixel data into your
>>> display pipeline. Under that assumption:
>>>
>>> drm_plane shoul
Hi Daniel,
Thanks for your answer.
On 26-05-2016 09:06, Daniel Vetter wrote:
> On Wed, May 25, 2016 at 04:46:15PM +0100, Jose Abreu wrote:
>> Hi all,
>>
>> Currently I am trying to develop a DRM driver that will use
>> Xilinx VDMA to transfer video data to a HDMI
++ Daniel
On 30-05-2016 09:44, Jose Abreu wrote:
> Hi Daniel,
>
> Thanks for your answer.
>
> On 26-05-2016 09:06, Daniel Vetter wrote:
>> On Wed, May 25, 2016 at 04:46:15PM +0100, Jose Abreu wrote:
>>> Hi all,
>>>
>>> Currently I am trying to de
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