Now that we have a GPIO driver for the AXP209, we can add it to our MFD.
Signed-off-by: Maxime Ripard
Acked-by: Linus Walleij
---
drivers/mfd/axp20x.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index fd80b0981f0f..4b3e073c47b7 100644
The CHIP has a status LED connected to one of the AXP GPIOs. Add the
gpio-leds node to be able to use the proper LED framework to control it.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun5i-r8-chip.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts
NULL, 0, NULL);
> + } else if (of_device_is_compatible(pdev->dev.of_node,
> + "allwinner,sun6i-a31-ts")) {
> + if (of_property_read_bool(pdev->dev.of_node,
> + "
ERNEL);
> + if (!info)
> + return -ENOMEM;
> +
> + info->buffer = iio_channel_get_all_cb(&pdev->dev,
> + &sunxi_gpadc_ts_callback,
> + (void *)info);
> + if (IS_ERR(i
inner,sun8i-h3-emac":
> +- allwinner,use-internal-phy: Use the H3 SoC's internal E(thernet) PHY
Can't that be derived from the presence of the phy property?
> +- allwinner,leds-active-low: EPHY LEDs are active low
That also seems PHY related. Overall, I feel like we really need a phy
node for the internal phy.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Fri, Jul 15, 2016 at 12:38:54PM +0200, Ondřej Jirman wrote:
> On 15.7.2016 10:53, Maxime Ripard wrote:
> > On Fri, Jul 01, 2016 at 02:50:57AM +0200, Ondřej Jirman wrote:
> >>>> /**
> >>>> + * sun8i_h3_apply_pll1_factors() - applies n, k, m, p fact
rnor. I don't see the system moving from
> 1008MHz to 24MHz and then to 1200MHz when some computation is needed!
It wouldn't happen that often. The sampling rate for the governor is
1000 times the latency, so, at most, 0.1% of the time would be spent
at 24MHz.
And if you're re
"iio_hwmon",
> > >> I still really dislike using this to force the probe of that driver but
> > >> kind of up to the hwmon / mfd guys on this.
> > >
> > > Can you at least say *why* you don't like it?
> > It just feels odd to have an mfd
> Also check candidates against the requested rate, rather than the
> ideal parent rate, the varying dividers also influence the difference
> between the requested rate and the rounded rate.
>
> Signed-off-by: Chen-Yu Tsai
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electron
On Mon, Sep 19, 2016 at 11:36:18PM +0800, Chen-Yu Tsai wrote:
> On Mon, Sep 19, 2016 at 3:16 AM, Maxime Ripard
> wrote:
> > Hi,
> >
> > On Thu, Sep 15, 2016 at 11:14:02PM +0800, Chen-Yu Tsai wrote:
> >> With display pixel clocks we want to have the closest poss
pare/disable delays are properly taken into account.
>
> This is useful for avoiding visual glitches.
This is not really taking any delays into account, especially since
drm_panel_enable and prepare are suppose to block until their
operation is complete.
Maxime
--
Maxime Ripard, Free Electr
On Thu, Sep 22, 2016 at 09:13:12AM +0200, Danny Milosavljevic wrote:
> Some of the registers defined in the driver are only usable on the
> A20. Rename these registers.
>
> Signed-off-by: Danny Milosavljevic
Acked-by: Maxime Ripard
Thanks!
Maxime
--
Maxime Ripard, Free Electr
On Thu, Sep 22, 2016 at 09:13:13AM +0200, Danny Milosavljevic wrote:
> The A20 has a few extra registers that the A10 doesn't have.
> Therefore, use different regmaps for A10 as compared to A20.
>
> Signed-off-by: Danny Milosavljevic
Acked-by: Maxime Ripard
Thanks!
Maxime
ner A10.
>
> Handle quirks by regmap config and codec and select the correct quirks
> automatically.
Usually, you would set the history of changes from one version to the
other here.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electro
On Mon, Jun 20, 2016 at 12:48:38PM +0800, Icenowy Zheng wrote:
> The NAND controller on some sun8i chips needs its reset line to be
> deasserted before they can enter working state.
>
> Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Thanks,
Maxime
--
Maxime Ripard, Fr
On Mon, Jun 20, 2016 at 12:48:37PM +0800, Icenowy Zheng wrote:
> Document the reset lines
>
> Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
sign
ull = ;
> >>> + };
> >>> +
> >>> + usb0_id_det: usb0_id_detect_pin@0 {
> >>> + allwinner,pins = "PD10";
> >>> + allwinner,function = "gpio_in";
> >>> + allwinner,drive = ;
> >>> + allwinner,pull = ;
> >>> + };
> >>> +
> >>> + usb1_vbus_pin_r16: usb1_vbus_pin@0 {
> >>> + allwinner,pins = "PD12";
> >>> + allwinner,function = "gpio_out";
> >>> + allwinner,drive = ;
> >>> + allwinner,pull = ;
> >>> + };
> >>> +};
> >>> +
> >>> +&r_pio {
> >>> + wifi_reset_pin_r16: wifi_reset_pin@3 {
> >>
> >> Why @3?
> >>
> >
> > This is a typo, I'll correct it.
> >
> >>> + allwinner,pins = "PL6";
> >>> + allwinner,function = "gpio_out";
> >>> + allwinner,drive = ;
> >>> + allwinner,pull = ;
> >>> + };
> >>> +};
> >>> +
> >>> +&r_rsb {
> >>> + status = "okay";
> >>> +
> >>> + axp22x: pmic@3a3 {
> >>> + compatible = "x-powers,axp223";
> >>> + reg = <0x3a3>;
> >>> + interrupt-parent = <&nmi_intc>;
> >>> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> >>> + eldoin-supply = <®_dcdc1>;
> >>
> >> A drivevbus-supply referencing reg_vcc5v0 here would be better.
> >>
> >
> > ACK.
> >
> >>> + x-powers,drive-vbus-en;
> >>> + };
> >>> +};
> >>> +
> >>> +#include "axp22x.dtsi"
> >>> +
> >>> +®_aldo1 {
> >>> + regulator-always-on;
> >>> + regulator-min-microvolt = <300>;
> >>> + regulator-max-microvolt = <300>;
> >>> + regulator-name = "aldo1";
> >>
> >> What is this for exactly? Would turning it off render the system
> >> inoperable?
> >> How was it referenced in the fex file?
> >>
> >> If this is for WiFi I/O VCC, then you should specify it in mmc1 with
> >> vqmmc-supply.
> >>
> >
> > In the fex, aldo1 is one of the three power inputs for the WiFi (the
> > others being dldo1 and dldo2) and in the schematics it is linked to
> > both VCC-USB and VCC-IO-WIFI.
> >
> > I tried to turn it off and, indeed, the system becomes inoperable.
> >
> > I'll add vqmmc-supply in mmc1 with aldo1 regulator. However, I am
> > wondering what to put in vmmc-supply for mmc1 since the WiFi module has
> > three power inputs: dldo1, dldo2 and aldo1. In the fex, they are
> > referenced as, respectively, module_power1, module_power2 and
> > module_power3 and in the schematics dldo1 and dldo2 are named VCC-WIFI
> > while aldo1 is used for VCC-IO-WIFI (if it can help in any way).
> >
> > VCC-WIFI is connected to pin VBAT of the Broadcom AP6212 WiFi chip.
> > VCC-IO-WIFI is connected to pin VDDIO of the chip.
>
> VCC-IO-WIFI is vqmmc, and VCC-WIFI is vmmc.
Isn't vmmc supposed to be always powered at 3.3v, and vqmmc the one
used to drop to 1.8V with the UHS cards?
In which case, VCC-IO-WIFI is vmmc, and VCC-WIFI is just one of the
wifi chip power rail, to be handled by a power sequence.
> About having 2 regulators, Maxime is working on a solution. In the
> meantime, you could have dldo1/dldo2 always-on, and put a TODO
> comment on them.
Yep.
> Not sure about it also linked to VCC-USB though. Is VCC-USB connected
> to the SoC or just a trace on the board? If it's the latter, it might
> also be designed to work with a USB based WiFi module.
It seems to be one of the inputs of the SoC.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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he host side, and whatever external pull-ups
> that might exist.
Ok.
> > In which case, VCC-IO-WIFI is vmmc, and VCC-WIFI is just one of the
> > wifi chip power rail, to be handled by a power sequence.
>
> For the WiFi chip, there is a separate IO-VCC rail, which is VCC-IO-WIFI.
> This, from what I understand of the datasheet, is for I/O signaling, and
> thus vqmmc. VCC-WIFI is what powers the chip, which is what vmmc is.
Ok. but there's still the issue of the two regulators that needs to be
kept in sync. Before, that, I'd rather stice to not tying them to the
MMC bus, and putting a comment on top.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Hi Stephen,
On Mon, Jun 20, 2016 at 06:15:37PM -0700, Stephen Boyd wrote:
> On 06/07, Maxime Ripard wrote:
> > +
> > +#include
> > +
> > +#include "ccu_common.h"
> > +
> > +struct ccu_fixed_factor {
> > + u16 div;
>
Hi Jean-Francois,
On Tue, Jun 21, 2016 at 11:40:44AM +0200, Jean-Francois Moine wrote:
> On Tue, 7 Jun 2016 22:41:39 +0200
> Maxime Ripard wrote:
>
> > The current code has been tested on the H3 and an Orange Pi PC,
> > including making sure that MMC still works, so
previous version.
Maxime
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Embedded Linux and Kernel engineering
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On Thu, Sep 22, 2016 at 08:03:31AM +1000, Jonathan Liu wrote:
> Hi Maxime,
>
> On Thursday, 22 September 2016, Maxime Ripard com> wrote:
>
> > On Wed, Sep 21, 2016 at 11:03:04PM +1000, Jonathan Liu wrote:
> > > The panel should be enabled after the controller s
sive as
> the ndelay, or the ndelay is less preferred, then I gladly make the
> change;
For the spin_lock part, I was just comparing it to a
spin_lock_irqsave, which is pretty expensive since it masks all the
interrupts in the system, introducing latencies.
> but I think we need the ndelay for the else where we do not
> have the ready flag (A10 or A13 iirc?)
H, good point. But that would also apply to your second patch
then, wouldn't it?
Maxime
--
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Embedded Linux and Kernel engineering
http://free-electrons.com
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On Fri, Sep 23, 2016 at 11:43:55PM +1000, Jonathan Liu wrote:
> Hi Maxime,
>
> On 23 September 2016 at 23:16, Maxime Ripard
> wrote:
> > On Thu, Sep 22, 2016 at 08:03:31AM +1000, Jonathan Liu wrote:
> >> Hi Maxime,
> >>
> >> On Thursday, 22 Septe
On Sat, Sep 24, 2016 at 10:05:01PM +0200, Danny Milosavljevic wrote:
> Rename "sun4i_codec_widgets" to "sun4i_codec_controls" for
> consistency with the struct field name.
>
> Signed-off-by: Danny Milosavljevic
Acked-by: Maxime Ripard
Thanks!
Maxime
--
Maxime
ock
> before-after this block where you basically get a very long lasting
> spin_lock, the alternative.
If you're only reading, why do you need to take the lock?
You probbaly want to have a timeout too.
Maxime
--
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Embedded Linux and Kernel engineering
http://free-electrons.com
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On Wed, Jul 27, 2016 at 10:36:49AM +0200, Jean-Francois Moine wrote:
> On Wed, 27 Jul 2016 09:40:20 +0200
> Maxime Ripard wrote:
>
> > > > Parenting functions would also not work as expected,
> > > > clk_hw_get_parent_by_index being the obvious example, in that
by Jean-Francois.
I guess I'd prefer to have the SoC names in the define, just in case
we need to introduce support for another SoC, but this can always be
done later.
Thanks!
Maxime
--
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Embedded Linux and Kernel engineering
http://free-electrons.com
sign
On Wed, Jul 27, 2016 at 01:02:41PM +0300, stefan.mavrod...@gmail.com wrote:
> On Wednesday, July 27, 2016 8:21:46 AM EEST Maxime Ripard wrote:
> > On Wed, Jul 27, 2016 at 08:12:29AM +0300, stefan.mavrod...@gmail.com wrote:
> > > > > +®_dcdc1 {
> > &
On Thu, Jul 28, 2016 at 03:40:31PM +0200, LABBE Corentin wrote:
> On Thu, Jul 21, 2016 at 09:55:19AM +0200, Maxime Ripard wrote:
> > Hi,
> >
> > On Wed, Jul 20, 2016 at 10:03:18AM +0200, LABBE Corentin wrote:
> > > This patch adds documentation for Device-Tree bi
On Wed, Jul 27, 2016 at 10:46:23AM +0200, Jean-Francois Moine wrote:
> On Tue, 26 Jul 2016 22:30:28 +0200
> Maxime Ripard wrote:
>
> > ere is the previous A64 patches made by Andre [1], reworked to use
> > the new sunxi-ng clock framework.
> >
> > This uses t
2..637fb7c 100644
> --- a/include/linux/mfd/axp20x.h
> +++ b/include/linux/mfd/axp20x.h
> @@ -21,6 +21,7 @@ enum {
> AXP223_ID,
> AXP288_ID,
> AXP809_ID,
> + AXP813_ID,
> NR_AXP20X_VARIANTS,
> };
>
> @@ -91,6 +92,16 @@ enum {
> #define AXP22X_ALDO3_V_OUT 0x2a
> #define AXP22X_CHRG_CTRL30x35
>
> +#define AXP813_FLDO1_V_OUT 0x1c
> +#define AXP813_FLDO2_V_OUT 0x1d
> +#define AXP813_DCDC1_V_OUT 0x20
> +#define AXP813_DCDC2_V_OUT 0x21
> +#define AXP813_DCDC3_V_OUT 0x22
> +#define AXP813_DCDC4_V_OUT 0x23
> +#define AXP813_DCDC5_V_OUT 0x24
> +#define AXP813_DCDC6_V_OUT 0x25
> +#define AXP813_DCDC7_V_OUT 0x26
> +
> /* Interrupt */
> #define AXP152_IRQ1_EN 0x40
> #define AXP152_IRQ2_EN 0x41
> @@ -288,6 +299,33 @@ enum {
> AXP809_REG_ID_MAX,
> };
>
> +enum {
> + AXP813_DCDC1 = 0,
> + AXP813_DCDC2,
> + AXP813_DCDC3,
> + AXP813_DCDC4,
> + AXP813_DCDC5,
> + AXP813_DCDC6,
> + AXP813_DCDC7,
> + AXP813_RTC_LDO,
> + AXP813_ALDO1,
> + AXP813_ALDO2,
> + AXP813_ALDO3,
> + AXP813_DLDO1,
> + AXP813_DLDO2,
> + AXP813_DLDO3,
> + AXP813_DLDO4,
> + AXP813_ELDO1,
> + AXP813_ELDO2,
> + AXP813_ELDO3,
> + AXP813_FLDO1,
> + AXP813_FLDO2,
> + AXP813_LDO_IO0,
> + AXP813_LDO_IO1,
> + AXP813_DC1SW,
> + AXP813_REG_ID_MAX,
> +};
> +
> /* IRQs */
> enum {
> AXP152_IRQ_LDO0IN_CONNECT = 1,
Looks fine otherwise.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
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P809_DC1SW)
> > ||
> > + (regulators == axp813_regulators && i == AXP813_DC1SW))
> > {
>
> Are we getting to the point now where we need some other way to flag
> these? Maybe a set of flags per regulator?
I'd be inclined to say
k/linux.git/log/?h=clk-sunxi-ng
> On 26.7.2016 08:32, Maxime Ripard wrote:
> > On Thu, Jul 21, 2016 at 11:52:15AM +0200, Ondřej Jirman wrote:
> >>>>> If so, then yes, trying to switch to the 24MHz oscillator before
> >>>>> applying the factors, and then swi
P_INT_FIFOC_TP_FIFO_TRIG_LEVEL(x) ((GENMASK(4, 0)
> & (x)) << 8)
> +#define SUNXI_GPADC_TP_INT_FIFOC_TP_DATA_DRQ_EN BIT(7)
> +#define SUNXI_GPADC_TP_INT_FIFOC_TP_FIFO_FLUSH BIT(4)
> +#define SUNXI_GPADC_TP_INT_FIFOC_TP_UP_IRQ_ENBIT(1)
> +#define SUNXI_GPADC_TP_INT_FIFOC_TP_DOWN_IRQ_EN BIT(0)
> +
> +#define SUNXI_GPADC_TP_INT_FIFOS 0x14
> +
> +#define SUNXI_GPADC_TP_INT_FIFOS_TEMP_DATA_PENDING BIT(18)
> +#define SUNXI_GPADC_TP_INT_FIFOS_FIFO_OVERRUN_PENDINGBIT(17)
> +#define SUNXI_GPADC_TP_INT_FIFOS_FIFO_DATA_PENDING BIT(16)
> +#define SUNXI_GPADC_TP_INT_FIFOS_TP_IDLE_FLG BIT(2)
> +#define SUNXI_GPADC_TP_INT_FIFOS_TP_UP_PENDING BIT(1)
> +#define SUNXI_GPADC_TP_INT_FIFOS_TP_DOWN_PENDING BIT(0)
> +
> +#define SUNXI_GPADC_TP_CDAT 0x1c
> +#define SUNXI_GPADC_TEMP_DATA0x20
> +#define SUNXI_GPADC_TP_DATA 0x24
> +
> +#define SUNXI_IRQ_FIFO_DATA 0
> +#define SUNXI_IRQ_TEMP_DATA 1
... and sometimes not at all.
> +
> +/* 10s delay before suspending the IP */
> +#define SUNXI_GPADC_AUTOSUSPEND_DELAY1
> +
> +struct sunxi_gpadc_mfd_dev {
> + struct device *dev;
> + struct regmap *regmap;
> + struct regmap_irq_chip_data *regmap_irqc;
> + void __iomem*regs;
> +};
> +
> +#endif
> --
> 2.5.0
>
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; + "could not request FIFO_DATA_PENDING interrupt: %d\n",
> + ret);
> + goto err;
> + }
> +
> + disable_irq(irq);
> + info->fifo_data_irq = irq;
> + atomic_set(&info->ignore_fifo_data_irq, 0);
These tw
t the handler is currently running from).
> > > +}
> > > +
> > > +static int sun8i_emac_probe(struct platform_device *pdev)
> > > +{
> > > + struct device_node *node = pdev->dev.of_node;
> > > + struct sun8i_emac_priv *priv;
> > > + struct net_device *ndev;
> > > + struct resource *res;
> > > + int ret;
> > > +
> > > + ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
> > > + if (ret) {
> > > + dev_err(&pdev->dev, "No suitable DMA available\n");
> > > + return ret;
> > > + }
> >
> > Isn't that the default?
> >
> No, it is necessary on arm64 as apritzel requested.
http://lxr.free-electrons.com/source/drivers/of/device.c#L93
It seems to be shared between the two.
Thanks!
Maxime
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Embedded Linux and Kernel engineering
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;
> I have searched for txdelay in Documentation, and found a few driver
> that give the units (us/ps).
>
> But in that case, the value in ps/us must be found in a table
> indexed by the Xxdelay value.
>
> So the settings seems always a raw number, and for sun8i-emac
> nothing
On Mon, Jul 25, 2016 at 10:03:14AM +0200, Michal Suchanek wrote:
> Hello,
>
> On 25 July 2016 at 09:32, Maxime Ripard
> wrote:
> > On Fri, Jun 17, 2016 at 12:34:44PM +0200, Michal Suchanek wrote:
> >> Hello,
> >>
> >> On 13 June 2016 at 21:57, Max
A can not acquire next TX descriptor
> >> > > + * and TX DMA FSM is suspended.
> >> > > + */
> >> > > + if (v & BIT(2))
> >> > > + priv->estats.tx_dma_ua++;
> >> > > +
> >> > > + if (v & BIT
clock for the spdif bus.
> "spdif" clock for spdif controller.
>
> + - reset: reset specifier for the ahb reset (A31 and newer only)
Isn't it resets ? (plural)
Thanks,
Maxime
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to 4 so it's been adjusted
> to 8 which suites both the older and newer SoCs.
>
> Signed-off-by: Marcus Cooper
Acked-by: Maxime Ripard
Thanks,
Maxime
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Embedded Linux and Kernel engineering
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lwinner,sun6i-a31-spdif")) {
>
> Given how much Allwinner likes to shuffle stuff around with each SoC
> generation, would it make sense to add a flag for this in some
> compatible specific config structure instead of checking against the
> compatible?
It really depends on the size
On Sat, Jul 30, 2016 at 05:34:11PM +0200, Code Kipper wrote:
> On 30 July 2016 at 17:17, Maxime Ripard
> wrote:
> > On Sat, Jul 30, 2016 at 04:27:15PM +0200, codekip...@gmail.com wrote:
> >> From: Marcus Cooper
> >>
> >> The A31 SoC uses the same SPDIF
On Fri, Jul 29, 2016 at 07:48:00AM +0200, Jean-Francois Moine wrote:
> On Thu, 28 Jul 2016 22:07:05 +0200
> Maxime Ripard wrote:
>
> > > > Let me know what you think,
> > >
> > > I don't see the interest to have common code for 32bits and 64bits
Hi,
On Fri, Jul 29, 2016 at 12:01:09AM +0200, Ondřej Jirman wrote:
> On 28.7.2016 23:00, Maxime Ripard wrote:
> > Hi Ondrej,
> >
> > On Thu, Jul 28, 2016 at 01:27:05PM +0200, Ondřej Jirman wrote:
> >> Hi Maxime,
> >>
> >> I don't have your
eeds to specify which
> pin is used for what signal (RGB, YUV, S/Video, composite).
> There seems to be an implicit rule that 1 pin is always used
> for composite, and the 3 others RGB, though.
I'm not sure why we would need to rework this one though. We have no
way to detect whet
On Tue, Sep 06, 2016 at 09:12:56AM +0200, Olliver Schinagl wrote:
> Hi Maxime!,
>
> On za, 2016-08-27 at 00:19 +0200, Maxime Ripard wrote:
> > On Thu, Aug 25, 2016 at 07:50:10PM +0200, Olliver Schinagl wrote:
> > >
> > > When we inform the PWM block to stop togge
he existing blocks in the DTS files
> to just "status = okay".
>
> Peripherals requiring board-specific things (like emac, USB, voltage
> regulators, displays) stay put in the DTS.
>
> It will explodes the scope of my proposed change a bit, but if you are OK
> wit
On Tue, Sep 06, 2016 at 11:04:38AM +0800, Chen-Yu Tsai wrote:
> On Tue, Sep 6, 2016 at 3:31 AM, Maxime Ripard
> wrote:
> > Hi Jorik,
> >
> > On Sat, Sep 03, 2016 at 02:09:32PM +0200, Jorik Jonker wrote:
> >> On Fri, Sep 02, 2016 at 09:04:25AM +0200, Maxime Ripard
SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
> > + SUNXI_FUNCTION(0x3, "emac")), /* ECRS */
>
> The cover letter said ethernet was gone?
That was my understanding, I doubled check and it's indeed there. I'll
amend the commit log. Thanks!
Maxim
From: Mylène Josserand
Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.
Signed-off-by: Mylène Josserand
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/
ettle down.
Signed-off-by: Mylène Josserand
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/ntc-gr8.dtsi | 1080
1 file changed, 1080 insertions(+)
create mode 100644 arch/arm/boot/dts/ntc-gr8.dtsi
diff --git a/arch/arm/boot/dts/ntc-gr8.dtsi b/arch/ar
The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family.
It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S),
but some controllers missing too (Ethernet, less I2C, less UARTs).
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
Documentation/arm
From: Mylène Josserand
The GR8-EVB is a small board with an NextThing GR8, an Hynix MLC NAND,
an AXP209 PMIC, USB host and OTG, an SPDIF output and a connectors for CSI,
I2S and LCD.
Signed-off-by: Mylène Josserand
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/Makefile| 1
they won't be usable.
Let me know if you have any questions,
Maxime
Changes from v1:
- Removed the panel part for now
- Added a few missing gates
- Changed the gate clocks compatible to the generic one
- Switched to the OTG mode
Maxime Ripard (1):
ARM: sunxi: Support the Nextth
Hi Linus,
On Wed, Sep 07, 2016 at 09:17:08PM +0200, Linus Walleij wrote:
> On Wed, Sep 7, 2016 at 4:53 PM, Maxime Ripard
> wrote:
>
> > From: Mylène Josserand
> >
> > Just like the other member of the sunxi family, let's add a pinctrl table
> > for the
Hi,
On Wed, Sep 07, 2016 at 09:41:19PM +0200, Linus Walleij wrote:
> On Wed, Aug 31, 2016 at 10:25 AM, Milo Kim wrote:
>
> > H3 has single PWM channel. The second PWM channel is not supported,
> > so the pinctrl function should be removed.
> >
> > Cc: Linus
Hi,
On Tue, Sep 06, 2016 at 10:08:05PM +0800, Chen-Yu Tsai wrote:
> On Tue, Sep 6, 2016 at 8:18 PM, Maxime Ripard
> wrote:
> > Now that we have support for the CCU driver in sunxi-ng, convert the A23
> > and A33 DTs to that driver.
> >
> > Signed-off-by: Maxime
;
> Signed-off-by: Jorik Jonker
There's really several options for the UART0 to be muxed, so it's
better if we leave that to the board entirely.
That's useful only for pins where you truely have only a single
option in the entire SoC.
Maxime
--
Maxime Ripard, Free Electrons
E
TS is very rare among the boards. Forcing it down the
throat of every user doesn't seem like the right thing to do.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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};
>
> - uart1_pins_a: uart1@0 {
> + uart1_rts_cts_pins: uart1_rts_cts {
> allwinner,pins = "PG6", "PG7", "PG8", "PG9";
I'd prefer to have one pinctrl node for RX/TX, and on
Hi,
On Wed, Sep 07, 2016 at 09:58:54AM +0200, jo...@kippendief.biz wrote:
> From: Jorik Jonker
>
> These are the only possible pins for UART0 on H3
That's not true, you can also mux it on PF2 / PF4.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineeri
On Tue, Sep 06, 2016 at 11:16:33PM +0800, Chen-Yu Tsai wrote:
> On Tue, Sep 6, 2016 at 10:46 PM, Maxime Ripard
> wrote:
> > The A33 has a significantly different pipeline, with components that differ
> > too.
> >
> > Make sure we had compatible for them.
> &
er group.
> Can pinconf/pinctrl work without them? Would there be any harm
> converting the sunxi driver to work directly with pins? This would
> make it match generic pinconf parsing, and make it easier to get
> both working together.
I think it comes from a requirement that yo
<36>, <40>, <44>,
> > @@ -254,7 +254,7 @@
> > "ahb_ohci", "ahb_ss",
> > "ahb_dma",
> > "ahb_bist", "ahb_mmc0",
> > "ahb_mmc1",
> > "ahb_mmc2", "ahb_nand",
> > -"ahb_sdram", "ahb_spi0",
> > +"ahb_sdram", "ahb_sdram",
> > "ahb_spi0",
>
> I don't think this will work. Copy/paste error?
Yes, that was supposed to be ethernet. Sorry.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Thu, Sep 08, 2016 at 12:32:48AM +0800, Chen-Yu Tsai wrote:
> On Wed, Sep 7, 2016 at 10:53 PM, Maxime Ripard
> wrote:
> > From: Mylène Josserand
> >
> > The GR8 is an SoC made by Nextthing loosely based on the sun5i family.
> >
> > Since it's not clear
On Tue, Sep 06, 2016 at 04:46:11PM +0200, Maxime Ripard wrote:
> Hi everyone,
>
> This serie introduces the support in the sun4i-drm driver for the A33.
>
> Beside the new IPs and special cases for the A33 new IPs, there's
> nothing really outstanding, and is now at feat
be able to test that it actually works before adding it
to the clock driver.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Wed, Sep 07, 2016 at 12:20:10AM +0800, Chen-Yu Tsai wrote:
> On Tue, Sep 6, 2016 at 8:18 PM, Maxime Ripard
> wrote:
> > Some dividers might have a maximum value that is lower than the width of
> > the register.
> >
> > Add a field to _ccu_div to handle those case
On Thu, Sep 08, 2016 at 10:02:13AM +0200, Jorik Jonker wrote:
> Maxime, Chen-Yu: thanks for taking the effort to go through my patches
> again!
>
> On Thu, Sep 08, 2016 at 08:23:17AM +0200, Maxime Ripard wrote:
> >On Wed, Sep 07, 2016 at 09:58:57AM +0200, jo...@kippendief.b
On Thu, Sep 08, 2016 at 04:32:25PM +0800, Chen-Yu Tsai wrote:
> On Thu, Sep 8, 2016 at 4:29 PM, Maxime Ripard
> wrote:
> > On Wed, Sep 07, 2016 at 03:24:11PM +0800, Chen-Yu Tsai wrote:
> >> > + [CLK_BUS_MSGBOX]= &bus_msgbox_clk.common.hw,
> &
used that on the CPU
clocks
- Renamed the CE (crypto engine) clocks to SS (security system) to
stick to what's being used in the datasheet
- Added a TODO to mention that we don't really know whose parents
are linked to the USB clocks.
Maxime Ripard (8):
Add support for the class with a single factor, N, being a multiplier.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/Kconfig| 4 ++
drivers/clk/sunxi-ng/Makefile | 1 +
drivers/clk/sunxi-ng/ccu_mult.c | 133
..62c0f8d49ef8
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23-a33.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2016 Maxime Ripard
+ *
+ * Maxime Ripard
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as pub
Add support for the clock unit found in the A23. Due to the similarities
with the A33, it also shares its clock IDs to allow sharing the DTSI.
Signed-off-by: Maxime Ripard
---
.../devicetree/bindings/clock/sunxi-ccu.txt| 1 +
drivers/clk/sunxi-ng/Kconfig | 12
27;ll use whatever value has been set.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi-ng/ccu_div.h | 24
drivers/clk/sunxi-ng/ccu_mp.c | 23 +--
drivers/clk/sunxi-ng/ccu_nkm.c | 4 ++--
drivers/clk/sunxi-ng/ccu_nkmp.c
The internal _ccu_div structure is meant to be embedded into other
structures to combine the various dividers and to form the clock classes
support.
Start to document those structures by using kerneldoc.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi-ng/ccu_div.h | 14 ++
1
Add a new macro to declare muxes based on a table and a gate.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_mux.h | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk
Now that we have support for the CCU driver in sunxi-ng, convert the A23
and A33 DTs to that driver.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 257 ---
arch/arm/boot/dts/sun8i-a23.dtsi | 51 ++-
arch
Add some macros to ease the declaration of clocks that are using them.
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
drivers/clk/sunxi-ng/ccu_div.h | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_div.h b
Hi Javier,
On Wed, Sep 07, 2016 at 04:51:55PM +0200, Javier Martinez Canillas wrote:
> Hello Maxime,
>
> On Wed, Aug 31, 2016 at 10:18 AM, Maxime Ripard
> wrote:
>
> [snip]
>
> > +
> > +#include "skeleton.dtsi"
> > +
>
> The skeleton.dt
On Wed, Sep 07, 2016 at 07:51:48PM +0200, Rask Ingemann Lambertsen wrote:
> On Wed, Aug 31, 2016 at 4:18 PM, Maxime Ripard
> wrote:
> > From: Mylène Josserand
> >
> > The GR8 is an SoC made by Nextthing loosely based on the sun5i family.
> >
> > Since it&#x
ettle down.
Signed-off-by: Mylène Josserand
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/ntc-gr8.dtsi | 1087
1 file changed, 1087 insertions(+)
create mode 100644 arch/arm/boot/dts/ntc-gr8.dtsi
diff --git a/arch/arm/boot/dts/ntc-gr8.dtsi b/arch/ar
The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family.
It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S),
but some controllers missing too (Ethernet, less I2C, less UARTs).
Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
---
Documentation/arm
From: Mylène Josserand
The GR8-EVB is a small board with an NextThing GR8, an Hynix MLC NAND,
an AXP209 PMIC, USB host and OTG, an SPDIF output and a connectors for CSI,
I2S and LCD.
Signed-off-by: Mylène Josserand
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/Makefile| 1
ctrl macros for the NAND pinctrl nodes
Changes from v1:
- Removed the panel part for now
- Added a few missing gates
- Changed the gate clocks compatible to the generic one
- Switched to the OTG mode
Maxime Ripard (1):
ARM: sunxi: Support the Nextthing GR8
Mylène Josserand (2):
+ compatible = "phg,pcf8563";
> > + reg = <0x51>;
> > + };
> > +
> > + wm8978: codec@1a {
>
> I think these should be ordered by address? Otherwise
Yeah, sorry, I don't know how to count anymore
t; drivers/gpu/drm/sun4i/sun4i_framebuffer.h,
> drivers/gpu/drm/sun4i/sun4i_rgb.h,
> drivers/gpu/drm/sun4i/sun4i_dotclock.h,
> so this patch adds missing header dependencies.
>
> Signed-off-by: Baoyou Xie
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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On Thu, Sep 08, 2016 at 11:48:35AM +0200, Maxime Ripard wrote:
> Hi everyone,
>
> Here is the migration for the A23 and A33 clocks to the sunxi-ng
> framework.
>
> It has been tested on SinA33 board, and I made sure that everything
> was reported at the exact same rate, t
On Tue, Sep 06, 2016 at 04:46:11PM +0200, Maxime Ripard wrote:
> Hi everyone,
>
> This serie introduces the support in the sun4i-drm driver for the A33.
>
> Beside the new IPs and special cases for the A33 new IPs, there's
> nothing really outstanding, and is now at feat
>
> Signed-off-by: Chen-Yu Tsai
> ---
>
> Hi Maxime,
>
> This patch applies on top of your A23/A33 CCU patches.
It was not applying properly. I think I did the proper fixup, but
you'll probably want to double check.
Maxime
--
Maxime Ripard, Free Electrons
Embedded
cenowy Zheng
>
> Oh I forgot to add a patch version number...
> It's PATCH v3.
>
> (But it seems that I should send a v4 to split the dtsi change and dts
> change.)
Indeed :)
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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e. I hope I get it and five
> times is a charm :-)
I queued it, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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Description: PGP signature
t
> > line is connected to NMI pin of the SoC.
> >
> > Signed-off-by: Chen-Yu Tsai
>
> The driver patches have all been merged into the mfd tree. Could
> you queue up the dts patches?
I just did.
Thanks for the remainder,
Maxime
--
Maxime Ripard, Free Electr
The A10-EVB from Allwinner comes with an unidentified panel, with the only
mark on the PCB being A10-SUB-EVB-5LCD.
Add timings to simple panel to handle it.
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions
From: Mylène Josserand
Just like the other member of the sunxi family, let's add a pinctrl table
for the muxing options.
Signed-off-by: Mylène Josserand
Signed-off-by: Maxime Ripard
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kc
The GR8 is an SoC made by Nextthing Co, loosely based on the sun5i family.
It has a number of new controllers compared to the A10s and A13 (SPDIF, I2S),
but some controllers missing too (Ethernet, less I2C, less UARTs).
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/arm
Some backlight GPIOs might be connected to some i2c based expanders whose
access might sleep.
Since it's not in any critical path, use the cansleep variant of the GPIO
API.
Signed-off-by: Maxime Ripard
---
drivers/video/backlight/pwm_bl.c | 4 ++--
1 file changed, 2 insertions(+), 2 dele
m them, so
they won't be usable.
Let me know if you have any questions,
Maxime
Maxime Ripard (3):
backlight: pwm_bl: Handle gpio that can sleep
drm/panel: simple: Add A10 EVB 5 inch panel support
ARM: sunxi: Support the Nextthing GR8
Mylène Josserand (3):
pinctrl: sunxi: Add GR8 con
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