On 12/5/2018 12:33 PM, Rajendra Nayak wrote:
+ return 0;
+ }
+
+ of_node_put(np);
This same code exists twice. Perhaps a helper needs to exist for
qcom_rpm_get_performance() to pull the number out of the DT.
Sure I can make both drivers use a common helper
Add the DT node for the rpmhpd powercontroller.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 51
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index
Add rpmpd device node and its OPP table
Signed-off-by: Rajendra Nayak
Signed-off-by: Viresh Kumar
Reviewed-by: Ulf Hansson
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch
be extended to support other SoCs which support RPMh
Signed-off-by: Rajendra Nayak
Reviewed-by: Ulf Hansson
---
drivers/soc/qcom/Kconfig | 9 +
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/rpmhpd.c | 431 ++
3 files changed, 441 insertions(+)
create mode
can easily
be extended by adding data for other qualcomm SoCs as well.
Signed-off-by: Rajendra Nayak
Signed-off-by: Viresh Kumar
Reviewed-by: Ulf Hansson
Acked-by: Rob Herring
---
drivers/soc/qcom/Kconfig | 9 ++
drivers/soc/qcom/Makefile | 1 +
drivers/soc/qcom/rpmpd.c | 294
Add support for the .set_performace_state() and .opp_to_performance_state()
callbacks in the rpmpd driver.
Signed-off-by: Rajendra Nayak
Signed-off-by: Viresh Kumar
Reviewed-by: Ulf Hansson
---
drivers/soc/qcom/rpmpd.c | 46
1 file changed, 46
/26/333
Rajendra Nayak (8):
dt-bindings: opp: Introduce qcom-opp bindings
dt-bindings: power: Add qcom rpm power domain driver bindings
soc: qcom: rpmpd: Add a Power domain driver to model corners
soc: qcom: rpmpd: Add support for get/set performance state
arm64: dts: msm8996: Add rpmpd
Add DT bindings to describe the rpm/rpmh power domains found on Qualcomm
Technologies, Inc. SoCs. These power domains communicate a performance
state to RPM/RPMh, which then translates it into corresponding voltage on a
PMIC rail.
Signed-off-by: Rajendra Nayak
Signed-off-by: Viresh Kumar
hardware blocks on SDM845 that MX performance state >= CX performance
state for a given operating frequency.
Signed-off-by: Rajendra Nayak
---
This patch is dependent on the series from
Viresh [1] which adds support to propogate performance states across the
power domain hierarchy which is st
these bindings in the qcom-opp bindings document.
Signed-off-by: Rajendra Nayak
Acked-by: Viresh Kumar
---
.../devicetree/bindings/opp/qcom-opp.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt
diff --git
On 12/5/2018 4:42 AM, Stephen Boyd wrote:
Overall looks good to me, just some nitpicks around modules and
includes.
Thanks for the review, I will fix up all your concerns below and respin soon.
Quoting Rajendra Nayak (2018-12-03 21:21:14)
The Power domains for corners just pass
On 12/5/2018 4:44 AM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2018-12-03 21:21:15)
@@ -221,6 +224,47 @@ static int rpmpd_power_off(struct generic_pm_domain
*domain)
return ret;
}
+static int rpmpd_set_performance(struct generic_pm_domain *domain
On 12/5/2018 4:46 AM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2018-12-03 21:21:18)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b72bdb0a31a5..a6d0cd8d17b0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom
Hi Viresh,
On 11/5/2018 12:06 PM, Viresh Kumar wrote:
This commit updates genpd core to start propagating performance state
updates to master domains that have their set_performance_state()
callback set.
A genpd handles two type of performance states now. The first one is the
performance state
On 11/21/2018 11:01 AM, Rajendra Nayak wrote:
On 11/21/2018 10:46 AM, Viresh Kumar wrote:
On 21-11-18, 10:33, Rajendra Nayak wrote:
Hi Viresh,
On 11/5/2018 12:06 PM, Viresh Kumar wrote:
This commit updates genpd core to start propagating performance state
updates to master domains
On 11/21/2018 10:46 AM, Viresh Kumar wrote:
On 21-11-18, 10:33, Rajendra Nayak wrote:
Hi Viresh,
On 11/5/2018 12:06 PM, Viresh Kumar wrote:
This commit updates genpd core to start propagating performance state
updates to master domains that have their set_performance_state()
callback set
On 11/5/2018 12:06 PM, Viresh Kumar wrote:
Introduce a new helper dev_pm_opp_xlate_performance_state() which will
be used to translate from pstate of a device to another one.
Initially this will be used by genpd to find pstate of a master domain
using its sub-domain's pstate.
Signed-off-by:
On 11/9/2018 10:09 PM, Niklas Cassel wrote:
On Mon, Nov 05, 2018 at 05:17:45PM -0600, Rob Herring wrote:
On Mon, Oct 15, 2018 at 02:47:49PM +0200, Niklas Cassel wrote:
Extend qcom-opp bindings with properties needed for Core Power Reduction
(CPR).
CPR is included in a great variety of
On 11/21/2018 11:36 AM, Viresh Kumar wrote:
On 21-11-18, 10:47, Viresh Kumar wrote:
On 21-11-18, 10:34, Rajendra Nayak wrote:
On 11/5/2018 12:06 PM, Viresh Kumar wrote:
Introduce a new helper dev_pm_opp_xlate_performance_state() which will
be used to translate from pstate of a device
On 11/21/2018 12:06 PM, Viresh Kumar wrote:
On 21-11-18, 11:12, Rajendra Nayak wrote:
And the reason for that seems to be that we update the genpd status to
GPD_STATE_ACTIVE
*after* we try to set the performance state, so we always hit this check which
bails out
thinking the genpd
ings)
Tested-by: Rajendra Nayak
[1] https://patchwork.ozlabs.org/cover/935289/
Based on opp/linux-next branch (which is 4.20-rc1 +
multiple-power-domain-support-in-opp-core + some OPP fixes).
v1->V2:
- First patch (1/5) is new and an improvement to earlier stuff.
- Move genpd_s
On 11/20/2018 9:44 PM, Niklas Cassel wrote:
On Tue, Nov 20, 2018 at 09:42:05AM +0530, Rajendra Nayak wrote:
On 11/9/2018 10:09 PM, Niklas Cassel wrote:
On Mon, Nov 05, 2018 at 05:17:45PM -0600, Rob Herring wrote:
On Mon, Oct 15, 2018 at 02:47:49PM +0200, Niklas Cassel wrote:
Extend qcom
.
Tested-by: Rajendra Nayak
---
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
index fd9c893..df8127b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1
Hi Tony,
On Thursday 04 April 2013 05:12 AM, Tony Lindgren wrote:
> Hi,
>
[]..
>> @@ -1663,6 +1664,40 @@ static struct omap_clk omap44xx_clks[] = {
>> CLK(NULL, "cpufreq_ck", _mpu_ck, CK_443X),
>> };
>>
>> +static struct clk *scrm_clks[] = {
>> +_ck,
>> +_ck,
>> +
[]..
> +
> +#define pr_fmt(fmt) "%s: " fmt, __func__
> +
> +#ifdef DEBUG
> +#define prn(num) printk(#num "=%d\n", num)
> +#define prx(num) printk(#num "=%x\n", num)
> +#else
> +#define prn(num) do { } while (0)
> +#define prx(num) do { } while (0)
> +#endif
> +
> +#include
> +#include
>
consistent manner to fix the same if the i2c dev interface have no
> consistent numbering. Provide alias to allow ordering the i2c devices
> correctly.
This looks good Nishanth. Shouldn't we just go ahead and fix these for
all OMAPs/AMxx devices which would have the same problem as OMAP5 ;)
series SoCs, where i2c is defined.
Thanks Nishanth.
Acked-by: Rajendra Nayak
>
> V1: https://patchwork.kernel.org/patch/3046671/
>
> Nishanth Menon (2):
> ARM: dts: OMAP3+: Add i2c aliases
> ARM: dts: AM33xx+: Add i2c aliases
>
> arch/arm/boot/dts/am33xx.dtsi |
On Tuesday 05 November 2013 06:44 PM, Sricharan R wrote:
> Enable the crossbar IP support for DRA7xx soc.
>
> Cc: Santosh Shilimkar
> Cc: Rajendra Nayak
> Cc: Tony Lindgren
> Signed-off-by: Sricharan R
> ---
> arch/arm/mach-omap2/Kconfig|1 +
> arch/ar
[]...
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 29a043e..4688265 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -15,6 +15,7 @@ OMAP
[]..
> diff --git a/arch/arm/mach-omap2/board-generic.c
> b/arch/arm/mach-omap2/board-generic.c
> index 0274ff7..23f2064 100644
> --- a/arch/arm/mach-omap2/board-generic.c
> +++ b/arch/arm/mach-omap2/board-generic.c
> @@ -158,7 +158,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened
>
On Thursday 21 March 2013 07:24 PM, Roger Quadros wrote:
> On 03/21/2013 03:08 PM, Rajendra Nayak wrote:
>> []..
>>
>>> diff --git a/arch/arm/mach-omap2/board-generic.c
>>> b/arch/arm/mach-omap2/board-generic.c
>>> index 0274ff7..23f2064 100644
>
; corresponding implementation in drivers/regulator/core.c.
>
> Ensure the description is more inline with the original intent.
>
> Cc: Rajendra Nayak
>
> Reported-by: Kishon Vijay Abraham I
> Signed-off-by: Nishanth Menon
> ---
>
> Ref: my confusion in http://marc.info/?t
On Wednesday 24 April 2013 09:58 PM, Mike Turquette wrote:
> Quoting Nishanth Menon (2013-04-14 14:19:17)
>> Overall strategy introduced here is simple: a clock node described in
>> device tree blob is used to identify the exact clock provided in the
>> SoC specific data. This is then linked back
am I
> ---
> Changes from v1:
> * changed the clock domain to "pcie_clkdm"
> * Added PCIe as a slave port for l3_main.
Looks good to me,
Reviewed-by: Rajendra Nayak
>
> Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
>
On Wednesday 18 June 2014 01:32 PM, Roger Quadros wrote:
> On 04/23/2014 08:35 PM, Roger Quadros wrote:
>> From: Nikhil Devshatwar
>>
>> Add hwmods for ocp2scp3 and sata modules.
>From what I see this is actually adding the ocp2scp3 data and fixing up some
of the sata data which is already added
On Wednesday 18 June 2014 05:46 PM, Roger Quadros wrote:
> This module is needed for the SATA and PCIe PHYs.
>
> Signed-off-by: Roger Quadros
> Tested-by: Roger Quadros
> ---
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 25 +
> 1 file changed, 25 insertions(+)
>
>
gt; Cc: Paul Walmsley
> Signed-off-by: Kishon Vijay Abraham I
> Tested-by: Kishon Vijay Abraham I
Looks good to me, feel free to add
Reviewed-by: Rajendra Nayak
> ---
> Please find the bootlog with these hwmod patches
> http://paste.ubuntu.com/7701601/
> arch/arm/mach-omap2/
On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>
> Cc: Tony Lindgren
> Cc: Russell King
> Cc: Paul Walmsley
> Signed-off-by: Kishon Vijay Abraham I
> Tested-by: Kishon Vijay Abraham I
> ---
> Please
On Thursday 19 June 2014 01:20 AM, Roger Quadros wrote:
> This module is needed for the SATA and PCIe PHYs.
>
> Signed-off-by: Roger Quadros
> Tested-by: Roger Quadros
Reviewed-by: Rajendra Nayak
> ---
> v2:
> - added .main_clk to hwmod.
> - moved interface stru
> Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
> is passed as the second memory resource in the device tree.
>
> Signed-off-by: Roger Quadros
> Tested-by: Roger Quadros
Reviewed-by: Rajendra Nayak
> ---
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c |
[]..
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
>> b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
>> new file mode 100644
>> index ..617c7bb25fb1
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
>> @@ -0,0 +1,13 @@
>> +// SPDX-License-Identifier: GPL-2.0
>
>
On 02/14/2018 06:02 AM, Doug Anderson wrote:
> Hi,
>
> On Sun, Feb 11, 2018 at 10:28 PM, Rajendra Nayak
> wrote:
>> Add the qup uart node and geni se instance needed to
>> support the serial console on the MTP.
>>
>> Signed-off-by: Rajendra Nayak
>&g
On 02/15/2018 12:41 AM, Bjorn Andersson wrote:
> [..]
>>> +
>>> + qup_1: geni-se@ac {
>> Color me confused. So you're saying here that this is "qup_1".
>> ...but above you turn the pinmux for pins "GPIO4" and "GPIO5" to
>> "qup9", right? So UART2 is on "qup 1" and "qup 9"?
>>
Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
Signed-off-by: Rajendra Nayak
Reviewed-by: Doug Anderson
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi| 277
Document the compatible string for the Kryo385 cpus found in qualcomm
SoCs.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt
b
Add a SoC string 'sdm845' for the qualcomm SDM845 SoC
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/arm/qcom.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt
b/Documentation/devicetree/bindings/arm/qcom.txt
index
Add the qup uart node and geni se instance needed to
support the serial console on the MTP.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +
arch/arm64/boot/dts/qcom/sdm845.dtsi| 39 +
2 files
fixes based on review
changes in v2:
* dropped cpu-map
* dropped GIC_CPU_MASK_SIMPLE()
* Added new cpu compatible for kryo385
* added ITS node, marked as disabled
Rajendra Nayak (4):
dt-bindings: arm: Document kryo385 cpu
dt-bindings: qcom: Add SDM845 bindings
arm64: dts: sdm845: Add minimal
On 03/10/2018 02:30 AM, Doug Anderson wrote:
> Hi,
>
> On Wed, Feb 21, 2018 at 10:12 PM, Rajendra Nayak
> wrote:
>> + gcc: clock-controller@10 {
>> + compatible = "qcom,gcc-sdm845";
>> +
Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
Signed-off-by: Rajendra Nayak
Reviewed-by: Doug Anderson
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi| 278
Add a SoC string 'sdm845' for the qualcomm SDM845 SoC
Signed-off-by: Rajendra Nayak
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/qcom.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt
b
Document the compatible string for the Kryo385 cpus found in qualcomm
SoCs.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Herring
Reviewed-by: Douglas Anderson
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
for issues reported with 'make dtbs W=2'
* other minor fixes based on review
changes in v2:
* dropped cpu-map
* dropped GIC_CPU_MASK_SIMPLE()
* Added new cpu compatible for kryo385
* added ITS node, marked as disabled
Rajendra Nayak (3):
dt-bindings: arm: Document kryo385 cpu
dt-bindings: qcom: Add
On 03/12/2018 04:59 PM, Marc Zyngier wrote:
> On 12/03/18 08:06, Rajendra Nayak wrote:
>> Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
>>
>> Signed-off-by: Rajendra Nayak
>> Reviewed-by: Doug Anderson
>> ---
>> arch/arm64/boot/dts/qcom/Mak
Document the compatible string for the Kryo385 cpus found in qualcomm
SoCs.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Herring
Reviewed-by: Douglas Anderson
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
, marked as disabled
Rajendra Nayak (3):
dt-bindings: arm: Document kryo385 cpu
dt-bindings: qcom: Add SDM845 bindings
arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
Documentation/devicetree/bindings/arm/qcom.txt
Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
Signed-off-by: Rajendra Nayak
Reviewed-by: Doug Anderson
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi| 276
Add a SoC string 'sdm845' for the qualcomm SDM845 SoC
Signed-off-by: Rajendra Nayak
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/qcom.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt
b
From: Viresh Kumar
This adds a new helper to let the power domain drivers to access
opp->np, so that they can read platform specific properties from the
node.
Signed-off-by: Viresh Kumar
Signed-off-by: Rajendra Nayak
---
drivers/opp/of.c | 19 +++
include/linux/pm_op
at init.
This should/can be removed once we have all clients moved to
be able to vote/unvote for themselves.
Signed-off-by: Rajendra Nayak
---
drivers/soc/qcom/rpmpd.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
index 4058c5b450c6
can easily
be extended by adding data for other qualcomm SoCs as well.
Signed-off-by: Rajendra Nayak
Signed-off-by: Viresh Kumar
---
.../devicetree/bindings/power/qcom,rpmpd.txt | 14 +
drivers/soc/qcom/Kconfig | 9 +
drivers/soc/qcom/Makefile
.
On platforms which don't specify an OPP table the driver falls
back to just setting the clock rates (as is done today)
Signed-off-by: Rajendra Nayak
Signed-off-by: Viresh Kumar
Cc: linux-...@vger.kernel.org
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 41 +
drivers/clk/qcom
-opp bindings document.
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/opp/qcom-opp.txt | 25 ++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/opp/qcom-opp.txt
diff --git a/Documentation/devicetree/bindings/opp/qcom
Add rpmpd device node and its OPP table
Signed-off-by: Rajendra Nayak
Signed-off-by: Viresh Kumar
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 46 +++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom
specific to msm8996 and is tested on the
db820c. We also modify mmc as one of the first devices to move to
using an OPP table and vote on corners using the performance state
infrastructure.
[1] https://lwn.net/Articles/742136/
Rajendra Nayak (6):
soc: qcom: rpmpd: Add a powerdomain driver
With genpd now expecting powerdomain drivers supporting performance
state to support get/set performance state callbacks, add support for it
in the rpmpd driver.
Signed-off-by: Rajendra Nayak
Signed-off-by: Viresh Kumar
---
drivers/soc/qcom/rpmpd.c | 42
On 03/16/2018 10:05 AM, Viresh Kumar wrote:
> On 16-03-18, 09:38, Rajendra Nayak wrote:
>> With genpd now expecting powerdomain drivers supporting performance
>> state to support get/set performance state callbacks, add support for it
>> in the rpmpd driver.
>>
>&
Document the compatible string for the Kryo385 cpus found in qualcomm
SoCs.
Signed-off-by: Rajendra Nayak
Reviewed-by: Rob Herring
Reviewed-by: Douglas Anderson
---
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
Signed-off-by: Rajendra Nayak
Reviewed-by: Doug Anderson
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi| 277
for issues reported with 'make dtbs W=2'
* other minor fixes based on review
changes in v2:
* dropped cpu-map
* dropped GIC_CPU_MASK_SIMPLE()
* Added new cpu compatible for kryo385
* added ITS node, marked as disabled
Rajendra Nayak (4):
dt-bindings: arm: Document kryo385 cpu
dt-bindings: qcom
Add the qup uart node and geni se instance needed to
support the serial console on the MTP.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +
arch/arm64/boot/dts/qcom/sdm845.dtsi| 39 +
2 files
Add a SoC string 'sdm845' for the qualcomm SDM845 SoC
Signed-off-by: Rajendra Nayak
Reviewed-by: Douglas Anderson
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/arm/qcom.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt
b
On 02/19/2018 10:06 PM, Marc Zyngier wrote:
> On Fri, 16 Feb 2018 11:35:02 +0530
> Rajendra Nayak wrote:
>
>> Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
>>
>> Signed-off-by: Rajendra Nayak
>> Reviewed-by: Doug Anderson
>> ---
>>
On 02/22/2018 04:53 AM, Doug Anderson wrote:
> Hi,
>
> On Mon, Feb 19, 2018 at 8:36 AM, Marc Zyngier wrote:
>>> + interrupts = ;
>>
>> Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC
>> binding. Set it to the actual trigger value.
>>
>
>>> +
Update the binding and driver for pmi8994-gpios
Signed-off-by: Rajendra Nayak
---
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 2 ++
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 +
2 files changed, 3 insertions(+)
diff --git a/Documentation/devicetree
On 04/09/2018 09:33 PM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2018-03-15 21:08:22)
>> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
>> b/arch/arm64/boot/dts/qcom/msm8996.dtsi
>> index 0a6f7952bbb1..43757a078146 100644
>> --- a/arch/arm64/boot/dts/qcom
On 03/05/2018 01:29 AM, Bjorn Andersson wrote:
> On Wed 21 Feb 22:12 PST 2018, Rajendra Nayak wrote:
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> [..]
>> +
On 02/07/2018 01:19 AM, Doug Anderson wrote:
> Hi,
>
> On Tue, Feb 6, 2018 at 11:06 AM, Bjorn Andersson
> wrote:
>> On Tue 06 Feb 10:37 PST 2018, Doug Anderson wrote:
>>
>>> Hi,
>>>
>>> On Fri, Jan 26, 2018 at 2:18 PM, Stephen Boyd wrote:
&g
[]..
>>> + };
>>> +
>>> + gcc: clock-controller@10 {
>>> + compatible = "qcom,gcc-sdm845";
>>> + reg = <0x10 0x1f>;
>>> + #clock-cells = <1>;
>>> + #reset-cells = <1>;
>>> +
On 02/07/2018 12:24 AM, Bjorn Andersson wrote:
> On Thu 25 Jan 08:32 PST 2018, Rajendra Nayak wrote:
>> +spmi_bus: qcom,spmi@c44 {
> [..]
>> +};
>> +
>
> While we have the chance, please remove this empty line.
Will do. Thanks
[]..
>> @@ -10,4 +10,46 @@
>> / {
>> model = "Qualcomm Technologies, Inc. SDM845 MTP";
>> compatible = "qcom,sdm845-mtp";
>> +
>> + aliases {
>> + serial0 = _uart2;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0";
>> +
[]..
>> +
>> +#include
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. SDM845";
>
> This should only be in the board level file.
thanks, will fix.
>
>> +
>> + interrupt-parent = <>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen
On 02/07/2018 03:25 AM, Doug Anderson wrote:
> Hi,
>
> On Wed, Jan 31, 2018 at 8:19 AM, Rajendra Nayak wrote:
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> new file mode 100644
>> index ..02520
On 12/28/2017 10:07 AM, Viresh Kumar wrote:
> On 27-12-17, 15:54, Rob Herring wrote:
>> On Wed, Dec 27, 2017 at 2:56 AM, Viresh Kumar
>> wrote:
>>> On 26-12-17, 14:29, Rob Herring wrote:
On Mon, Dec 18, 2017 at 03:51:30PM +0530, Viresh Kumar wrote:
>>>
> +On some platforms the exact
On 07/18/2017 09:12 AM, Frank Rowand wrote:
> Hi Abhijeet,
>
> My qcom-apq8074-dragonboard panics on boot on v4.13-rc1.
>
> I bisected the problem to commit 7f1d4e58dabb, "spmi: pmic-arb:
> optimize table lookups".
there's a fix on its way upstream,
https://patchwork.kernel.org/patch/9810723/
On 1/15/2021 9:45 PM, Bjorn Andersson wrote:
On Thu 24 Dec 05:12 CST 2020, Roja Rani Yarubandi wrote:
While most devices within power-domains which support performance states,
scale the performance state dynamically, some devices might want to
set a static/default performance state while the
On 1/15/2021 8:13 PM, Bjorn Andersson wrote:
On Thu 24 Dec 05:12 CST 2020, Roja Rani Yarubandi wrote:
@@ -629,6 +658,16 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct
device *dev)
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
disable_irq(gi2c->irq);
+
+
On 10/4/2020 3:56 AM, Kuogee Hsieh wrote:
Set link rate by using OPP set rate api so that CX level will be set
accordingly based on the link rate.
Changes in v2:
-- remove dev from dp_ctrl_put() parameters
-- address review comments
This needs to go below '---' and should not be part of the
, and also add the power-domains property to specify
the cx power-domain.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index
For devices which have 'assigned-performance-states' specified in DT,
set the specified performance state during attach and drop it on detach.
Also drop/set as part of runtime suspend/resume callbacks.
Signed-off-by: Rajendra Nayak
---
drivers/base/power/domain.c | 27
scaling the device's performance, also known as DVFS techniques.
Add a property 'assigned-performance-states' which client devices can
use to set this default performance state on their power-domains.
Signed-off-by: Rajendra Nayak
---
.../devicetree/bindings/power/power-domain.yaml| 47
.
Rajendra Nayak (3):
dt-bindings: power: Introduce 'assigned-performance-states' property
PM / Domains: Add support for 'assigned-performance-states'
arm64: dts: sc7180: Add assigned-performance-states for i2c
.../devicetree/bindings/power/power-domain.yaml| 47 ++
arch
On 8/5/2020 12:09 PM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2020-08-04 04:46:54)
While most devices within power-domains which support performance states,
scale the performance state dynamically, some devices might want to
set a static/default performance state while the device
On 8/5/2020 12:11 PM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2020-08-04 04:46:56)
qup-i2c devices on sc7180 are clocked with a fixed clock (19.2 Mhz)
s/Mhz/MHz/
Though qup-i2c does not support DVFS, it still needs to vote for a
performance state on 'cx' to satisfy the 19.2 Mhz clock
'
Instead make it fall through and put back the dropped performance
and bandwidth votes and/or enable back the regulators.
Fixes: cd7ea582 ("opp: Make dev_pm_opp_set_rate() handle freq = 0 to drop
performance votes")
Reported-by: Sajida Bhanu
Signed-off-by: Rajendra Nayak
---
drivers/
On 9/30/2020 1:55 PM, Lukasz Luba wrote:
Hi Douglas,
On 9/30/20 12:53 AM, Doug Anderson wrote:
Hi,
On Tue, Sep 29, 2020 at 5:16 AM Lukasz Luba wrote:
The Energy Model (EM) can store power values in milli-Watts or in abstract
scale. This might cause issues in the subsystems which use the
On 9/30/2020 7:34 PM, Lukasz Luba wrote:
On 9/30/20 11:55 AM, Rajendra Nayak wrote:
On 9/30/2020 1:55 PM, Lukasz Luba wrote:
Hi Douglas,
On 9/30/20 12:53 AM, Doug Anderson wrote:
Hi,
On Tue, Sep 29, 2020 at 5:16 AM Lukasz Luba wrote:
The Energy Model (EM) can store power values
On 9/30/2020 1:54 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2020-09-29 10:10:26)
Set link rate by using OPP set rate api so that CX level will be set
accordingly base on the link rate.
s/base/based/
Signed-off-by: Kuogee Hsieh
---
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c
Add device tree binding Documentation details for Qualcomm SC7280
TLMM block.
Signed-off-by: Rajendra Nayak
---
.../bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 170 +
1 file changed, 170 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7280 SoC
Signed-off-by: Rajendra Nayak
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom/Makefile |1 +
drivers/pinctrl/qcom/pinctrl-sc7280.c | 1717
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