Yeah sure Stephen.
On 5/5/2018 8:21 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-03 02:09:57)
Hello Stephen,
I have tested the below patch & didn't see any issues.
Alright. Thanks! Can I take that as a "Tested-by"?
--
QUALCOMM INDIA, on behalf of Qualcomm Innovati
Hello Stephen,
Could you please let me know your comments on the below.
On 5/4/2018 10:21 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-04 03:02:38)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
new file mode 100644
index 000..944fe04
--- /dev/null
+++ b
send requests for the RPMh managed clock resources.
The RPMh clock driver depends upon the RPMh driver [1] and command DB
driver [2] which are both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (1):
clk: qcom: clk-
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c
iver [2] which are both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (1):
clk: qcom: clk-rpmh: Add QCOM RPMh clock driver
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/q
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c
ischal <anisc...@codeaurora.org>
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 42 ++
drivers/clk/qcom/gdsc.h | 1 +
2 files changed, 27 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drive
Hello Stephen,
Thanks for your review comments, please check my comments below, so
that I could submit the next patch series.
On 5/8/2018 5:58 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-07 03:48:06)
Hello Stephen,
Could you please let me know your comments on the below.
On 5/4
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for hanging the frequency of CPUs. The driver implements the cpufreq driver
interface for this firmware.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drivers/cpufreq/Kconfig.arm | 9 ++
drivers/c
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
.../bindings/cpufreq/cpufreq-qcom-fw.txt
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for hanging the frequency of CPUs. The driver implements the cpufreq driver
interface for this firmware.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM CPUFREQ FW bindings
cpufreq: qcom-fw: Add support for QCOM
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this firmware.
Signed-off-by: Saravana Kannan <skan...@codeaurora.org>
Signed-off-by: Taniya Das <t...@codeaurora.org>
[v2]
* Address comments given in v0 series.
[v1]
* Fixed compilation reported by Amit K.
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this firmware.
Taniya Das (2
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
.../bindings/cpufreq/cpufreq-qcom-fw.txt
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
.../bindings/cpufreq/cpufreq-qcom-fw.txt
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this firmware.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drivers/cpufreq/Kconfig.arm | 9 ++
drivers/c
[v1]
* Fixed compilation reported by Amit K.
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq driver
interface for this firmware.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM CPUFREQ FW
Hi Viresh,
Thanks for the review comments, I have already fixed the resource
comment in the v1 series which I sent across. I will fix the rest of the
comments and send it for review.
On 5/17/2018 3:44 PM, Viresh Kumar wrote:
On 17-05-18, 15:00, Taniya Das wrote:
The CPUfreq FW present
Hello Viresh,
Thanks for your comments.
On 5/22/2018 12:36 AM, skan...@codeaurora.org wrote:
On 2018-05-21 02:01, Viresh Kumar wrote:
On 19-05-18, 23:04, Taniya Das wrote:
The CPUfreq FW present in some QCOM chipsets offloads the steps
necessary
for changing the frequency of CPUs
On 5/23/2018 8:43 PM, Sudeep Holla wrote:
On 19/05/18 18:34, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
Signed-off-by: Taniya Das &l
h Kumar <viresh.ku...@linaro.org> wrote:
On 22-05-18, 14:31, Rob Herring wrote:
On Sat, May 19, 2018 at 11:04:50PM +0530, Taniya Das wrote:
+ freq-domain-0 {
+ compatible = "cpufreq";
+ reg = <0x17d43920 0x4>,
+
to identify if dfs mode is enabled.
In the cases where a RCG requires a Dynamic Frequency switch support
requires to register which would at runtime read the clock perf level
registers to identify the frequencies supported and update the frequency
table accordingly.
Taniya Das (1):
clk: qcom
In the cases where a RCG requires a Dynamic Frequency switch support
requires to register which would at runtime read the clock perf level
registers to identify the frequencies supported and update the frequency
table accordingly.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drive
Hello Viresh,
Sure, will do it next time. Hope updating the fixes in this email is
fine. Do let me know in case you need me to send it across again the
series with cover letter updated.
On 5/21/2018 11:35 AM, Viresh Kumar wrote:
On 19-05-18, 23:04, Taniya Das wrote:
[v2]
* Address
ree bindings.
[v1]
* Fixed compilation reported by Amit K.
Taniya Das (2):
dt-bindings: cpufreq: Introduce QCOM CPUFREQ FW bindings
cpufreq: qcom-fw: Add support for QCOM cpufreq FW driver
.../bindings/cpufreq/cpufreq-qcom-fw.txt | 173 +++
drivers/cpufreq/Kconfig.arm
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this firmware.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 9 +
drivers
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-fw.txt | 173 +
1 file
Hello Stephen,
Thanks for review.
On 6/12/2018 1:25 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-06-04 00:56:25)
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
new file mode 100644
index 000..317ab33
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sdm845
Frequency table macro is used by multiple clock drivers, move frequency
table macro to common header file.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h | 2 ++
drivers/clk/qcom/gcc-apq8084.c | 2 --
drivers/clk/qcom/gcc-ipq4019.c | 2 --
drivers/clk/qcom/gcc-ipq8074.c | 2
Frequency table macro is used by multiple clock drivers, move frequency
table macro to common header file.
Change-Id: I78d76f04b6c335c05dd9325025be7db1e99cbeac
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h| 2 ++
drivers/clk/qcom/gcc-apq8084.c| 2 --
drivers/clk/qcom/gcc
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sdm845.c
. This would allow display drivers to probe and
control their clocks.
The Display clock driver depends on the frequency table macro
movement to a common file [1].
[1]: https://lkml.org/lkml/2018/6/13/216
Taniya Das (2):
dt-bindings: clock: Introduce QCOM Display clock bindings
clk: qcom: Add display
Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock/qcom,dispcc.txt | 19 +
include/dt-bindings/clock/qcom,dispcc-sdm845.h | 45
Hello Sudeep,
Thanks for review comments.
On 6/13/2018 4:56 PM, Sudeep Holla wrote:
On 12/06/18 12:02, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware
Hello Sudeep,
Thanks for your comments.
On 6/14/2018 4:17 PM, Sudeep Holla wrote:
On 13/06/18 19:13, Taniya Das wrote:
Hello Sudeep,
Thanks for review comments.
On 6/13/2018 4:56 PM, Sudeep Holla wrote:
[...]
You are bit inconsistent on the wordings. Some places you refer
On 6/15/2018 5:29 PM, Amit Kucheria wrote:
On Thu, Jun 14, 2018 at 9:24 PM, Taniya Das wrote:
Sorry Sudeep I missed replying to your earlier query.
The High level OS(HLOS) would require to access only these specific
registers from this IP block and just mapping the whole block(huge
region
On 6/15/2018 6:53 PM, Sudeep Holla wrote:
On 14/06/18 19:24, Taniya Das wrote:
Hello Sudeep,
Thanks for your comments.
On 6/14/2018 4:17 PM, Sudeep Holla wrote:
On 13/06/18 19:13, Taniya Das wrote:
Hello Sudeep,
Thanks for review comments.
On 6/13/2018 4:56 PM, Sudeep Holla wrote
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,lpasscc.txt | 46 ++
include/dt-bindings/clock/qcom,lpass-sdm845.h | 18 +
2
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 ++
drivers/clk/qcom/Makefile | 1
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this firmware.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 9 ++
drivers
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-fw.txt | 173 +
1 file
device tree bindings.
[v1]
* Fixed compilation reported by Amit K.
Taniya Das (2):
dt-bindings: cpufreq: Introduce QCOM CPUFREQ FW bindings
cpufreq: qcom-fw: Add support for QCOM cpufreq FW driver
.../bindings/cpufreq/cpufreq-qcom-fw.txt | 173 +++
drivers/cpufreq/
Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,dispcc.txt | 19 +
include/dt-bindings/clock/qcom,dispcc-sdm845.h | 45 ++
2 files changed, 64
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM Display clock bindings
clk: qcom: Add display clock controller driver for SDM845
.../devicetree
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sdm845.c
Hello Viresh,
Thank you for the review comments.
On 6/6/2018 11:31 AM, Viresh Kumar wrote:
On 04-06-18, 16:16, Taniya Das wrote:
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface
Hello Sudeep,
Thanks for the review comments.
On 6/4/2018 4:25 PM, Sudeep Holla wrote:
On Mon, Jun 04, 2018 at 04:16:33PM +0530, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which
Hello Rob,
Could you please suggest if the below looks okay to be implemented?
On 5/24/2018 11:13 AM, Viresh Kumar wrote:
On 24-05-18, 10:48, Taniya Das wrote:
Hello Rob, Viresh,
Thank you for the comments. If I understand correctly, the device tree nodes
should look something like the below
Frequency table macro is used by multiple clock drivers, move frequency
table macro to common header file.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h| 2 ++
drivers/clk/qcom/gcc-apq8084.c| 2 --
drivers/clk/qcom/gcc-ipq4019.c| 2 --
drivers/clk/qcom/gcc-ipq8074.c
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sdm845.c
Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock/qcom,dispcc.txt | 19 +
include/dt-bindings/clock/qcom,dispcc-sdm845.h | 45
update the Kconfig.
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Taniya Das (3):
clk: qcom: Move frequency table macro to common file
dt-bindings: clock: Introduce QCOM Display clock bindings
clk
Hello Stephen,
Thanks for the comments.
On 6/19/2018 8:53 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-06-13 03:33:15)
[v2]
* Removed unused header file includes.
* Moved the frequency table macro to a common file [1].
* Move to pll config to probe.
* Update SoC name
/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (2):
dt-bindings: clock: Introduce QCOM RPMh clock bindings
clk: qcom: clk-rpmh: Add QCOM RPMh clock driver
.../devicetree/bindings/clock/qcom,rpmh-clk.txt| 53 +++
drivers/clk/qcom/Kconfig | 9 +
dri
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource state requests to control
the clocks managed by RPMh.
Signed-off-by: Taniya Das <t...@codeaurora.org>
Reviewed-by: Rob Herring <r...@kernel.org>
---
.../devicet
Thanks Stephen for the comments.
On 5/2/2018 2:57 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-01 01:41:33)
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Amit Nischal <anisc...@codeaurora.
In the cases where a RCG requires a Dynamic Frequency switch support
requires to register which would at runtime read the clock perf level
registers to identify the frequencies supported and update the frequency
table accordingly.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drive
Hello Stephen,
I have tested the below patch & didn't see any issues.
On 5/2/2018 12:27 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-04-30 22:03:33)
@@ -45,15 +50,28 @@
#define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
-static int gdsc_is_enabled(struct gdsc
Hello Doug,
Thanks for the comments, I have based my latest patch on top of the
earlier patches (clk-qcom-sdm845 branch of clk-next).
On 5/1/2018 12:12 AM, Doug Anderson wrote:
Hi,
On Fri, Apr 27, 2018 at 1:19 AM, Taniya Das <t...@codeaurora.org> wrote:
-static int gdsc_is_enabled(
ischal <anisc...@codeaurora.org>
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 42 ++
drivers/clk/qcom/gdsc.h | 1 +
2 files changed, 27 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/qcom/gdsc.c b/drive
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource state requests to control
the clocks managed by RPMh.
Signed-off-by: Amit Nischal <anisc...@codeaurora.org>
Signed-off-by: Taniya Das <t...@codeaurora.org>
Revi
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Amit Nischal <anisc...@codeaurora.org>
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 9 +
driv
Hello Stephen,
Thanks for the review comments.
On 4/27/2018 5:10 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-04-24 05:23:19)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
new file mode 100644
index 000..907a73f
--- /dev/null
+++ b/drivers/clk/qcom/clk-rpmh.c
send requests for the RPMh managed clock resources.
The RPMh clock driver depends upon the RPMh driver [1] and command DB
driver [2] which are both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (2):
dt-bind
On 5/1/2018 6:13 PM, Rob Herring wrote:
On Tue, May 01, 2018 at 02:11:33PM +0530, Taniya Das wrote:
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Amit Nischal <anisc...@codeaurora.org>
Sign
both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (1):
clk: qcom: clk-rpmh: Add QCOM RPMh clock driver
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c |
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Taniya Das <t...@codeaurora.org>
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c
Hello Stephen,
Thanks for review.
On 5/2/2018 9:00 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-02 03:51:17)
+ ret = devm_clk_hw_register(>dev, hw_clks[i]);
+ if (ret) {
+ dev_err(>dev, "failed to re
On 6/18/2018 2:51 PM, Sudeep Holla wrote:
On 15/06/18 18:40, Taniya Das wrote:
On 6/15/2018 5:29 PM, Amit Kucheria wrote:
[...]
A future version of the HW engine, or more likely, a firmware
revision, will make more functionality available. Say, this needs
access to another register
On 6/19/2018 3:04 PM, Sudeep Holla wrote:
On 19/06/18 08:53, Taniya Das wrote:
On 6/18/2018 2:51 PM, Sudeep Holla wrote:
On 15/06/18 18:40, Taniya Das wrote:
On 6/15/2018 5:29 PM, Amit Kucheria wrote:
[...]
A future version of the HW engine, or more likely, a firmware
revision
On 6/19/2018 2:24 PM, Viresh Kumar wrote:
Sorry for being late..
On 07-06-18, 12:48, Taniya Das wrote:
On 6/6/2018 11:31 AM, Viresh Kumar wrote:
On 04-06-18, 16:16, Taniya Das wrote:
+static struct cpufreq_driver cpufreq_qcom_fw_driver = {
+ .flags = CPUFREQ_STICKY
On 7/7/2018 5:12 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-04 23:55:20)
diff --git a/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
b/Documentation/devicetree/bindings/clock/qcom,lpasscc.txt
new file mode 100644
index 000..fe7378b
--- /dev/null
+++ b/Documentation
On 7/7/2018 5:09 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-04 23:55:21)
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c
b/drivers/clk/qcom/lpasscc-sdm845.c
new file mode 100644
index 000..5285b26
--- /dev/null
+++ b/drivers/clk/qcom/lpasscc-sdm845.c
@@ -0,0 +1,243 @@
+// SPDX
tree flag.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sdm845.c | 35 +++
drivers/clk/qcom/lpasscc-sdm845.c | 189 ++
4 files changed, 234 insertions
Add device tree bindings for Low Power Audio subsystem clock controller for
Qualcomm Technology Inc's SDM845 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt | 2 ++
.../devicetree/bindings/clock/qcom,lpasscc.txt | 33 ++
include/dt
M845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM LPASS clock bindings
clk: qcom: Add lpass clock controller driver for SDM845
.../devicetree/bindings/clock/
On 7/27/2018 3:35 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-23 03:54:35)
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
This is fine to merge as long
QUPv3 clocks support DFS and thus register the RCGs which require support
for the same.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sdm845.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index
-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h | 2 +
drivers/clk/qcom/clk-rcg2.c | 224
2 files changed, 226 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index dbd5a9e..e6300e0 100644
--- a/drivers/clk/qcom
here a RCG requires a Dynamic Frequency switch support
requires to register which would at runtime read the clock perf level
registers to identify the frequencies supported and update the frequency
table accordingly.
Taniya Das (2):
clk: qcom: Add support for RCG to register for DFS
clk: qcom:
On 8/8/2018 12:54 AM, skan...@codeaurora.org wrote:
On 2018-08-07 04:12, Sudeep Holla wrote:
On Mon, Aug 06, 2018 at 01:54:24PM -0700, skan...@codeaurora.org wrote:
On 2018-08-03 16:46, Stephen Boyd wrote:
>Quoting Taniya Das (2018-07-24 03:42:49)
>>diff --git
>>a/Documenta
On 8/8/2018 11:52 AM, Stephen Boyd wrote:
Quoting skan...@codeaurora.org (2018-08-06 13:46:05)
On 2018-08-03 15:24, Stephen Boyd wrote:
Quoting skan...@codeaurora.org (2018-08-03 12:52:48)
On 2018-08-03 12:40, Evan Green wrote:
Hi Taniya,
On Tue, Jul 24, 2018 at 3:44 AM Taniya Das wrote
Hello Craig,
Could you please correct the authorship and also provide the reference
to code where this is picked from?
On 8/11/2018 1:51 AM, Craig Tatlor wrote:
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to
/dt-bindings/clock/qcom,gcc-sdm845.h | 3 +++
1 file changed, 3 insertions(+)
Acked-by: Rob Herring
Reviewed-by: Taniya Das
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core_clk.clkr,
+ [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = _qspi_cnoc_periph_ahb_clk.clkr,
};
static const struct qcom_reset_map gcc_sdm845_resets[] = {
Reviewed-by: Taniya Das
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
Hello Stephen,
Thanks for the changes, I have tested the changes and would require the
change mentioned below for this to work.
On 8/18/2018 11:31 PM, Taniya Das wrote:
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das
On 8/28/2018 2:34 AM, Stephen Boyd wrote:
Quoting Stephen Boyd (2018-08-23 11:25:41)
Quoting Taniya Das (2018-08-22 03:28:31)
H. Ok. That won't work then. recalc_rate() better not try to
populate the frequency table then or it will not work. So I suppose it
needs to fallback
On 8/21/2018 9:00 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-21 04:36:20)
On 8/18/2018 11:31 PM, Taniya Das wrote:
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
[v4]
* Add
Hello Stephen,
I will test these changes and get back.
On 8/18/2018 7:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-10 18:53:54)
[v4]
* Add recalc_clk_ops to calculate the clock frequency reading the current
perf state, also add CLK_GET_RATE_NOCACHE flag.
* Cleanup 'goto
added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove initialization of 'index'
* Check for valid 'c'
* Removed initialization of 'prev_cc' from 'qcom_read_lut'.
Taniya Das (2):
dt-bindings: cpufreq: Introduce QCOM CPUFREQ Firmware bin
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +
1
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 11
Hello Stephen,
Thanks for the review comments.
On 7/13/2018 5:14 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-07-12 11:05:45)
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface
Hello Stephen,
Thanks for your review comments.
On 7/9/2018 12:34 PM, Stephen Boyd wrote:
Quoting Taniya Das (2018-06-28 04:47:30)
Dynamic Frequency switch is a feature of clock controller by which request
from peripherals allows automatic switching frequency of input clock.
There are various
SPDX headers updated for common/branch/pll/regmap files.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-alpha-pll.c | 10 +-
drivers/clk/qcom/clk-alpha-pll.h | 14 ++
drivers/clk/qcom/clk-branch.c| 10 +-
drivers/clk/qcom/clk-branch.h| 14
-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h | 2 +
drivers/clk/qcom/clk-rcg2.c | 173
2 files changed, 175 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index b209a2f..bffb625 100644
--- a/drivers/clk/qcom
QUPv3 clocks support DFS and thus register the RCGs which require support
for the same.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sdm845.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index
dfs mode is enabled.
In the cases where a RCG requires a Dynamic Frequency switch support
requires to register which would at runtime read the clock perf level
registers to identify the frequencies supported and update the frequency
table accordingly.
Taniya Das (2):
clk: qcom: Add support for
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