uot; for dev_err and
also for "qcom_cpu_resources_init".
* Removed ret = 0 from qcom_get_related_cpus and added to check for
cpu_mask_empty to return -ENOENT.
* Fixes qcom_cpu_resources_init function
* Remove initialization of 'index'
* Check for valid 'c
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by the hardware engine.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 +++
The CPUfreq HW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this hardware engine.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 11
Hello Viresh,
Thanks for your comments.
On 5/22/2018 12:36 AM, skan...@codeaurora.org wrote:
On 2018-05-21 02:01, Viresh Kumar wrote:
On 19-05-18, 23:04, Taniya Das wrote:
The CPUfreq FW present in some QCOM chipsets offloads the steps
necessary
for changing the frequency of CPUs. The
at 12:48 AM, Viresh Kumar wrote:
On 22-05-18, 14:31, Rob Herring wrote:
On Sat, May 19, 2018 at 11:04:50PM +0530, Taniya Das wrote:
+ freq-domain-0 {
+ compatible = "cpufreq";
+ reg = <0x17d43920 0x4>,
+
On 5/23/2018 8:43 PM, Sudeep Holla wrote:
On 19/05/18 18:34, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
Signed-off-by: Taniy
From: Amit Nischal
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource state requests to control
the clocks managed by RPMh.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock
From: Amit Nischal
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: David Collins
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom
Hello,
This patch series adds a driver and device tree documentation binding
for the clock control via Resource Power Manager-hardened (RPMh) on some
Qualcomm Technologies, Inc, SoCs such as SDM845. The clock RPMh driver
would send requests for the RPMh managed clock resources.
The RPMh clock dri
,
especially in the disable sequence, where the status bit
will be cleared even before the core is completely power
collapsed. On targets with this issue, poll the power on/off
bits in the CFG_GDSCR register instead to correctly determine
the GDSC state.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya
Hello Doug,
Thanks for the comments, I have based my latest patch on top of the
earlier patches (clk-qcom-sdm845 branch of clk-next).
On 5/1/2018 12:12 AM, Doug Anderson wrote:
Hi,
On Fri, Apr 27, 2018 at 1:19 AM, Taniya Das wrote:
-static int gdsc_is_enabled(struct gdsc *sc, unsigned
,
especially in the disable sequence, where the status bit
will be cleared even before the core is completely power
collapsed. On targets with this issue, poll the power on/off
bits in the CFG_GDSCR register instead to correctly determine
the GDSC state.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya
Hello Stephen,
Thanks for the review comments.
On 4/27/2018 5:10 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-04-24 05:23:19)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
new file mode 100644
index 000..907a73f
--- /dev/null
+++ b/drivers/clk/qcom/clk-rpmh.c
send requests for the RPMh managed clock resources.
The RPMh clock driver depends upon the RPMh driver [1] and command DB
driver [2] which are both still undergoing review.
Thanks,
Taniya
[1]: https://lkml.org/lkml/2018/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (2):
dt-bind
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource state requests to control
the clocks managed by RPMh.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk
On 5/1/2018 6:13 PM, Rob Herring wrote:
On Tue, May 01, 2018 at 02:11:33PM +0530, Taniya Das wrote:
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
---
drivers/clk
Thanks Stephen for the comments.
On 5/2/2018 2:57 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-05-01 01:41:33)
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Amit Nischal
Signed-off-by: Taniya Das
Add RPMh clock device bindings for Qualcomm Technology Inc's SoCs. These
devices would be used for communicating resource state requests to control
the clocks managed by RPMh.
Signed-off-by: Taniya Das
Reviewed-by: Rob Herring
---
.../devicetree/bindings/clock/qcom,rpmh-clk.txt
/3/9/979
[2]: https://lkml.org/lkml/2018/3/14/787
Taniya Das (2):
dt-bindings: clock: Introduce QCOM RPMh clock bindings
clk: qcom: clk-rpmh: Add QCOM RPMh clock driver
.../devicetree/bindings/clock/qcom,rpmh-clk.txt| 53 +++
drivers/clk/qcom/Kconfig | 9 +
dri
Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 366
In the cases where a RCG requires a Dynamic Frequency switch support
requires to register which would at runtime read the clock perf level
registers to identify the frequencies supported and update the frequency
table accordingly.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h | 7
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sdm845.c
Add device tree bindings for display clock controller for Qualcomm
Technology Inc's SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,dispcc.txt | 19 +
include/dt-bindings/clock/qcom,dispcc-sdm845.h | 45 ++
2 files change
Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Taniya Das (2):
dt-bindings: clock: Introduce QCOM Display clock bindings
clk: qcom: Add display clock controller driver for SDM845
.../devicetree
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for this firmware.
Signed-off-by: Saravana Kannan
Signed-off-by: Taniya Das
---
drivers/cpufreq/Kconfig.arm | 9 ++
drivers
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions which are
controlled by firmware.
Signed-off-by: Taniya Das
---
.../bindings/cpufreq/cpufreq-qcom-fw.txt | 173 +
1
le_exit as this driver would not be used as module, also updated
the Kconfig to bool from tristate.
* Updated the subsystem in device tree bindings.
[v1]
* Fixed compilation reported by Amit K.
Taniya Das (2):
dt-bindings: cpufreq: Introduce QCOM CPUFREQ FW bindings
cpufreq: qcom-f
Hello Viresh,
Thank you for the review comments.
On 6/6/2018 11:31 AM, Viresh Kumar wrote:
On 04-06-18, 16:16, Taniya Das wrote:
The CPUfreq FW present in some QCOM chipsets offloads the steps necessary
for changing the frequency of CPUs. The driver implements the cpufreq
driver interface for
Hello Sudeep,
Thanks for the review comments.
On 6/4/2018 4:25 PM, Sudeep Holla wrote:
On Mon, Jun 04, 2018 at 04:16:33PM +0530, Taniya Das wrote:
Add QCOM cpufreq firmware device bindings for Qualcomm Technology Inc's
SoCs. This is required for managing the cpu frequency transitions
Add the bindings for sc7280 and support the rpmh clock which
are required to be supported on SC7280.
Taniya Das (2):
dt-bindings: clock: Add RPMHCC bindings for SC7280
clk: qcom: rpmh: Add support for RPMH clocks on SC7280
.../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
drivers
Add bindings and update documentation for clock rpmh driver on SC7280.
Signed-off-by: Taniya Das
---
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
b/Documentation/devicetree
Add support for RPMH clocks on SC7280 SoCs.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rpmh.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 6a2a13c..c180959 100644
--- a
Thanks Rob for your review comments.
diff --git a/include/dt-bindings/clock/qcom,gcc-sc7280.h
b/include/dt-bindings/clock/qcom,gcc-sc7280.h
new file mode 100644
index 000..3295bd4
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sc7280.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier:
Thanks Stephen for your review comments.
On 1/13/2021 1:36 AM, Stephen Boyd wrote:
+ clock-names:
+items:
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+ - const: sleep_clk
+ - const: pcie_0_pipe_clk
+ - const: pcie_1_pipe_clk
+ - const: usb3_phy_wrapper_gcc_usb30_
Thanks Stephen for your review comments.
On 1/13/2021 1:34 AM, Stephen Boyd wrote:
+
+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x7500c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_8,
+ .freq_tbl = ftbl_gcc_sdcc1_apps_cl
QSPI/WPSS/MSS/LPASS/PCIE clocks.
* Update the floor rcg ops for SDCC/QSPI clock.
* Add comment for cpuss critical clocks.
[v1]
* Documentation binding for GCC clock for SC7280.
* GCC clock driver for SC7280.
Taniya Das (2):
dt-bindings: clock: Add SC7280 GCC clock binding
clk: qcom: Add Gl
Add device tree bindings for global clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc-sc7280.yaml | 92 +
include/dt-bindings/clock/qcom,gcc-sc7280.h| 226 +++
Add support for the global clock controller found on SC7280
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc
[v2]
- Update the node in sorted order.
- Depends on the patch
https://lore.kernel.org/r/20200731133006.1.Iee81b115f5be50d6d69500fe1bda11bba6e16143@changeid
[v1]
- Clock controller LPASS device Node.
Taniya Das (1):
arm64: dts: qcom: sc7180: Add LPASS clock controller nodes
arch/arm64
Update the clock controller nodes for Low power audio subsystem
functionality.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom
Hi Stephen,
On 8/6/2020 1:54 AM, Stephen Boyd wrote:
Quoting Taniya Das (2020-07-24 09:07:58)
+
+static struct clk_rcg2 core_clk_src = {
+ .cmd_rcgr = 0x1d000,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = lpass_core_cc_parent_map_2,
+ .clkr.hw.init
On 12/11/2020 12:40 PM, Stephen Boyd wrote:
Quoting Vinod Koul (2020-12-10 21:43:49)
On 10-12-20, 12:43, Stephen Boyd wrote:
+static struct clk_branch gcc_camera_ahb_clk = {
+ .halt_reg = 0x26004,
+ .halt_check = BRANCH_HALT_DELAY,
+ .hwcg_reg = 0x26004,
+ .hwcg_bit =
clk ones")
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sc7180.c | 21 +++--
1 file changed, 3 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index d82d725..b05901b 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++
Update the RCGs to use shared ops to park the RCGs at XO.
Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for
SC7180")
Signed-off-by: Taniya Das
---
drivers/clk/qcom/camcc-sc7180.c | 50 -
1 file changed, 25 inserti
Hello Stephen,
Thanks for your review.
On 3/14/2021 4:29 AM, Stephen Boyd wrote:
Quoting Taniya Das (2021-03-11 04:51:32)
The root clock generators with MND divider has the capability to support
change in duty-cycle by updating the 'D'. Add the clock ops which would
check all th
Add support for display, video & graphics clock controllers on SC7280
along with the bindings for each of the clock controllers.
Taniya Das (6):
dt-bindings: clock: Add SC7280 DISPCC clock binding
clk: qcom: Add display clock controller driver for SC7280
dt-bindings: clock: Add SC7280 G
Add device tree bindings for video clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,videocc.yaml| 4 +++-
include/dt-bindings/clock/qcom,videocc-sc7280.h| 27 ++
2
Add support for the display clock controller found on SC7280
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sc7280.c
Add device tree bindings for display clock controller subsystem for
Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7280-dispcc.yaml | 94 ++
include/dt-bindings/clock/qcom,dispcc-sc7280.h | 55 +
2
Add support for the graphics clock controller found on SC7280
based devices. This would allow graphics drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gpucc-sc7280.c | 491
Add support for the video clock controller found on SC7280
based devices. This would allow video drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sc7280.c | 372
Add device tree bindings for graphics clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gpucc.yaml | 4 ++-
include/dt-bindings/clock/qcom,gpucc-sc7280.h | 35 ++
2
.
Thus park the RCGs at XO during clock disable and update the rcg_ops to
use the shared_ops.
Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for
SC7180")
Signed-off-by: Taniya Das
---
drivers/clk/qcom/camcc-sc7180.c | 50 ---
Thanks Stephen for the review.
On 3/23/2021 12:59 PM, Stephen Boyd wrote:
Quoting Taniya Das (2021-03-19 00:47:34)
Update the RCGs to use shared ops to park the RCGs at XO.
s/Update/fix/?
Can you also elaborate more on why we need to park the RCGs here for all
these different clks? Is the
Hi Bjorn,
On 1/21/2021 12:35 AM, Bjorn Andersson wrote:
On Wed 20 Jan 12:25 CST 2021, Taniya Das wrote:
The CPUFREQ-HW driver is intended to be used only for CPUFREQ HW designs
where the firmware programs the look up tables.
It's obvious that this is the intended target for the cu
On 4/13/2021 9:19 AM, Viresh Kumar wrote:
On 12-04-21, 15:01, Taniya Das wrote:
Technically the HW we are trying to program here differs in terms of
clocking, the LUT definitions and many more. It will definitely make
debugging much more troublesome if we try to accommodate multiple versions
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Add the LPASS clock IDs for
LPASS PIL client to request for the clocks.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7280-lpasscc.yaml| 69
Add support for the lpass clock controller found on SC7280 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 8 ++
drivers/clk/qcom/Makefile | 1
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SC7280 SoCs.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280
Add support for the video, gpu, display, lpass clock controller
device nodes for SC7280 SoC.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 58
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch
Add device node for cpufreq HW and clock controllers of GPU, DISP, VIDEO, LPASS.
The clock controller nodes are dependent on the following
VIDEO/DISP/GPU: https://lkml.org/lkml/2021/3/16/1624
LPASS: https://lkml.org/lkml/2021/4/9/812
Taniya Das (2):
arm64: dts: qcom: sc7280: Add cpufreq hw
Hi Vinod,
On 12/4/2020 10:05 AM, Vinod Koul wrote:
Hi Bjorn,
On 03-12-20, 18:06, Bjorn Andersson wrote:
On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
[..]
+static int gcc_sm8350_probe(struct platform_device *pdev)
Reviewed-by: Taniya Das
On 2/24/2021 11:20 PM, Douglas Anderson wrote:
While picking commit a8cd989e1a57 ("mmc: sdhci-msm: Warn about
overclocking SD/MMC") back to my tree I was surprised that it was
reporting warnings. I thought I fixed those! Looking closer at the
fix, I see that
Hello Stephen,
Thanks for the review.
On 2/23/2021 1:13 PM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-02-11 23:28:43)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 7848e88..10851e7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/
There are intermittent GDSC power-up failures observed for titan top
gdsc, which requires the XO clock. Thus mark all the MM XO clocks always
enabled from probe.
Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of
clk ones")
Signed-off-by: Taniya Das
---
d
The CPUFREQ-HW driver is intended to be used only for CPUFREQ HW designs
where the firmware programs the look up tables.
Suggestion is to separate out the driver where the programming is
managed by high level OS.
On 1/19/2021 11:15 PM, AngeloGioacchino Del Regno wrote:
On new SoCs (SDM845 on
Hi Bjorn,
On 1/21/2021 4:10 AM, Bjorn Andersson wrote:
On Wed 20 Jan 01:47 CST 2021, Taniya Das wrote:
There are intermittent GDSC power-up failures observed for titan top
gdsc, which requires the XO clock. Thus mark all the MM XO clocks always
enabled from probe.
But if this is the reason
The bi_tcxo clock source for SC7280 requires a div 4 to derive 19.2MHz
from the xo_board. Thus update the same.
Fixes: fff2b9a65162 ("clk: qcom: rpmh: Add support for RPMH clocks on SC7280")
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rpmh.c | 7 +--
1 file changed, 5
The root clock generators with MND divider has the capability to support
change in duty-cycle by updating the 'D'. Add the clock ops which would
check all the boundary conditions and enable setting the desired duty-cycle
as per the consumer.
Signed-off-by: Taniya Das
---
drivers/cl
The root clock generators with MND divider has the capability to support
change in duty-cycle by updating the 'D'. Add the clock ops which would
check all the boundary conditions and enable setting the desired duty-cycle
as per the consumer.
Signed-off-by: Taniya Das
---
drivers/cl
Add device tree bindings for global clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc-sc7280.yaml | 85
include/dt-bindings/clock/qcom,gcc-sc7280.h| 215 +++
Add support for the global clock controller found on SC7280
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc
Add driver support for Global Clock controller for SC7280 and also update
device tree bindings for the various clocks supported in the clock controller.
Taniya Das (2):
dt-bindings: clock: Add SC7280 GCC clock binding
clk: qcom: Add Global Clock controller (GCC) driver for SC7280
The LPASSCC driver's suspend/resume is invoked multiple number of times
and thus allow the device to autosuspend for 500ms.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/lpasscorecc-sc7180.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clk
Update global clock controller SDCC2/4 clocks to use the floor rcg ops,
so as to use the rounded down clock rates for these clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-ipq8074.c | 2 +-
drivers/clk/qcom/gcc-msm8998.c | 4 ++--
drivers/clk/qcom/gcc-qcs404.c | 2 +-
drivers/clk
Hi Stephen, Vinod,
On 9/7/2019 2:08 AM, Stephen Boyd wrote:
Quoting Vinod Koul (2019-09-05 21:56:59)
Update the gcc qcs404 clock driver to use floor ops for sdcc clocks. As
disuccsed in [1] it is good idea to use floor ops for sdcc clocks as we
dont want the clock rates to do round up.
[1]:
h
.
Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for
SDM845")
Reported-by: Douglas Anderson
Cc: Taniya Das
Signed-off-by: Stephen Boyd
---
I suppose we need to do this for all the sdc clks in qcom driver?
Seems like a good idea to me.
drivers/clk/q
On 8/15/2019 9:30 PM, Stephen Boyd wrote:
These aren't useful and they reference the init structure name. Let's
just drop them.
Cc: Taniya Das
Signed-off-by: Stephen Boyd
---
Acked-by: Taniya Das
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a memb
oth these problems so that clk provider drivers can use the new
style of parent mapping without having to also update their DT at the
same time. This patch is based on an earlier patch from Taniya Das which
checked for -EINVAL in addition to -ENOENT return values from
clk_core_get().
Fixes: 601b6e
On 9/4/2019 4:17 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-09-03 08:52:12)
Hi,
On 8/31/2019 3:04 AM, Doug Anderson wrote:
Hi,
On Fri, Aug 30, 2019 at 12:51 PM Stephen Boyd wrote:
Some MMC cards fail to enumerate properly when inserted into an MMC slot
on sdm845 devices. This is
Hello Rob,
Thank you for your review comments.
On 8/20/2019 12:44 AM, Rob Herring wrote:
On Mon, Aug 19, 2019 at 11:38 AM Taniya Das wrote:
The GCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those. Also update
the compatible
Hi Stephen,
Thanks for your review.
On 8/21/2019 11:31 PM, Stephen Boyd wrote:
Quoting Taniya Das (2019-08-19 09:37:48)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e1ff83cc361e..ebd4902afd9f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
ller.
Taniya Das (3):
clk: qcom: rcg: update the DFS macro for RCG
dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
clk: qcom: Add Global Clock controller (GCC) driver for SC7180
.../devicetree/bindings/clock/qcom,gcc.txt| 94 -
.../devicetree/bindings/clock/qcom,gcc.
Update the init data name for each of the dynamic frequency switch
controlled clock associated with the RCG clock name, so that it can be
generated as per the hardware plan. Thus update the macro accordingly.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h| 2 +-
drivers/clk/qcom
The GCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those. Also update
the compatible for SC7180 along with example for clocks & clock-names.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.txt|
Add support for the global clock controller found on SC7180
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc
Hi Stephen,
On 10/1/2019 8:08 PM, Stephen Boyd wrote:
Quoting Taniya Das (2019-09-27 00:37:57)
Hi Stephen,
On 9/25/2019 6:33 PM, Stephen Boyd wrote:
Quoting Taniya Das (2019-09-25 04:20:07)
Hi Stephen,
Please find my comments.
On 9/25/2019 4:42 AM, Stephen Boyd wrote:
Quoting Taniya Das
Hi Stephen,
On 10/5/2019 4:50 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-10-04 10:39:31)
Hi Stephen,
On 10/3/2019 9:31 PM, Stephen Boyd wrote:
Quoting Taniya Das (2019-10-03 03:31:15)
Hi Stephen,
On 10/1/2019 8:08 PM, Stephen Boyd wrote:
Why do you want to keep them critical and
Hi Stephen,
On 10/3/2019 9:31 PM, Stephen Boyd wrote:
Quoting Taniya Das (2019-10-03 03:31:15)
Hi Stephen,
On 10/1/2019 8:08 PM, Stephen Boyd wrote:
Why do you want to keep them critical and registered? I'm suggesting
that any clk that is marked critical and doesn't have a par
Hi Rajendra,
Please pick the patch in the series :
https://patchwork.kernel.org/patch/11150013/
On 9/19/2019 4:38 PM, Rajendra Nayak wrote:
[]..
+static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
+ DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_s
Hi Stephen,
Please find my comments.
On 9/25/2019 4:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-09-23 01:01:11)
Hi Stephen,
Thanks for your comments.
On 9/19/2019 3:09 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-09-18 02:50:18)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b
Hi Stephen,
On 9/25/2019 6:33 PM, Stephen Boyd wrote:
Quoting Taniya Das (2019-09-25 04:20:07)
Hi Stephen,
Please find my comments.
On 9/25/2019 4:42 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-09-23 01:01:11)
Hi Stephen,
Thanks for your comments.
On 9/19/2019 3:09 AM, Stephen Boyd
Hi Matthias,
Thank you for your review.
On 9/18/2019 11:22 PM, Matthias Kaehlcke wrote:
Hi Taniya,
not a full review, just a couple of things I noticed, comments inline.
On Wed, Sep 18, 2019 at 03:20:17PM +0530, Taniya Das wrote:
The GCC clock provider have a bunch of generic properties
Hi Stephen,
Thanks for your comments.
On 9/19/2019 3:09 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-09-18 02:50:18)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
new file mode 100644
index ..d47865d5408f
--- /dev/null
+++ b/drivers/clk/qcom/gcc
On 8/8/2019 3:44 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-08-07 11:13:00)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 8661c3cd3ccf..18d95467cb36 100644
--- a/Documentation/devicetree/bindings/clock
Hello Stephen,
On 8/8/2019 3:54 AM, Stephen Boyd wrote:
Quoting Taniya Das (2019-08-07 11:13:01)
Add support for the global clock controller found on SC7180
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das
controller for SC7180 and also
update device tree bindings for the various clocks supported in the
clock controller.
Taniya Das (3):
clk: qcom: rcg: update the DFS macro for RCG
dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
clk: qcom: Add Global Clock controller (GCC
Update the init data name for each of the dynamic frequency switch
controlled clock associated with the RCG clock name, so that it can be
generated as per the hardware plan. Thus update the macro accordingly.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rcg.h| 2 +-
drivers/clk/qcom
The GCC clock provider have a bunch of generic properties that
are needed in a device tree. Add a YAML schemas for those. Also update
the compatible for SC7180 along with example for clocks & clock-names.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc.yaml |
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