On Fri, 16 Mar 2018, Paolo Bonzini wrote:
> On 06/03/2018 22:03, Radim Krcmar wrote:
> >> /* Fam 15h MSRs */
> >> #define MSR_F15H_PERF_CTL 0xc0010200
> >> +#define MSR_F15H_PERF_CTL0MSR_F15H_PERF_CTL
> >> +#define MSR_F15H_PERF_CTL1(MSR_F15H_PERF_CTL + 2)
On 06/03/2018 22:03, Radim Krcmar wrote:
>> /* Fam 15h MSRs */
>> #define MSR_F15H_PERF_CTL 0xc0010200
>> +#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
>> +#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
>> +#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4
2018-02-05 13:24-0600, Janakarajan Natarajan:
> Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
>
> Signed-off-by: Janakarajan Natarajan
> ---
> arch/x86/include/asm/msr-index.h | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/x86/include/asm/msr-i
Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
Signed-off-by: Janakarajan Natarajan
---
arch/x86/include/asm/msr-index.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index e7b983a..28853
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