> In AST2600 there have a slow peripheral bus between CPU and i2c
> controller.
> Therefore GIC i2c interrupt status clear have delay timing, when CPU
> issue write clear i2c controller interrupt status.
> To avoid this issue, the driver need have read after write clear at
> i2c ISR.
>
>
> > And is there maybe a Fixes: tag for it?
> > [Ryan Chen] Yes it is a fix patch.
>
> I meant this (from submitting-patches.rst):
>It fixes the original implementation of the driver basically. It's just a
>classic posted-write fix. The write to clear the pending interrupt is
>asynchronous, so
On Wed, Apr 29, 2020 at 11:37:37AM +0800, ryan_chen wrote:
> In AST2600 there have a slow peripheral bus between CPU
> and i2c controller.
> Therefore GIC i2c interrupt status clear have delay timing,
> when CPU issue write clear i2c controller interrupt status.
> To avoid this issue, the driver
On Wed, 2020-04-29 at 11:03 +0200, Wolfram Sang wrote:
> > And is there maybe a Fixes: tag for it?
> > [Ryan Chen] Yes it is a fix patch.
>
> I meant this (from submitting-patches.rst):
It fixes the original implementation of the driver basically. It's just
a classic posted-write fix. The write
On Wed, 2020-04-29 at 11:37 +0800, ryan_chen wrote:
> In AST2600 there have a slow peripheral bus between CPU
> and i2c controller.
> Therefore GIC i2c interrupt status clear have delay timing,
> when CPU issue write clear i2c controller interrupt status.
> To avoid this issue, the driver need
> And is there maybe a Fixes: tag for it?
> [Ryan Chen] Yes it is a fix patch.
I meant this (from submitting-patches.rst):
===
If your patch fixes a bug in a specific commit, e.g. you found an issue using
``git bisect``, please use the 'Fixes:' tag with the first 12 characters of
the SHA-1 ID,
...@lists.infradead.org; linux-asp...@lists.ozlabs.org;
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v0 linux master] i2c/busses: Avoid i2c interrupt status
clear race condition.
On Wed, Apr 29, 2020 at 11:37:37AM +0800, ryan_chen wrote:
> In AST2600 there have a slow peripheral bus between CPU and
On Wed, Apr 29, 2020 at 11:37:37AM +0800, ryan_chen wrote:
> In AST2600 there have a slow peripheral bus between CPU
> and i2c controller.
> Therefore GIC i2c interrupt status clear have delay timing,
> when CPU issue write clear i2c controller interrupt status.
> To avoid this issue, the driver
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