0x2d to 0x2 for
supporting the PLL registers read.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 292 ++-
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 9 +
2 files changed, 290 insertions(+), 11 deletions(-)
diff --git a/drivers
nodes
with recalc_rate operation.
2. Added all the supported cpu frequencies in frequency table.
Abhishek Sahu (7):
clk: qcom: ipq4019: Added the clock nodes and operations for pll
clk: qcom: ipq4019: Added the apss cpu pll divider clock node
clk: qcom: ipq4019: Added the nodes for pcnoc
.
This patch registers new clock node and adds its clock
operations for APPS CPU clock divider. Since, this divider
is nonlinear, so frequency table is also added for this,
which contains the frequency and its corresponding hardware
divider values.
Signed-off-by: Abhishek Sahu
---
drivers/clk
The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
This PCNOC clock is critical and should not be turned off so
setting CRITICAL flag also.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 39
The APPS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers
The feedback divider for DDR PLL has been changed in IPQ4019
bootloader from 111 to 112 so changed the frequency values
for the same.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 52 +-
1 file changed, 26 insertions(+), 26 deletions
The current I2C freq table uses MND values which is not
applicable for I2C since its RCG does not have MND
counter. This patch updates the freq table for 19.05
MHz clk frequency with FEPLL_200 parent.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 3 +--
1 file changed, 1
1. The parent for sdcc clock is sdccpll so corrected the same
in its parent map.
2. The frequency value was wrong so changed to correct
frequency.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff
On 2016-06-18 22:02, Wolfram Sang wrote:
We run the command i2cdetect for address 0x3 to 0x77. The QUP
generates
write error for address 0x3 to 0x7 apart from other bus errors since
these are reserved addresses. I was getting the crash in non DMA mode
and BAM hang in DMA mode before putting the
The APPS CPU clock does not contain all the frequencies in its
frequency table so this patch adds the same.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b
with recalc_rate operation.
2. Added all the supported cpu frequencies in frequency table.
Abhishek Sahu (5):
clk: qcom: ipq4019: Added the clock nodes and operations for pll
clk: qcom: ipq4019: Added the apss cpu pll divider clock node
clk: qcom: ipq4019: Added the nodes for pcnoc
clk
the parent of this clock to stable PLL FEPLL500 when it gets
for PRE_RATE_CHANGE event. This event will be generated before actual
clock set operations. The clock set operation will again change its
corresponding parent by getting the same from frequency table.
Signed-off-by: Abhishek Sahu
to 0x2 for
supporting the PLL registers read.
5. Changes the fixed clock name to have consistency in all
clock names
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 316 ---
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 9 +
2
.
This patch registers new clock node and adds its clock
operations for APPS CPU clock divider. Since, this divider
is nonlinear, so frequency table is also added for this,
which contains the frequency and its corresponding hardware
divider values.
Signed-off-by: Abhishek Sahu
---
drivers/clk
The current ipq4019 clock driver does not have the node for
PCNOC so this patch adds and registers the PCNOC clock nodes.
Signed-off-by: Abhishek Sahu
---
drivers/clk/qcom/gcc-ipq4019.c | 37
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 1 +
2 files
On 2017-08-16 09:48, Archit Taneja wrote:
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these functions call with appropriate flags using
following rule
1
On 2017-08-16 10:04, Archit Taneja wrote:
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
In EBI2, all codeword data will be read in FLASH_BUF_ACC buffer
and ADM will copy the data from source (FLASH_BUF_ACC) to
destination (memory for data read).
In QPIC, there is no FLASH_BUF_ACC and all the
On 2017-08-16 10:20, Archit Taneja wrote:
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
1. DM_EN is only required for EBI2 NAND controller which uses ADM
2. BAM mode will be disabled after power on reset which needs to
be enabled before starting any BAM transfers.
Signed-off-by: Abhishek
On 2017-08-16 11:22, Archit Taneja wrote:
On 08/11/2017 05:09 PM, Abhishek Sahu wrote:
The FLASH_DEV_CMD registers starting offset is not same in
different QPIC NAND controller versions. This patch adds
the starting offset in NAND controller properties and uses
the same for calculating the
registers read/write descriptors in
command channel.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
drivers/mtd/nand/qcom_nandc.c | 148 ++
1 file changed, 136 insertions(+), 12 deletions(-)
diff --git a/drivers
patch for driver and documentation changes
5. Changed the compatible string for EBI2
* v1:
http://www.spinics.net/lists/devicetree/msg183706.html
Abhishek Sahu (16):
mtd: nand: qcom: DMA mapping support for register read buffer
mtd: nand: qcom: allocate BAM transaction
mtd: nand: qcom: add
1. DM_EN is only required for EBI2 NAND controller which uses ADM
2. BAM mode will be disabled after power on reset which needs to
be enabled before starting any BAM transfers.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
drivers/mtd/nand
should be reset
before every page read by setting and clearing bit 0 of
NAND_ERASED_CW_DETECT_CFG.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
drivers/mtd/nand/qcom_nandc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers
Qualcom IPQ8074 SoC uses QPIC NAND controller version 1.5.0
which uses BAM DMA Engine.
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd
DMA and its not required for
BAM DMA.
Acked-by: Rob Herring
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
.../devicetree/bindings/mtd/qcom_nandc.txt | 55 +-
1 file changed, 54 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings
1. Add the function for command descriptor preparation which will
be used only by BAM DMA and it will form the DMA descriptors
containing command elements
2. DMA_PREP_CMD flag should be used for forming command DMA
descriptors
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
Add the compatible string for IPQ8074 QPIC NAND controller
version 1.5.0 which uses BAM DMA and its FLASH_DEV_CMD registers
starting offset is 0x7000.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
drivers/mtd/nand/qcom_nandc.c | 10 ++
1 file
1. Correct the compatible string for IPQ806x
2. Change the NAND controller and NAND chip nodes name
for more clarity.
Acked-by: Rob Herring
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 6 +++---
1 file changed, 3
Add the compatible string for IPQ4019 QPIC NAND controller
version 1.4.0 which uses BAM DMA.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
drivers/mtd/nand/qcom_nandc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/nand
All the QPIC register read/write through BAM DMA requires
command descriptor which contains the array of command elements.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
* BUILD DEPENDENCY:
This PATCH has build dependency over following BAM command
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
drivers/mtd/nand/qcom_nandc.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index fd77d59..1ff5daf 100644
--- a/drivers/mtd
The FLASH_DEV_CMD registers starting offset is not same in
different QPIC NAND controller versions. This patch adds
the starting offset in NAND controller properties and uses
the same for calculating the actual offset of these registers.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
.
So for all the write requests in single codeword, the EOT should
be cleared for all tx data descriptors except the last one.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from v4:
1. Added flag argument description in function comment
2. Minor modification in the
flash buffer from which data should be
read
b. Amount of data to be read
c. Flag bit specifying the last read request from the flash
buffer. Following the last read request the NANDc refers to the
buffer as empty.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from
calculated based on the NAND device with the maximum page size,
among all the devices connected to the
controller.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
drivers/mtd/nand/qcom_nandc.c | 94 +++
1 file changed
ll
be synced for device operation and after operation
completion, it will be synced again for CPU.
Reviewed-by: Archit Taneja
Signed-off-by: Abhishek Sahu
---
* Changes from v4: None
drivers/mtd/nand/qcom_nandc.c | 40
1 file changed, 40 insertions(+)
: Abhishek Sahu
On 2018-07-19 03:24, Boris Brezillon wrote:
On Fri, 6 Jul 2018 13:21:59 +0530
Abhishek Sahu wrote:
Driver does not send the commands to NAND device for page
read/write operations in ->cmdfunc(). It just does some
minor variable initialization and rest of the things
are being done in act
On 2018-07-19 03:12, Miquel Raynal wrote:
Abhishek,
Miquel Raynal wrote on Wed, 18 Jul 2018
23:41:44 +0200:
Hi Boris,
Boris Brezillon wrote on Wed, 18 Jul
2018
23:36:37 +0200:
> On Wed, 18 Jul 2018 23:15:26 +0200
> Miquel Raynal wrote:
>
> > Hi Abhishek,
> >
> &
hanks,
Miquèl
Abhishek Sahu wrote on Fri, 6 Jul 2018
13:21:56 +0530:
> The NAND base layer calls write_oob() by setting bytes at
> chip->badblockpos with value non 0xFF for updating bad block status.
> The QCOM NAND controller skips the bad block bytes while doing normal
> wr
On 2018-02-28 04:45, Andy Gross wrote:
On Sat, Feb 03, 2018 at 01:28:14PM +0530, Abhishek Sahu wrote:
The BAM mode requires buffer for start tag data and tx, rx SG
list. Currently, this is being taken for maximum transfer length
(65K). But an I2C transfer can have multiple messages and each
On 2018-02-28 04:28, Andy Gross wrote:
On Sat, Feb 03, 2018 at 01:28:11PM +0530, Abhishek Sahu wrote:
@@ -841,20 +856,12 @@ static int qup_i2c_bam_do_xfer(struct
qup_i2c_dev *qup, struct i2c_msg *msg,
goto desc_err;
}
- if (rx_buf
s are working properly.
The code changes have been tested for QUP v1 (IPQ8064) and QUP
v2 (IPQ8074) with sample application written over i2c-dev.
Abhishek Sahu (13):
i2c: qup: fix copyrights and update to SPDX identifier
i2c: qup: fixed releasing dma without flush operation completion
i2c
The file has been updated from 2016 to 2018 so fixed the
copyright years.
Signed-off-by: Abhishek Sahu
---
drivers/i2c/busses/i2c-qup.c | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c
index 08f8e01
for freeing the DMA resources where the
descriptors are still in process.
Signed-off-by: Abhishek Sahu
Acked-by: Sricharan R
Reviewed-by: Austin Christ
Reviewed-by: Andy Gross
---
* Changes from v1:
1. Removed copyright and added in separate patch with SPDX license
change
drivers/i2c
this patch is scheduling FLUSH and EOT only once after all the
descriptors. So, flush will clear all the scheduled descriptors and
BAM will generate the completion interrupt.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
1. Modified commit message with more details
drivers/i2c/busses/i2c
According to I2c specification, “If a master-receiver sends a
repeated START condition, it sends a not-acknowledge (A) just
before the repeated START condition”. QUP v2 supports sending
of NACK without stop with QUP_TAG_V2_DATARD_NACK so added the
same.
Signed-off-by: Abhishek Sahu
Reviewed-by
Currently the completion timeout is being taken according to
maximum transfer length which is too high if SCL is operating in
high frequency. This patch calculates timeout on the basis of
one-byte transfer time and uses the same for completion timeout.
Signed-off-by: Abhishek Sahu
Reviewed-by
length. Now, this
patch selects DMA mode if the total length is greater than FIFO
length.
Signed-off-by: Abhishek Sahu
Reviewed-by: Austin Christ
Reviewed-by: Andy Gross
---
* Changes from v1:
1. Removed dma_threshold from global structure
2. Modified commit message for the same
drivers/i2c
bytes have been copied in RX FIFO. For
read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts
whenever it has block size of available data.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
1. Fixed auto build test WARNING ‘idx' may be used uninitialized
in this funct
bytes)
and schedule each block separately. QUP v2 supports reconfiguration
during run in which QUP can transfer multiple blocks without issuing a
stop events.
7. Port the SMBus block read support for new code changes.
Signed-off-by: Abhishek Sahu
---
* Changes from v1:
1. Removed event
descriptor scheduling.
The idea is to fit as many messages in one DMA transfers for 65K
threshold value (max_xfer_sg_len). Whenever the sg_cnt is
crossing this, then schedule the BAM transfer and subsequent
transfer will again start from zero.
Signed-off-by: Abhishek Sahu
Reviewed-by
In case of FLUSH operation, BAM copies INPUT EOT FLUSH (0x94)
instead of normal EOT (0x93) tag in input data stream when an
input EOT tag is received during flush operation. So only one tag
will be written instead of 2 separate tags.
Signed-off-by: Abhishek Sahu
Reviewed-by: Andy Gross
. Now,
since the error handling is proper so this release channel can be
completely avoided.
Signed-off-by: Abhishek Sahu
Reviewed-by: Sricharan R
Reviewed-by: Austin Christ
---
* Changes from v1: None
drivers/i2c/busses/i2c-qup.c | 25 -
1 file changed, 16
1. Assigns use_dma in qup_dev structure itself which will
help in subsequent patches to determine the mode in IRQ handler.
2. Does minor code reorganization for loops to reduce the
unnecessary comparison and assignment.
Signed-off-by: Abhishek Sahu
Reviewed-by: Austin Christ
Reviewed-by
The rx_nents and tx_nents are redundant. rx_buf and tx_buf can
be used for total number of SG entries. Since rx_buf and tx_buf
give the impression that it is buffer instead of count so rename
it to tx_cnt and rx_cnt for giving it more meaningful variable
name.
Signed-off-by: Abhishek Sahu
On 2018-02-28 03:36, Christ, Austin wrote:
Hey Abhishek,
On 2/3/2018 12:58 AM, Abhishek Sahu wrote:
The BAM mode requires buffer for start tag data and tx, rx SG
list. Currently, this is being taken for maximum transfer length
(65K). But an I2C transfer can have multiple messages and each
static void qup_i2c_set_blk_event(struct qup_i2c_dev *qup, bool
is_rx)
{
qup->cur_blk_events = 0;
@@ -1442,13 +1155,452 @@ static int qup_i2c_xfer(struct i2c_adapter
*adap,
return ret;
}
+/*
+ * Function to configure registers related with reconfiguration
during run
On 2018-03-24 17:52, Wolfram Sang wrote:
On Mon, Mar 12, 2018 at 06:44:49PM +0530, Abhishek Sahu wrote:
* v2:
1. Address review comments in v1
2. Changed the license to SPDX
3. Changed commit messages for some of the patch having more detail
4. Removed event-based completion and changed
On 2018-04-10 14:29, Miquel Raynal wrote:
Hi Abhishek,
On Wed, 4 Apr 2018 18:12:19 +0530, Abhishek Sahu
wrote:
The NAND flash controller generates ECC uncorrectable error
first in case of completely erased page. Currently driver
applies the erased page detection logic for other operation
On 2018-04-10 14:42, Miquel Raynal wrote:
Hi Abhishek,
On Wed, 4 Apr 2018 18:12:20 +0530, Abhishek Sahu
wrote:
parse_read_errors can be called with only oob buf also in which
case data_buf will be NULL. If data_buf is NULL, then don’t
treat this page as completely erased in case of ECC
On 2018-04-12 12:19, Miquel Raynal wrote:
Hi Abhishek,
On Thu, 12 Apr 2018 12:03:58 +0530, Abhishek Sahu
wrote:
On 2018-04-10 14:29, Miquel Raynal wrote:
> Hi Abhishek,
> > On Wed, 4 Apr 2018 18:12:19 +0530, Abhishek Sahu
> wrote:
> >> The NAND flash controller genera
On 2018-04-10 15:14, Miquel Raynal wrote:
Hi Abhishek,
On Wed, 4 Apr 2018 18:12:24 +0530, Abhishek Sahu
wrote:
This patch does minor code reorganization for raw reads.
Currently the raw read is required for complete page but for
subsequent patches related with erased codeword bit flips
On 2018-04-10 15:33, Miquel Raynal wrote:
Hi Abhishek,
On Wed, 4 Apr 2018 18:12:21 +0530, Abhishek Sahu
wrote:
read_page and read_oob both calls the read_page_ecc function.
The QCOM NAND controller protect the OOB available bytes with
ECC so read errors should be checked for read_oob also
On 2018-04-10 15:42, Miquel Raynal wrote:
Hi Abhishek,
On Wed, 4 Apr 2018 18:12:23 +0530, Abhishek Sahu
wrote:
Currently there is no error checking for raw read. For raw
reads, there won’t be any ECC failure but the operational
failures are possible so schedule the NAND_FLASH_STATUS read
On 2018-04-10 16:00, Miquel Raynal wrote:
Hi Abhishek,
On Wed, 4 Apr 2018 18:12:25 +0530, Abhishek Sahu
wrote:
Some of the newer nand parts can have bit flips in an erased
page due to the process technology used. In this case, qpic
AFAIK, this has always been possible, it was just rare
On 2018-04-10 13:37, Boris Brezillon wrote:
On Tue, 10 Apr 2018 09:55:58 +0200
Miquel Raynal wrote:
> Hi Abhishek,
>
> On Tue, 10 Apr 2018 11:39:35 +0530, Abhishek Sahu
> wrote:
>
> > On 2018-04-06 18:01, Miquel Raynal wrote:
> > > Hi Abhishek,
> > >
&
On 2018-04-06 18:01, Miquel Raynal wrote:
Hi Abhishek,
On Wed, 4 Apr 2018 18:12:17 +0530, Abhishek Sahu
wrote:
Currently the driver uses the ECC strength specified in
device tree. The ONFI or JEDEC device parameter page
contains the ‘ECC correctability’ field which indicates the
number of
On 2018-02-28 04:06, Andy Gross wrote:
On Sat, Feb 03, 2018 at 01:28:09PM +0530, Abhishek Sahu wrote:
A single BAM transfer can have multiple read and write messages.
The EOT and FLUSH tags should be scheduled at the end of BAM HW
descriptors. Since the READ and WRITE can be present in any
On 2018-11-04 21:26, Boris Brezillon wrote:
Hi Abhishek,
On Fri, 20 Jul 2018 15:03:48 +0200
Boris Brezillon wrote:
On Fri, 20 Jul 2018 17:46:38 +0530
Abhishek Sahu wrote:
> Hi Boris,
>
> On 2018-07-19 03:13, Boris Brezillon wrote:
> > On Wed, 18 Jul 2018 23:23:50 +0200
&g
On 2018-07-01 23:39, Miquel Raynal wrote:
Hi Abhishek,
Abhishek Sahu wrote on Wed, 20 Jun 2018
12:57:27 +0530:
* v4:
1. Added patch to make other ECC configurations function static.
2. Clubbed the DT update patches.
3. Removed the bad block related patch. Discussion is going on
related
h CW, check the number of 0 in cw_data and usable
oob bytes, The bbm and spare (unused) bytes bit flip won’t
affect the ECC so don’t check the number of bitflips in this area.
Signed-off-by: Abhishek Sahu
---
* Changes from v4:
1. Used for_each_set_bit for determining CW’s whic
function which calls the
required helper functions for the above logic. The drivers can use
this single function instead of calling the 3 helper functions
individually.
CC: Masahiro Yamada
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Renamed function to nand_ecc_choose_conf.
2. Minor
Use the NAND core helper function nand_ecc_choose_conf to tune
the ECC parameters instead of the function locally defined.
CC: Masahiro Yamada
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Changed commit message
* Changes from v1:
NEW PATCH
drivers/mtd
it detects the same.
[1]: https://patchwork.ozlabs.org/patch/328994/
[2]: https://patchwork.ozlabs.org/patch/509970/
Abhishek Sahu (16):
mtd: rawnand: helper function for setting up ECC configuration
mtd: rawnand: denali: use helper function for ecc setup
dt-bindings: qcom_nandc: make nand
also (like TIMEOUT, MPU
errors, etc.), the erased CW detect logic is being applied so fix this
and return EIO for other operational errors.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Changed commit message slightly
* Changes from v1:
1. Added more detail in
QCOM NAND controller supports only one step size (512) so
nand-ecc-step-size DT property is redundant. This property
can be removed and ecc step size can be assigned with 512 value.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NEW CHANGE
1. Removed the custom logic and used the
If nand-ecc-strength specified in DT, then controller will use
this ECC strength otherwise ECC strength will be calculated
according to chip requirement and available OOB size.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
NEW PATCH
Documentation/devicetree
Currently the driver uses the ECC strength specified in DT.
The QPIC/EBI2 NAND supports 4 or 8-bit ECC correction. The same
kind of board can have different NAND parts so use the ECC
strength from device parameters if it is not specified in DT.
Signed-off-by: Abhishek Sahu
---
* Changes from v2
: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Added more detail in commit message
2. Added comment before each if/else
drivers/mtd/nand/raw/qcom_nandc.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a
number of 0 in cw_data and usable
oob bytes, The bbm and spare (unused) bytes bit flip won’t
affect the ECC so don’t check the number of bitflips in this area.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Minor change in commit message
2. invalidate p
Currently there is no error checking for raw read. For raw
reads, there won’t be any ECC failure but the operational
failures are possible, so schedule the NAND_FLASH_STATUS read
after each codeword.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Removed the
n writes the codeword back.
The reading codeword is unnecessary since user is responsible to
have these bytes cleared to 0xFF.
This patch removes the read part and updates the OOB bytes with
data area padded with OxFF.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from
specifies which CW reads are required in complete page.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Included more detail in function comment
drivers/mtd/nand/raw/qcom_nandc.c | 197 --
1 file changed, 123 insertions(+), 74
this, copy_last_cw function won’t be required.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Changed commit message and comments slightly
* Changes from v1:
NEW CHANGE
drivers/mtd/nand/raw/qcom_nandc.c | 66 +++
1 file changed, 25 insertions
Fix value returned by ->read_page_raw() to be the
actual operation status, instead of always 0.
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
1. Changed commit message
* Changes from v1:
NEW CHANGE
drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
errors.
Reviewed-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v2:
NONE
* Changes from v1:
1. Minor code change for return early in case of error
drivers/mtd/nand/raw/qcom_nandc.c | 26 +-
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git
completed all its DMA
descriptors. It assigns completion callback in last
DMA descriptors of that channel and wait for completion.
Fixes: 8d6b6d7e135e ("mtd: nand: qcom: support for command descriptor
formation")
Cc: sta...@vger.kernel.org
Signed-off-by: Abhishek Sahu
---
* Changes fr
QCOM NAND controller supports only one step size (512) but
nand-ecc-step-size is required property in DT. This DT property
can be removed and ecc step size can be assigned in driver with
512 value.
Signed-off-by: Abhishek Sahu
---
Currently there is no user in mainline linux kernel for
QPIC
On 2018-05-26 14:12, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:29 +0530, Abhishek Sahu
wrote:
commit 2c8f8afa7f92 ("mtd: nand: add generic helpers to check,
match, maximize ECC settings") provides generic helpers which
drivers can use for setting up ECC paramete
On 2018-05-26 14:12, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:31 +0530, Abhishek Sahu
wrote:
If nand-ecc-strength specified in DT, then controller will use
this ECC strength otherwise ECC strength will be calculated
according to chip requirement and available OOB size
On 2018-05-26 14:12, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:33 +0530, Abhishek Sahu
wrote:
QCOM NAND controller supports only one step size (512) so
nand-ecc-step-size DT property is redundant. This property
can be removed and ecc step size can be assigned with 512 value
On 2018-05-26 14:13, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:34 +0530, Abhishek Sahu
wrote:
Currently the driver uses the ECC strength specified in DT.
The QPIC/EBI2 NAND supports 4 or 8-bit ECC correction. The same
kind of board can have different NAND parts so use the
On 2018-05-26 14:16, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:41 +0530, Abhishek Sahu
wrote:
The QCOM NAND controller layout is such that, the bad block byte
offset for last codeword will come to first byte in spare area.
"is the first spare byte"?
Currentl
On 2018-05-26 14:28, Miquel Raynal wrote:
Hi Abhishek,
@@ -2141,12 +2127,10 @@ static int qcom_nandc_block_bad(struct
mtd_info *mtd, loff_t ofs)
goto err;
}
- bbpos = mtd->writesize - host->cw_size * (ecc->steps - 1);
-
- bad = nandc->data_buffer[bbpos] !=
On 2018-05-27 19:23, Miquel Raynal wrote:
Hi Abhishek,
On Fri, 25 May 2018 17:51:43 +0530, Abhishek Sahu
wrote:
This patch does minor code reorganization for raw reads.
Currently the raw read is required for complete page but for
subsequent patches related with erased codeword bit flips
h CW, check the number of 0 in cw_data and usable
oob bytes, The bbm and spare (unused) bytes bit flip won’t
affect the ECC so don’t check the number of bitflips in this area.
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. Major changes in erased codeword detection for
raw re
QCOM NAND controller supports only one step size (512) so
nand-ecc-step-size DT property is redundant. This property
can be removed and ecc step size can be assigned with 512 value.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. Minor change in comment
(s
Fix value returned by ->read_page_raw() to be the
actual operation status, instead of always 0.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
NONE
* Changes from v2:
1. Changed commit message
* Changes from v1:
NEW CHANGE
drivers/mtd/nand/raw/qcom_nand
Currently there is no error checking for raw read. For raw
reads, there won’t be any ECC failure but the operational
failures are possible, so schedule the NAND_FLASH_STATUS read
after each codeword.
Acked-by: Miquel Raynal
Signed-off-by: Abhishek Sahu
---
* Changes from v3:
1. Since bad block
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