...
+int sr_configure_errgen(struct smartreflex *sr)
+{
+ struct smartreflex_platform_data *pdata = sr-pdev-dev.platform_data;
+ u32 sr_config, sr_errconfig;
+
+ if (IS_ERR_OR_NULL(sr))
+ return -EINVAL;
+
+ if (!sr_calculate_clk_length(sr))
+
On Mon, Sep 26, 2011 at 03:01:54PM +0530, Santosh Shilimkar wrote:
Samual,
On Monday 26 September 2011 02:20 PM, Samuel Ortiz wrote:
Hi Todd,
On Thu, Sep 15, 2011 at 01:37:38PM -0700, Todd Poynor wrote:
On Tue, Sep 06, 2011 at 09:29:30PM +0530, Santosh Shilimkar wrote:
TWL6030
these as
equivalent, presumably due to problems that can be incurred
when locking more than one irq_desc, so best to avoid this.
Suspend/resume actions implemented as PM notifiers to avoid
touch the TWL core for this.
Signed-off-by: Todd Poynor toddpoy...@google.com
---
This patch applies on top
it at DPM resume
time, at which time the child module IRQs will be re-enabled.
Signed-off-by: Todd Poynor toddpoy...@google.com
---
drivers/mfd/twl6030-irq.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mfd/twl6030-irq.c b/drivers/mfd/twl6030-irq.c
index
On Tue, Sep 06, 2011 at 09:29:30PM +0530, Santosh Shilimkar wrote:
TWL6030 devices have an interrupt line which is connected to
application processor like OMAP. These devices support multiple features
such as MMC card detect, USB cable detect, RTC interrupt, etc. that must
wake up the
On Wed, Aug 24, 2011 at 08:07:12PM +0530, Keerthy wrote:
...
+ temp_sensor-phy_base = ioremap(mem-start, resource_size(mem));
Check NULL return.
temp_sensor-phy_base is never iounmapped in error paths or _remove
function.
...
+static int __devexit omap_temp_sensor_remove(struct
On Thu, Aug 18, 2011 at 04:22:15PM +0530, Keerthy wrote:
...
+static int omap_temp_sensor_clk_enable(struct omap_temp_sensor *temp_sensor)
+{
+ u32 ret = 0;
+
+ if (temp_sensor-clk_on) {
+ dev_err(temp_sensor-hwmon_dev, clock already on\n);
+ goto out;
+
On Thu, Aug 18, 2011 at 04:22:14PM +0530, Keerthy wrote:
...
+int omap_temp_sensor_device_idle(struct omap_device *od)
+{
+ struct omap_temp_sensor_registers *registers;
+ struct resource*mem;
+ void__iomem *phy_base;
+
On Fri, Aug 12, 2011 at 12:20:21PM +0530, Munegowda, Keshava wrote:
On Wed, Aug 10, 2011 at 10:01 PM, Todd Poynor toddpoy...@google.com wrote:
@@ -913,12 +598,15 @@ static int usbhs_enable(struct device *dev)
(pdata-ehci_data-reset_gpio_port[1], 1
On Tue, Aug 09, 2011 at 07:45:09PM +0530, Keshava Munegowda wrote:
From: Keshava Munegowda keshava_mgo...@ti.com
The usbhs core driver does not enable/disable the intefrace and
typo: interface
fucntional clocks; These clocks are handled by hwmod and runtime pm,
typo: functional
hence
the RTC is stopped, prior to clearing
pending alarms, etc.
The new ordering also avoids leaving the platform
device drvdata set to an unregistered struct rtc_device *
on probe errors.
Signed-off-by: Todd Poynor toddpoy...@google.com
---
This version generated after applying:
[PATCH] rtc-twl: Switch
On Thu, Jul 28, 2011 at 10:30:15AM +0200, jean.pi...@newoldbits.com wrote:
...
+int pwrdm_set_wkup_lat_constraint(struct powerdomain *pwrdm, void *cookie,
+ long min_latency)
+{
+ struct pwrdm_wkup_constraints_entry *user = NULL;
+ struct
On Thu, Jul 28, 2011 at 10:30:14AM +0200, jean.pi...@newoldbits.com wrote:
From: Jean Pihet j-pi...@ti.com
The powerdomains next states are initialized in pwrdms_setup as a
late_initcall. Because the PM QoS devices constraint can be requested
early in the boot sequence, the power domains
On Fri, Jul 29, 2011 at 10:47:43AM +0200, Jean Pihet wrote:
On Fri, Jul 29, 2011 at 9:59 AM, Todd Poynor toddpoy...@google.com wrote:
...
All min_latency != PM_QOS_DEV_LAT_DEFAULT_VALUE paths need
free_new_user = 1.
free_new_user = 1 is only needed if no existing constraint has been
found
On Wed, Jul 27, 2011 at 05:14:58PM +0530, DebBarma, Tarun Kanti wrote:
...
omap_gpio_mod_init calls mpuio_init calls platform_driver_register
which can't be called in an IRQs off and spinlocked atomic context,
...
I have isolated mpuio_init() from omap_gpio_mod_init().
mpuio_init() is now
On Thu, Jul 28, 2011 at 03:05:29PM +0530, DebBarma, Tarun Kanti wrote:
...
Looking at omap_gpio_mod_init() it seems like much of its processing
could probably be done once at probe time (or at pm_runtime_get_sync
time) as well, namely setting the IRQ enable masks.
This must be called at
:130 handle_irq_event_percpu+nnn
irq nnn handler twl_rtc_interrupt+nnn enabled interrupts
Signed-off-by: Todd Poynor toddpoy...@google.com
---
drivers/rtc/rtc-twl.c | 14 +++---
1 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
the RTC is stopped, prior to clearing
pending alarms, etc.
The new ordering also avoids leaving the platform
device drvdata set to an unregistered struct rtc_device *
on probe errors.
Signed-off-by: Todd Poynor toddpoy...@google.com
---
drivers/rtc/rtc-twl.c | 52
On Sat, Jul 16, 2011 at 01:45:45PM +0530, Tarun Kanti DebBarma wrote:
With register offsets now defined for respective OMAP versions we can get rid
of cpu_class_* checks. This function now has common initialization code for
all OMAP versions. Initialization specific to OMAP16xx has been moved
On Sat, Jul 16, 2011 at 01:45:50PM +0530, Tarun Kanti DebBarma wrote:
Call runtime pm APIs pm_runtime_get_sync() and pm_runtime_put_sync()
for enabling/disabling clocks appropriately. Remove syscore_ops and
instead use dev_pm_ops now.
...
@@ -481,6 +483,22 @@ static int
On Tue, Jul 05, 2011 at 01:27:47PM +0300, Tero Kristo wrote:
Introduce a chained interrupt handler mechanism for the PRCM
interrupt, so that individual PRCM event can cleanly be handled by
handlers in separate drivers. We do this by introducing PRCM event
names, which are then matched to the
On Wed, Jul 13, 2011 at 07:24:17PM +0530, Tarun Kanti DebBarma wrote:
From: Charulatha V ch...@ti.com
Call runtime pm APIs pm_runtime_get_sync() and pm_runtime_put_sync()
for enabling/disabling clocks appropriately. Remove syscore_ops and
instead use dev_pm_ops now.
...
+ /*
+ *
On Wed, Jul 13, 2011 at 05:00:35PM +0300, Tero Kristo wrote:
OMAP SMPS regulator driver provides access to OMAP voltage processor
controlled regulators. These include VDD1 and VDD2 for OMAP3 and additionally
VDD3 for OMAP4. SMPS regulators use the OMAP voltage layer for the actual
voltage
On Wed, Jul 13, 2011 at 07:24:12PM +0530, Tarun Kanti DebBarma wrote:
With register offsets now defined for respective OMAP versions we can get rid
of cpu_class_* checks. This function now has common initialization code for
all OMAP versions. Initialization specific to OMAP16xx has been moved
Signed-off-by: Todd Poynor toddpoy...@google.com
---
arch/arm/mach-omap2/irq.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3af2b7a..acbb05c 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach
On Mon, Jul 11, 2011 at 04:59:12PM +0530, Tarun Kanti DebBarma wrote:
Add dmtimer platform driver functions which include:
(1) platform driver initialization
(2) driver probe function
(3) driver remove function
...
+ timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
+ if
On Mon, Jul 11, 2011 at 04:59:11PM +0530, Tarun Kanti DebBarma wrote:
Add routines to converts dmtimers to platform devices. The device data
is obtained from hwmod database of respective platform and is registered
to device model after successful binding to driver.
In addition, capability
On Thu, Jul 07, 2011 at 02:25:23AM -0600, Paul Walmsley wrote:
On Fri, 1 Jul 2011, Benoit Cousson wrote:
The CLKCTRL register was accessed using an absolute address.
The usage of hardcoded macros to calculate virtual address from physical
one should be avoided as much as possible.
The
On Fri, Jul 01, 2011 at 11:09:09PM +0200, Benoit Cousson wrote:
It is mandatory to wait for a module to be in disabled state before
potentially disabling source clock or re-asserting a reset.
omap_hwmod_idle and omap_hwmod_shutdown does not wait for
the module to be fully idle.
Add a
On Fri, Jul 01, 2011 at 07:37:56AM +0530, Rajendra Nayak wrote:
From: Aneesh V ane...@ti.com
Macros for identifying the max frequency supported by various
OMAP4 variants - Expanding along the lines of OMAP3's feature
handling.
[n...@ti.com: minor fixes for checks that should only for
On Tue, Jun 28, 2011 at 04:10:55PM +0200, Cousson, Benoit wrote:
On 6/27/2011 8:56 PM, Todd Poynor wrote:
On Mon, Jun 27, 2011 at 06:33:06PM +0200, Benoit Cousson wrote:
...
+ r = clk_get_sys(dev_name(od-pdev.dev), clk_alias);
+ if (!IS_ERR(r)) {
+ pr_warning(omap_device: %s
On Fri, Jun 24, 2011 at 04:38:05PM +0200, jean.pi...@newoldbits.com wrote:
...
+ /* Find the associated omap_device for dev */
+ od = container_of(pdev, struct omap_device, pdev);
+ if (!od || (od-hwmods_cnt != 1)) {
+ pr_err(%s: Error: No unique hwmod for device %s\n,
On Mon, Jun 27, 2011 at 06:33:06PM +0200, Benoit Cousson wrote:
...
+ r = clk_get_sys(dev_name(od-pdev.dev), clk_alias);
+ if (!IS_ERR(r)) {
+ pr_warning(omap_device: %s: %s already exist\n,
+dev_name(od-pdev.dev), clk_alias);
I believe a clk_put(r)
On Mon, Jun 27, 2011 at 06:11:37PM +0200, Benoit Cousson wrote:
From: Rajendra Nayak rna...@ti.com
Add the SoC specific implemenation for clkdm_is_idle
for OMAP2/3 and OMAP4.
This is now called clkdm_allows_idle.
Todd
--
To unsubscribe from this list: send the line unsubscribe linux-omap
On Mon, Jun 27, 2011 at 06:11:39PM +0200, Benoit Cousson wrote:
From: Rajendra Nayak rna...@ti.com
The omap_set_pwrdm_state function forces clockdomains
to idle, without checking the existing idle state
programmed, instead based solely on the HW capability
of the clockdomain to support
On Mon, Jun 27, 2011 at 06:11:41PM +0200, Benoit Cousson wrote:
...
+ * clkdm_hwmod_disable - remove an enabled downstream hwmod from this clkdm
+ * @clkdm: struct clockdomain *
+ * @oh: struct omap_hwmod * of the disabled downstream hwmod
+ *
+ * Decrement the usecount of this clockdomain
On Fri, Jun 24, 2011 at 01:06:00PM +0200, Benoit Cousson wrote:
From: Nayak, Rajendra rna...@ti.com
Add a clockdomain api to check if hardware supervised
idle transitions are enabled on a clockdomain.
...
+ * clkdm_is_idle - Check if the clkdm hwsup/autoidle is enabled
+ * @clkdm: struct
On Fri, Jun 24, 2011 at 02:06:32PM +0200, Benoit Cousson wrote:
Duplicate the existing API for clockdomain enable from clock to enable
a clock domain from hwmod framework.
This will be needed when the hwmod framework will move from the current
clock centric approach to the module based
On Fri, Jun 24, 2011 at 10:14:03AM -0500, Moiz Sonasath wrote:
...
+ if (enabled)
+ twl-vbus_enable = 1;
+ else
+ twl-vbus_enable = 0;
+
Suggest twl-vbus_enable = enabled;
/*
* Start driving VBUS. Set OPA_MODE bit in CHARGERUSB_CTRL1
On Thu, Jun 09, 2011 at 04:24:06PM +0530, Rajendra Nayak wrote:
Add a clockdomain api to check if hardware supervised
idle transitions are enabled on a clockdomain.
...
+ * clkdm_is_idle - Check if the clkdm hwsup/autoidle is enabled
A minor suggestion on naming: clkdm_allows_idle seems more
On Thu, Jun 09, 2011 at 04:24:09PM +0530, Rajendra Nayak wrote:
The omap_set_pwrdm_state function forces clockdomains
to idle, without checking the existing idle state
programmed, instead based solely on the HW capability
of the clockdomain to support idle.
This is wrong and the clockdomains
Enable all CPUs in the shared policy in the CPU init callback.
Otherwise, the governor CPUFREQ_GOV_START event is invoked with
a policy that only includes the first CPU, leaving other CPUs
uninitialized by the governor.
Signed-off-by: Todd Poynor toddpoy...@google.com
---
arch/arm/mach-omap2
On Mon, Jun 06, 2011 at 03:32:29PM -0700, Kevin Hilman wrote:
Colin Cross ccr...@android.com writes:
On Sat, Jun 4, 2011 at 12:03 PM, Colin Cross ccr...@android.com wrote:
Setting the IRQWAKEN bit was overwriting previous IRQWAKEN bits,
causing only the last bit set to take effect,
Reading the VPVOLTAGE field of PRM_VP_*_VOLTAGE registers currently
relies on a u32 - u8 conversion to mask off the FORCEUPDATEWAIT field
in the upper bits. Make this explicit using the mask symbol
already defined, added as a new field in struct omap_vp_common.
Signed-off-by: Todd Poynor toddpoy
the L3_FLAGMUX_REGERRn
register.
* Remove extra l3_base[] entry.
* Modify L3 custom error message for consistency with standard
error message.
Signed-off-by: Todd Poynor toddpoy...@google.com
---
V2 updated for feedback from Santosh (thanks!).
arch/arm/mach-omap2/omap_l3_noc.c | 38
!dev case needs iounmap before return.
Signed-off-by: Todd Poynor toddpoy...@google.com
---
arch/arm/mach-omap2/omap_phy_internal.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c
b/arch/arm/mach-omap2/omap_phy_internal.c
index
Reading the VPVOLTAGE field of PRM_VP_*_VOLTAGE registers currently
relies on a u32 - u8 conversion to mask off the FORCEUPDATEWAIT field
in the upper bits. Make this explicit using the mask and shift symbols
already defined, added as new fields in struct omap_vp_common.
Signed-off-by: Todd
On Wed, May 25, 2011 at 12:39:56PM +0530, Santosh Shilimkar wrote:
Tod,
On 5/25/2011 8:20 AM, Todd Poynor wrote:
* Move variable declarations from header file and make these static
(the entire header file should probably go away).
Infact the intial version posted on the list had all
On Wed, May 25, 2011 at 04:38:49PM -0700, Nishanth Menon wrote:
OMAP2+ all have frequency tables, hence the hacks we had for older
silicon do not need to be carried forward. As part of this change,
use cpufreq_frequency_table_target to find the best match for
frequency requested.
On Wed, May 25, 2011 at 04:38:50PM -0700, Nishanth Menon wrote:
By creating freq_table_[alloc|free] we can handle the differences
between OMAP2 and OMAP3+ systems and we have a centralized allocation
and cleanup strategy. We use this to cleanup the freq_table when
On Wed, May 25, 2011 at 04:38:51PM -0700, Nishanth Menon wrote:
Since we have multiple CPUs, the cpuinit call for CPU1 causes
freq_table of CPU0 to be overwritten. Instead, we maintain
a counter to keep track of cpus who use the cpufreq table
allocate it once(one freq table for all CPUs) and
On Wed, May 25, 2011 at 06:56:56PM -0700, Nishanth Menon wrote:
...
@@ -427,6 +465,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned
long rate)
u16 freqsel = 0;
struct dpll_data *dd;
int ret;
+ unsigned long orig_rate = 0;
if (!clk || !rate)
* Move variable declarations from header file and make these static
(the entire header file should probably go away).
* Define L3 TARG instance offsets, and read/write STDERRLOG registers
relative to those offsets, rather than defining STDERRLOG_MAIN
instance offsets and accessing other
On Mon, May 23, 2011 at 06:12:15PM -0500, Nishanth Menon wrote:
cpufreq table allocated by opp_init_cpufreq_table is better
freed by OPP layer itself. This allows future modifications to
the table handling to be transparent to the users.
...
+void opp_free_cpufreq_table(struct device *dev,
+
On Wed, May 18, 2011 at 02:37:43AM -0500, Nishanth Menon wrote:
this should probably get squashed in..
Signed-off-by: Nishanth Menon n...@ti.com
---
arch/arm/mach-omap2/omap2plus-cpufreq.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git
on boards not yet modified to
register voltage params.
Signed-off-by: Todd Poynor toddpoy...@google.com
---
arch/arm/mach-omap2/voltage.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index dbc1cfe..8f23d95
[Another try with a different email client, sorry for any dups.]
...
diff --git a/arch/arm/mach-omap2/sr_device.c
b/arch/arm/mach-omap2/sr_device.c
index 2782d3f..65b2aae 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -82,6 +82,7 @@ static int
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