[PATCH 27/58] arm64: dts: renesas: r8a774a1: Add GPIO device nodes

[Simon Horman]

From: Fabrizio Castro 

Add GPIO device nodes to the DT of the r8a774a1 SoC.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Biju Das 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 120 ++
 1 file changed, 120 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index c956bf7ecde9..4c251c48619b 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -133,6 +133,126 @@
status = "disabled";
};
 
+   gpio0: gpio@e605 {
+   compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+   reg = <0 0xe605 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 0 16>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 912>;
+   power-domains = < 32>;
+   resets = < 912>;
+   };
+
+   gpio1: gpio@e6051000 {
+   compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+   reg = <0 0xe6051000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 32 29>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 911>;
+   power-domains = < 32>;
+   resets = < 911>;
+   };
+
+   gpio2: gpio@e6052000 {
+   compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+   reg = <0 0xe6052000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 64 15>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 910>;
+   power-domains = < 32>;
+   resets = < 910>;
+   };
+
+   gpio3: gpio@e6053000 {
+   compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+   reg = <0 0xe6053000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 96 16>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 909>;
+   power-domains = < 32>;
+   resets = < 909>;
+   };
+
+   gpio4: gpio@e6054000 {
+   compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+   reg = <0 0xe6054000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 128 18>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 908>;
+   power-domains = < 32>;
+   resets = < 908>;
+   };
+
+   gpio5: gpio@e6055000 {
+   compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+   reg = <0 0xe6055000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 160 26>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 907>;
+   power-domains = < 32>;
+   resets = < 907>;
+   };
+
+   gpio6: gpio@e6055400 {
+   compatible = "renesas,gpio-r8a774a1",
+"renesas,rcar-gen3-gpio";
+   reg = <0 0xe6055400 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 192 32>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 906>;
+ 

[PATCH 31/58] arm64: dts: renesas: r8a774a1: Add IPMMU device nodes

[Simon Horman]

From: Fabrizio Castro 

Add r8a774a1 IPMMU nodes.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Biju Das 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 73 +++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 02620c89e004..8589122e3c94 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -642,6 +642,79 @@
dma-channels = <16>;
};
 
+   ipmmu_ds0: mmu@e674 {
+   compatible = "renesas,ipmmu-r8a774a1";
+   reg = <0 0xe674 0 0x1000>;
+   renesas,ipmmu-main = <_mm 0>;
+   power-domains = < 32>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_ds1: mmu@e774 {
+   compatible = "renesas,ipmmu-r8a774a1";
+   reg = <0 0xe774 0 0x1000>;
+   renesas,ipmmu-main = <_mm 1>;
+   power-domains = < 32>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_hc: mmu@e657 {
+   compatible = "renesas,ipmmu-r8a774a1";
+   reg = <0 0xe657 0 0x1000>;
+   renesas,ipmmu-main = <_mm 2>;
+   power-domains = < 32>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_mm: mmu@e67b {
+   compatible = "renesas,ipmmu-r8a774a1";
+   reg = <0 0xe67b 0 0x1000>;
+   interrupts = ,
+;
+   power-domains = < 32>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_mp: mmu@ec67 {
+   compatible = "renesas,ipmmu-r8a774a1";
+   reg = <0 0xec67 0 0x1000>;
+   renesas,ipmmu-main = <_mm 4>;
+   power-domains = < 32>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_pv0: mmu@fd80 {
+   compatible = "renesas,ipmmu-r8a774a1";
+   reg = <0 0xfd80 0 0x1000>;
+   renesas,ipmmu-main = <_mm 5>;
+   power-domains = < 32>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_pv1: mmu@fd95 {
+   compatible = "renesas,ipmmu-r8a774a1";
+   reg = <0 0xfd95 0 0x1000>;
+   renesas,ipmmu-main = <_mm 6>;
+   power-domains = < 32>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_vc0: mmu@fe6b {
+   compatible = "renesas,ipmmu-r8a774a1";
+   reg = <0 0xfe6b 0 0x1000>;
+   renesas,ipmmu-main = <_mm 8>;
+   power-domains = < 14>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_vi0: mmu@febd {
+   compatible = "renesas,ipmmu-r8a774a1";
+   reg = <0 0xfebd 0 0x1000>;
+   renesas,ipmmu-main = <_mm 9>;
+   power-domains = < 32>;
+   #iommu-cells = <1>;
+   };
+
avb: ethernet@e680 {
compatible = "renesas,etheravb-r8a774a1",
 "renesas,etheravb-rcar-gen3";
-- 
2.11.0

[PATCH 50/58] arm64: dts: renesas: r8a77990: Add BRG support to SCIF2

[Simon Horman]

From: Takeshi Kihara 

Add the device node for the external SCIF_CLK, and describe the clock
inputs for the Baud Rate Generator for External Clock (BRG) for SCIF2,
which can increase serial clock accuracy.

The presence of the SCIF_CLK crystal and its clock frequency depend on
the actual board.

Signed-off-by: Takeshi Kihara 
[geert: Enhance patch description]
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index e2c2d1480a68..6198768264be 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -63,6 +63,13 @@
method = "smc";
};
 
+   /* External SCIF clock - to be overridden by boards that provide it */
+   scif_clk: scif {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
soc: soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -412,8 +419,11 @@
 "renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = ;
-   clocks = < CPG_MOD 310>;
-   clock-names = "fck";
+   clocks = < CPG_MOD 310>,
+< CPG_CORE R8A77990_CLK_S3D1C>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 310>;
status = "disabled";
-- 
2.11.0

[PATCH 10/58] arm64: dts: renesas: salvator-xs: enable SATA

[Simon Horman]

From: Wolfram Sang 

Add the nodes to enable SATA. Note that MD12 (SW12-7) must be switched
off for that to work.

Signed-off-by: Wolfram Sang 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts  | 14 ++
 arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 14 ++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index 8c142affee49..ba3357636fdb 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -151,6 +151,15 @@
};
 };
 
+ {
+   pcie_sata_switch {
+   gpio-hog;
+   gpios = <7 GPIO_ACTIVE_HIGH>;
+   output-low; /* enable SATA by default */
+   line-name = "PCIE/SATA switch";
+   };
+};
+
  {
usb2_pins: usb2 {
groups = "usb2";
@@ -175,6 +184,11 @@
};
 };
 
+/* MD12 (SW12-7) must be set 'Off' which is not the default! */
+ {
+   status = "okay";
+};
+
 _phy2 {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts 
b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
index 9de4e3db1621..45016a06fab1 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -47,3 +47,17 @@
 _con {
remote-endpoint = <_dw_hdmi0_out>;
 };
+
+ {
+   pcie_sata_switch {
+   gpio-hog;
+   gpios = <7 GPIO_ACTIVE_HIGH>;
+   output-low; /* enable SATA by default */
+   line-name = "PCIE/SATA switch";
+   };
+};
+
+/* MD12 (SW12-7) must be set 'Off' which is not the default! */
+ {
+   status = "okay";
+};
-- 
2.11.0

[PATCH 13/58] arm64: dts: renesas: Initial r8a774a1 SoC device tree

[Simon Horman]

From: Biju Das 

Basic support for the RZ/G2M SoC.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 190 ++
 1 file changed, 190 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a774a1.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
new file mode 100644
index ..8e63e9aee456
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the r8a774a1 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a774a1";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   /*
+* The external audio clocks are configured as 0 Hz fixed frequency
+* clocks by default.
+* Boards that provide audio clocks should override them.
+*/
+   audio_clk_a: audio_clk_a {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   audio_clk_b: audio_clk_b {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   audio_clk_c: audio_clk_c {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   /* External CAN clock - to be overridden by boards that provide it */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   a57_0: cpu@0 {
+   compatible = "arm,cortex-a57", "arm,armv8";
+   reg = <0x0>;
+   device_type = "cpu";
+   power-domains = < 0>;
+   next-level-cache = <_CA57>;
+   enable-method = "psci";
+   clocks =< CPG_CORE 0>;
+   };
+
+   a57_1: cpu@1 {
+   compatible = "arm,cortex-a57", "arm,armv8";
+   reg = <0x1>;
+   device_type = "cpu";
+   power-domains = < 1>;
+   next-level-cache = <_CA57>;
+   enable-method = "psci";
+   clocks =< CPG_CORE 0>;
+   };
+
+   L2_CA57: cache-controller-0 {
+   compatible = "cache";
+   power-domains = < 12>;
+   cache-unified;
+   cache-level = <2>;
+   };
+   };
+
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   extalr_clk: extalr {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   /* External PCIe clock - can be overridden by the board */
+   pcie_bus_clk: pcie_bus {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   pmu_a57 {
+   compatible = "arm,cortex-a57-pmu";
+   interrupts-extended = < GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-affinity = <_0>, <_1>;
+   };
+
+   psci {
+   compatible = "arm,psci-1.0", "arm,psci-0.2";
+   method = "smc";
+   };
+
+   /* External SCIF clock - to be overridden by boards that provide it */
+   scif_clk: scif {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   soc {
+   compatible = "simple-bus";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   cpg: clock-controller@e615 {
+   compatible = "renesas,r8a774a1-cpg-mssr";
+   reg = <0 0xe615 0 0x0bb0>;
+   clocks = <_clk>, <_clk>;
+   clock-names = "extal", "extalr";
+   #clock-cells = <2>;
+   #power-domain-cells = <0>;
+   #reset-cells = <1>;
+   };
+
+   rst: reset-controller@e616 {
+   compatible = "renesas,r8a774a1-rst";
+   reg = <0 

[PATCH 36/58] arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instances

[Simon Horman]

From: Fabrizio Castro 

Add FCPF and FCPV instances to the r8a774a1 dtsi, similarly
to what was done for the r8a7796 with commit 41dbbf0c5b4e
("arm64: dts: r8a7796: Add FCPF and FCPV instances"),
commit 69490bc9665d ("arm64: dts: renesas: r8a7796: Point
FDP1 via FCPF to IPMMU-VI0"), and commit cef942d0bd89 ("arm64:
dts: renesas: r8a7796: Point VSPI via FCPVI to IPMMU-VC0").

Signed-off-by: Fabrizio Castro 
Reviewed-by: Biju Das 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 52 +++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 50c9265aa1c4..5d0109a376c2 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1385,6 +1385,58 @@
resets = < 408>;
};
 
+   fcpf0: fcp@fe95 {
+   compatible = "renesas,fcpf";
+   reg = <0 0xfe95 0 0x200>;
+   clocks = < CPG_MOD 615>;
+   power-domains = < 14>;
+   resets = < 615>;
+   };
+
+   fcpvb0: fcp@fe96f000 {
+   compatible = "renesas,fcpv";
+   reg = <0 0xfe96f000 0 0x200>;
+   clocks = < CPG_MOD 607>;
+   power-domains = < 14>;
+   resets = < 607>;
+   };
+
+   fcpvd0: fcp@fea27000 {
+   compatible = "renesas,fcpv";
+   reg = <0 0xfea27000 0 0x200>;
+   clocks = < CPG_MOD 603>;
+   power-domains = < 32>;
+   resets = < 603>;
+   iommus = <_vi0 8>;
+   };
+
+   fcpvd1: fcp@fea2f000 {
+   compatible = "renesas,fcpv";
+   reg = <0 0xfea2f000 0 0x200>;
+   clocks = < CPG_MOD 602>;
+   power-domains = < 32>;
+   resets = < 602>;
+   iommus = <_vi0 9>;
+   };
+
+   fcpvd2: fcp@fea37000 {
+   compatible = "renesas,fcpv";
+   reg = <0 0xfea37000 0 0x200>;
+   clocks = < CPG_MOD 601>;
+   power-domains = < 32>;
+   resets = < 601>;
+   iommus = <_vi0 10>;
+   };
+
+   fcpvi0: fcp@fe9af000 {
+   compatible = "renesas,fcpv";
+   reg = <0 0xfe9af000 0 0x200>;
+   clocks = < CPG_MOD 611>;
+   power-domains = < 14>;
+   resets = < 611>;
+   iommus = <_vc0 19>;
+   };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
-- 
2.11.0

[PATCH 21/58] arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes

[Simon Horman]

From: Biju Das 

Add sys-dmac[0-2] device nodes for RZ/G2M (r8a774a1) SoC.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 102 ++
 1 file changed, 102 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 8e63e9aee456..4a4cf352208e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,108 @@
#power-domain-cells = <1>;
};
 
+   dmac0: dma-controller@e670 {
+   compatible = "renesas,dmac-r8a774a1",
+"renesas,rcar-dmac";
+   reg = <0 0xe670 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 219>;
+   clock-names = "fck";
+   power-domains = < 32>;
+   resets = < 219>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
+   dmac1: dma-controller@e730 {
+   compatible = "renesas,dmac-r8a774a1",
+"renesas,rcar-dmac";
+   reg = <0 0xe730 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 218>;
+   clock-names = "fck";
+   power-domains = < 32>;
+   resets = < 218>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
+   dmac2: dma-controller@e731 {
+   compatible = "renesas,dmac-r8a774a1",
+"renesas,rcar-dmac";
+   reg = <0 0xe731 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 217>;
+   clock-names = "fck";
+   power-domains = < 32>;
+   resets = < 217>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
gic: interrupt-controller@f101 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
-- 
2.11.0

[PATCH 20/58] arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI support

[Simon Horman]

From: Sergei Shtylyov 

Define the Condor/V3HSK board dependent parts of the DU and  LVDS device
nodes. Also add the device nodes for Thine THC63LVD1024 LVDS decoder and
Analog Devices ADV7511W HDMI transmitter...

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 
Reviewed-by: Ulrich Hecht 
Reviewed-by: Laurent Pinchart 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 106 +++
 arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts  | 129 
 2 files changed, 235 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts 
b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 494f4ef37a4e..59db4c152fb8 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -45,6 +45,56 @@
regulator-boot-on;
regulator-always-on;
};
+
+   d1_8v: regulator-2 {
+   compatible = "regulator-fixed";
+   regulator-name = "D1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   hdmi-out {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+   };
+
+   lvds-decoder {
+   compatible = "thine,thc63lvd1024";
+   vcc-supply = <_3v>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   thc63lvd1024_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+
+   port@2 {
+   reg = <2>;
+   thc63lvd1024_out: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
+   };
+
+   x1_clk: x1-clock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <14850>;
+   };
 };
 
  {
@@ -74,6 +124,13 @@
};
 };
 
+ {
+   clocks = < CPG_MOD 724>,
+<_clk>;
+   clock-names = "du.0", "dclkin.0";
+   status = "okay";
+};
+
 _clk {
clock-frequency = <1666>;
 };
@@ -102,6 +159,55 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+   hdmi@39 {
+   compatible = "adi,adv7511w";
+   reg = <0x39>;
+   interrupt-parent = <>;
+   interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+   avdd-supply = <_8v>;
+   dvdd-supply = <_8v>;
+   pvdd-supply = <_8v>;
+   bgvdd-supply = <_8v>;
+   dvdd-3v-supply = <_3v>;
+
+   adi,input-depth = <8>;
+   adi,input-colorspace = "rgb";
+   adi,input-clock = "1x";
+   adi,input-style = <1>;
+   adi,input-justification = "evenly";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   adv7511_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   adv7511_out: endpoint {
+   remote-endpoint = <_con>;
+   };
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+
+   ports {
+   port@1 {
+   lvds0_out: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
 };
 
  {
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts 
b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
index 9147d8564557..44ab7344f8aa 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -27,6 +27,72 @@
/* first 128MB is reserved for secure area. */
reg = <0 0x4800 0 0x7800>;
};
+
+   hdmi-out {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con: endpoint {
+   remote-endpoint = 

[PATCH 24/58] arm64: dts: renesas: r8a774a1: Add Ethernet AVB node

[Simon Horman]

From: Fabrizio Castro 

This patch adds the SoC specific part of the Ethernet AVB
device tree node.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Biju Das 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 15d7785fb177..b771211a8444 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -350,6 +350,51 @@
dma-channels = <16>;
};
 
+   avb: ethernet@e680 {
+   compatible = "renesas,etheravb-r8a774a1",
+"renesas,etheravb-rcar-gen3";
+   reg = <0 0xe680 0 0x800>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+   interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+   clocks = < CPG_MOD 812>;
+   power-domains = < 32>;
+   resets = < 812>;
+   phy-mode = "rgmii";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
scif0: serial@e6e6 {
compatible = "renesas,scif-r8a774a1",
 "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.11.0

[PATCH 40/58] arm64: dts: renesas: r8a77980: add PCIe support

[Simon Horman]

From: Sergei Shtylyov 

Describe the PCIe PHY, PCIEC, and PCIe bus clock in the R8A77980 device
tree.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi | 49 +++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index c099053cf5fe..d58e9f2c9883 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,13 @@
clock-frequency = <0>;
};
 
+   /* External PCIe clock - can be overridden by the board */
+   pcie_bus_clk: pcie_bus {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@@ -437,6 +444,16 @@
status = "disabled";
};
 
+   pcie_phy: pcie-phy@e65d {
+   compatible = "renesas,r8a77980-pcie-phy";
+   reg = <0 0xe65d 0 0x8000>;
+   #phy-cells = <0>;
+   clocks = < CPG_MOD 319>;
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+   resets = < 319>;
+   status = "disabled";
+   };
+
canfd: can@e66c {
compatible = "renesas,r8a77980-canfd",
 "renesas,rcar-gen3-canfd";
@@ -1047,6 +1064,38 @@
resets = < 408>;
};
 
+   pciec: pcie@fe00 {
+   compatible = "renesas,pcie-r8a77980",
+"renesas,pcie-rcar-gen3";
+   reg = <0 0xfe00 0 0x8>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   bus-range = <0x00 0xff>;
+   device_type = "pci";
+   ranges = <
+   0x0100 0 0x 0 0xfe10 0 0x010
+   0x0200 0 0xfe20 0 0xfe20 0 0x020
+   0x0200 0 0x3000 0 0x3000 0 0x800
+   0x4200 0 0x3800 0 0x3800 0 0x800
+   >;
+   dma-ranges = <0x4200 0 0x4000 0 0x4000
+ 0 0x8000>;
+   interrupts = ,
+,
+;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0  GIC_SPI 148
+IRQ_TYPE_LEVEL_HIGH>;
+   clocks = < CPG_MOD 319>, <_bus_clk>;
+   clock-names = "pcie", "pcie_bus";
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+   resets = < 319>;
+   phys = <_phy>;
+   phy-names = "pcie";
+   status = "disabled";
+   };
+
vspd0: vsp@fea2 {
compatible = "renesas,vsp2";
reg = <0 0xfea2 0 0x5000>;
-- 
2.11.0

[PATCH 38/58] arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodes

[Simon Horman]

From: Biju Das 

Add usb dmac and hsusb device nodes on RZ/G2M SoC dtsi.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 45 +++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 3868f51e..b42117486b77 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -596,6 +596,51 @@
status = "disabled";
};
 
+   hsusb: usb@e659 {
+   compatible = "renesas,usbhs-r8a774a1",
+"renesas,rcar-gen3-usbhs";
+   reg = <0 0xe659 0 0x100>;
+   interrupts = ;
+   clocks = < CPG_MOD 704>;
+   dmas = <_dmac0 0>, <_dmac0 1>,
+  <_dmac1 0>, <_dmac1 1>;
+   dma-names = "ch0", "ch1", "ch2", "ch3";
+   renesas,buswait = <11>;
+   phys = <_phy0>;
+   phy-names = "usb";
+   power-domains = < 32>;
+   resets = < 704>;
+   status = "disabled";
+   };
+
+   usb_dmac0: dma-controller@e65a {
+   compatible = "renesas,r8a774a1-usb-dmac",
+"renesas,usb-dmac";
+   reg = <0 0xe65a 0 0x100>;
+   interrupts = ;
+   interrupt-names = "ch0", "ch1";
+   clocks = < CPG_MOD 330>;
+   power-domains = < 32>;
+   resets = < 330>;
+   #dma-cells = <1>;
+   dma-channels = <2>;
+   };
+
+   usb_dmac1: dma-controller@e65b {
+   compatible = "renesas,r8a774a1-usb-dmac",
+"renesas,usb-dmac";
+   reg = <0 0xe65b 0 0x100>;
+   interrupts = ;
+   interrupt-names = "ch0", "ch1";
+   clocks = < CPG_MOD 331>;
+   power-domains = < 32>;
+   resets = < 331>;
+   #dma-cells = <1>;
+   dma-channels = <2>;
+   };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a774a1",
 "renesas,rcar-dmac";
-- 
2.11.0

[PATCH 12/58] arm64: dts: renesas: salvator-common: adv748x: Override secondary addresses

[Simon Horman]

From: Kieran Bingham 

Ensure that the ADV748x device addresses do not conflict, and group them
together (visually in i2cdetect)

Signed-off-by: Kieran Bingham 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/salvator-common.dtsi | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi 
b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 7d3d866a0063..3b90f816dfef 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -420,7 +420,10 @@
 
video-receiver@70 {
compatible = "adi,adv7482";
-   reg = <0x70>;
+   reg = <0x70 0x71 0x72 0x73 0x74 0x75
+  0x60 0x61 0x62 0x63 0x64 0x65>;
+   reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
+   "infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
 
#address-cells = <1>;
#size-cells = <0>;
-- 
2.11.0

[PATCH 13/13] ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions

[Simon Horman]

From: Geert Uytterhoeven 

Replace the hardcoded clock indices by R9A06G032_CLK_* symbols.

Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Phil Edworthy 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r9a06g032.dtsi | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index afe29c95a006..3e45375b79aa 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include 
+#include 
 
 / {
compatible = "renesas,r9a06g032";
@@ -21,14 +22,14 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
-   clocks = < 84>;
+   clocks = < R9A06G032_CLK_A7MP>;
};
 
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <1>;
-   clocks = < 84>;
+   clocks = < R9A06G032_CLK_A7MP>;
enable-method = "renesas,r9a06g032-smp";
cpu-release-addr = <0 0x4000c204>;
};
@@ -82,7 +83,7 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
-   clocks = < 146>;
+   clocks = < R9A06G032_CLK_UART0>;
clock-names = "baudclk";
status = "disabled";
};
-- 
2.11.0

[PATCH 12/13] ARM: dts: Include R-Car Gen1 product name in DTSI files

[Simon Horman]

From: Magnus Damm 

Browsing the DTS for all the R-Car SoCs with similar part numbers
still makes my head hurt, so to improve the user friendliness of
the 32-bit ARM DTS code base include R-Car Gen1 product names for
each DTSI file.

Signed-off-by: Magnus Damm 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7778.dtsi | 2 +-
 arch/arm/boot/dts/r8a7779.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 1bce16cc6b20..05db0ccad7a6 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for Renesas r8a7778
+ * Device Tree Source for the R-Car M1A (R8A77781) SoC
  *
  * Copyright (C) 2013  Renesas Solutions Corp.
  * Copyright (C) 2013  Kuninori Morimoto 
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 03919714645a..3bc133d9489c 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for Renesas r8a7779
+ * Device Tree Source for the R-Car H1 (R8A77790) SoC
  *
  * Copyright (C) 2013 Renesas Solutions Corp.
  * Copyright (C) 2013 Simon Horman
-- 
2.11.0

[PATCH 35/58] arm64: dts: renesas: r8a774a1: Add audio support

[Simon Horman]

From: Biju Das 

Add sound support for the RZ/G2M SoC (a.k.a. R8A774A1).

This work is based on similar work done on the R8A7796 SoC
by Kuninori Morimoto .

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 275 ++
 1 file changed, 275 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index c9ac545f08f3..50c9265aa1c4 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1045,6 +1045,281 @@
status = "disabled";
};
 
+   rcar_sound: sound@ec50 {
+   /*
+* #sound-dai-cells is required
+*
+* Single DAI : #sound-dai-cells = <0>; <_sound>;
+* Multi  DAI : #sound-dai-cells = <1>; <_sound N>;
+*/
+   /*
+* #clock-cells is required for audio_clkout0/1/2/3
+*
+* clkout   : #clock-cells = <0>;   <_sound>;
+* clkout0/1/2/3: #clock-cells = <1>;   <_sound N>;
+*/
+   compatible =  "renesas,rcar_sound-r8a774a1", 
"renesas,rcar_sound-gen3";
+   reg =   <0 0xec50 0 0x1000>, /* SCU */
+   <0 0xec5a 0 0x100>,  /* ADG */
+   <0 0xec54 0 0x1000>, /* SSIU */
+   <0 0xec541000 0 0x280>,  /* SSI */
+   <0 0xec74 0 0x200>;  /* Audio DMAC peri 
peri*/
+   reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+   clocks = < CPG_MOD 1005>,
+< CPG_MOD 1006>, < CPG_MOD 1007>,
+< CPG_MOD 1008>, < CPG_MOD 1009>,
+< CPG_MOD 1010>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1013>,
+< CPG_MOD 1014>, < CPG_MOD 1015>,
+< CPG_MOD 1022>, < CPG_MOD 1023>,
+< CPG_MOD 1024>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1027>,
+< CPG_MOD 1028>, < CPG_MOD 1029>,
+< CPG_MOD 1030>, < CPG_MOD 1031>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<_clk_a>, <_clk_b>,
+<_clk_c>,
+< CPG_CORE 10>;
+   clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.9", "src.8", "src.7", "src.6",
+ "src.5", "src.4", "src.3", "src.2",
+ "src.1", "src.0",
+ "mix.1", "mix.0",
+ "ctu.1", "ctu.0",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+   power-domains = < 32>;
+   resets = < 1005>,
+< 1006>, < 1007>,
+< 1008>, < 1009>,
+< 1010>, < 1011>,
+< 1012>, < 1013>,
+< 1014>, < 1015>;
+   reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+   status = "disabled";
+
+   rcar_sound,dvc {
+   dvc0: dvc-0 {
+   dmas = < 0xbc>;
+   dma-names = "tx";
+   };
+   dvc1: dvc-1 {
+   dmas = < 0xbe>;
+   dma-names = "tx";
+   };
+   };
+
+   rcar_sound,mix {
+   mix0: mix-0 { };
+   mix1: mix-1 { };
+   };
+
+   rcar_sound,ctu {
+   ctu00: ctu-0 { };
+  

[PATCH 19/58] arm64: dts: renesas: v3msk: add eMMC support

[Simon Horman]

From: Sergei Shtylyov 

Add the eMMC chip support for the V3M Started Kit board.

Based on the original (and large) patches by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts 
b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
index 8eac8ca6550b..0dbcb418 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -51,6 +51,15 @@
regulator-always-on;
};
 
+   vcc_vddq_vin0: regulator-2 {
+   compatible = "regulator-fixed";
+   regulator-name = "VCC_VDDQ_VIN0";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <_d3_3v>;
@@ -128,6 +137,12 @@
function = "i2c0";
};
 
+   mmc_pins: mmc_3_3v {
+   groups = "mmc_data8", "mmc_ctrl";
+   function = "mmc";
+   power-source = <3300>;
+   };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@@ -192,6 +207,17 @@
};
 };
 
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   vmmc-supply = <_d3_3v>;
+   vqmmc-supply = <_vddq_vin0>;
+   bus-width = <8>;
+   non-removable;
+   status = "okay";
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
-- 
2.11.0

[PATCH 45/58] arm64: dts: renesas: r8a77965: Move timer node

[Simon Horman]

From: Geert Uytterhoeven 

To preserve alphabetical sort order.

Fixes: 4c529600eef0a6b7 ("arm64: dts: renesas: r8a77965: Add R-Car Gen3 thermal 
support")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Niklas Söderlund 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 83f469d6a680..7f477a15fa59 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1932,14 +1932,6 @@
};
};
 
-   timer {
-   compatible = "arm,armv8-timer";
-   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>;
-   };
-
thermal-zones {
sensor_thermal1: sensor-thermal1 {
polling-delay-passive = <250>;
@@ -1984,6 +1976,14 @@
};
};
 
+   timer {
+   compatible = "arm,armv8-timer";
+   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>;
+   };
+
/* External USB clocks - can be overridden by the board */
usb3s0_clk: usb3s0 {
compatible = "fixed-clock";
-- 
2.11.0

[PATCH 30/58] arm64: dts: renesas: r8a774a1: Add RZ/G2M thermal support

[Simon Horman]

From: Biju Das 

Add thermal support for R8A774A1 (RZ/G2M) SoC.

Based on the work done for r8a7796 SoC.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 60 +++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index ced254601364..02620c89e004 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -290,6 +290,21 @@
#power-domain-cells = <1>;
};
 
+   tsc: thermal@e6198000 {
+   compatible = "renesas,r8a774a1-thermal";
+   reg = <0 0xe6198000 0 0x100>,
+ <0 0xe61a 0 0x100>,
+ <0 0xe61a8000 0 0x100>;
+   interrupts = ,
+,
+;
+   clocks = < CPG_MOD 522>;
+   power-domains = < 32>;
+   resets = < 522>;
+   #thermal-sensor-cells = <1>;
+   status = "okay";
+   };
+
intc_ex: interrupt-controller@e61c {
compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
#interrupt-cells = <2>;
@@ -840,6 +855,51 @@
};
};
 
+   thermal-zones {
+   sensor_thermal1: sensor-thermal1 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = < 0>;
+
+   trips {
+   sensor1_crit: sensor1-crit {
+   temperature = <12>;
+   hysteresis = <1000>;
+   type = "critical";
+   };
+   };
+   };
+
+   sensor_thermal2: sensor-thermal2 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   sensor2_crit: sensor2-crit {
+   temperature = <12>;
+   hysteresis = <1000>;
+   type = "critical";
+   };
+   };
+
+   };
+
+   sensor_thermal3: sensor-thermal3 {
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = < 2>;
+
+   trips {
+   sensor3_crit: sensor3-crit {
+   temperature = <12>;
+   hysteresis = <1000>;
+   type = "critical";
+   };
+   };
+   };
+   };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
-- 
2.11.0

[PATCH 48/58] arm64: dts: renesas: salvator-xs: Improve SATA switch settings comments

[Simon Horman]

From: Geert Uytterhoeven 

The comments describing the non-default switch settings to use SATA are
confusing: 'Off' refers to the switch position, not to the MD12 logic
value, while the parentheses suggest otherwise.  Rephrase to fix this.

Fixes: bec000784d5bb571 ("arm64: dts: renesas: salvator-xs: enable SATA")
Signed-off-by: Geert Uytterhoeven 
Acked-by: Wolfram Sang 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts  | 2 +-
 arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index ba3357636fdb..cf08a119eec0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -184,7 +184,7 @@
};
 };
 
-/* MD12 (SW12-7) must be set 'Off' which is not the default! */
+/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
  {
status = "okay";
 };
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts 
b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
index 45016a06fab1..f03a5e9e0c42 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77965-salvator-xs.dts
@@ -57,7 +57,7 @@
};
 };
 
-/* MD12 (SW12-7) must be set 'Off' which is not the default! */
+/* SW12-7 must be set 'Off' (MD12 set to 1) which is not the default! */
  {
status = "okay";
 };
-- 
2.11.0

[PATCH 57/58] arm64: dts: renesas: draak: Sort device nodes

[Simon Horman]

From: Geert Uytterhoeven 

- Device nodes with unit addresses are sorted by unit address,
  - Device nodes without unit addresses and references are sorted
alphabetically.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 276 -
 1 file changed, 138 insertions(+), 138 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts 
b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index a8e8f2669d4c..e39b73005381 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -24,38 +24,6 @@
stdout-path = "serial0:115200n8";
};
 
-   vga {
-   compatible = "vga-connector";
-
-   port {
-   vga_in: endpoint {
-   remote-endpoint = <_out>;
-   };
-   };
-   };
-
-   vga-encoder {
-   compatible = "adi,adv7123";
-
-   ports {
-   #address-cells = <1>;
-   #size-cells = <0>;
-
-   port@0 {
-   reg = <0>;
-   adv7123_in: endpoint {
-   remote-endpoint = <_out_rgb>;
-   };
-   };
-   port@1 {
-   reg = <1>;
-   adv7123_out: endpoint {
-   remote-endpoint = <_in>;
-   };
-   };
-   };
-   };
-
composite-in {
compatible = "composite-video-connector";
 
@@ -101,76 +69,86 @@
regulator-always-on;
};
 
-   x12_clk: x12 {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <7425>;
-   };
-};
-
-_clk {
-   clock-frequency = <4800>;
-};
+   vga {
+   compatible = "vga-connector";
 
- {
-   avb0_pins: avb {
-   mux {
-   groups = "avb0_link", "avb0_mdio", "avb0_mii";
-   function = "avb0";
+   port {
+   vga_in: endpoint {
+   remote-endpoint = <_out>;
+   };
};
};
 
-   du_pins: du {
-   groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
-   function = "du";
-   };
+   vga-encoder {
+   compatible = "adi,adv7123";
 
-   i2c0_pins: i2c0 {
-   groups = "i2c0";
-   function = "i2c0";
-   };
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
 
-   i2c1_pins: i2c1 {
-   groups = "i2c1";
-   function = "i2c1";
+   port@0 {
+   reg = <0>;
+   adv7123_in: endpoint {
+   remote-endpoint = <_out_rgb>;
+   };
+   };
+   port@1 {
+   reg = <1>;
+   adv7123_out: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
};
 
-   pwm0_pins: pwm0 {
-   groups = "pwm0_c";
-   function = "pwm0";
+   x12_clk: x12 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <7425>;
};
+};
 
-   pwm1_pins: pwm1 {
-   groups = "pwm1_c";
-   function = "pwm1";
-   };
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   renesas,no-ether-link;
+   phy-handle = <>;
+   phy-mode = "rgmii-txid";
+   status = "okay";
 
-   scif2_pins: scif2 {
-   groups = "scif2_data";
-   function = "scif2";
+   phy0: ethernet-phy@0 {
+   rxc-skew-ps = <1500>;
+   reg = <0>;
+   interrupt-parent = <>;
+   interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
};
+};
 
-   sdhi2_pins: sd2 {
-   groups = "mmc_data8", "mmc_ctrl";
-   function = "mmc";
-   power-source = <1800>;
-   };
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "okay";
 
-   sdhi2_pins_uhs: sd2_uhs {
-   groups = "mmc_data8", "mmc_ctrl";
-   function = "mmc";
-   power-source = <1800>;
-   };
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+<_clk>;
+   clock-names = "du.0", "du.1", "dclkin.0";
 
-   

[PATCH 26/58] arm64: dts: renesas: r8a774a1: Add pinctrl device node

[Simon Horman]

From: Fabrizio Castro 

This patch adds pinctrl device node for R8A774A1 SoC.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Biju Das 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b9a381808417..c956bf7ecde9 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -133,6 +133,11 @@
status = "disabled";
};
 
+   pfc: pin-controller@e606 {
+   compatible = "renesas,pfc-r8a774a1";
+   reg = <0 0xe606 0 0x50c>;
+   };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a774a1-cpg-mssr";
reg = <0 0xe615 0 0x0bb0>;
-- 
2.11.0

[PATCH 28/58] arm64: dts: renesas: r8a774a1: Add SDHI nodes

[Simon Horman]

From: Fabrizio Castro 

Add SDHI nodes to the DT of the r8a774a1 SoC.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Biju Das 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 48 +++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 4c251c48619b..51ac94f266ae 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -627,6 +627,54 @@
status = "disabled";
};
 
+   sdhi0: sd@ee10 {
+   compatible = "renesas,sdhi-r8a774a1",
+"renesas,rcar-gen3-sdhi";
+   reg = <0 0xee10 0 0x2000>;
+   interrupts = ;
+   clocks = < CPG_MOD 314>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 314>;
+   status = "disabled";
+   };
+
+   sdhi1: sd@ee12 {
+   compatible = "renesas,sdhi-r8a774a1",
+"renesas,rcar-gen3-sdhi";
+   reg = <0 0xee12 0 0x2000>;
+   interrupts = ;
+   clocks = < CPG_MOD 313>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 313>;
+   status = "disabled";
+   };
+
+   sdhi2: sd@ee14 {
+   compatible = "renesas,sdhi-r8a774a1",
+"renesas,rcar-gen3-sdhi";
+   reg = <0 0xee14 0 0x2000>;
+   interrupts = ;
+   clocks = < CPG_MOD 312>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 312>;
+   status = "disabled";
+   };
+
+   sdhi3: sd@ee16 {
+   compatible = "renesas,sdhi-r8a774a1",
+"renesas,rcar-gen3-sdhi";
+   reg = <0 0xee16 0 0x2000>;
+   interrupts = ;
+   clocks = < CPG_MOD 311>;
+   max-frequency = <2>;
+   power-domains = < 32>;
+   resets = < 311>;
+   status = "disabled";
+   };
+
gic: interrupt-controller@f101 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
-- 
2.11.0

[PATCH 42/58] arm64: dts: renesas: r8a77965: m3nulcb-kf: Initial device tree

[Simon Horman]

From: Eugeniu Rosca 

This is based on the existing KF device tree sources:
$ ls -1 arch/arm64/boot/dts/renesas/*-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-es1-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7795-h3ulcb-kf.dts
arch/arm64/boot/dts/renesas/r8a7796-m3ulcb-kf.dts

Signed-off-by: Eugeniu Rosca 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/Makefile|  1 +
 arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts | 16 
 2 files changed, 17 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile 
b/arch/arm64/boot/dts/renesas/Makefile
index eb158d1f90e9..a8ce6594342d 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb.dtb
+dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
 dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
 dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts 
b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts
new file mode 100644
index ..dadad97051b9
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb-kf.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the M3NULCB Kingfisher board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+#include "r8a77965-m3nulcb.dts"
+#include "ulcb-kf.dtsi"
+
+/ {
+   model = "Renesas M3NULCB Kingfisher board based on r8a77965";
+   compatible = "shimafuji,kingfisher", "renesas,m3nulcb",
+"renesas,r8a77965";
+};
-- 
2.11.0

[PATCH 03/58] arm64: dts: renesas: r8a77995: Attach the SYS-DMAC to the IPMMU

[Simon Horman]

From: Magnus Damm 

Hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to IPMMU-DS0 and IPMMU-DS1
following the R-Car Gen3 Rev.1.00 (April 2018) datasheet.

Signed-off-by: Magnus Damm 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77995.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index c94513ce5b9b..625ba2b302c7 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -391,6 +391,10 @@
resets = < 219>;
#dma-cells = <1>;
dma-channels = <8>;
+   iommus = <_ds0 0>, <_ds0 1>,
+  <_ds0 2>, <_ds0 3>,
+  <_ds0 4>, <_ds0 5>,
+  <_ds0 6>, <_ds0 7>;
};
 
dmac1: dma-controller@e730 {
@@ -415,6 +419,10 @@
resets = < 218>;
#dma-cells = <1>;
dma-channels = <8>;
+   iommus = <_ds1 0>, <_ds1 1>,
+  <_ds1 2>, <_ds1 3>,
+  <_ds1 4>, <_ds1 5>,
+  <_ds1 6>, <_ds1 7>;
};
 
dmac2: dma-controller@e731 {
@@ -439,6 +447,10 @@
resets = < 217>;
#dma-cells = <1>;
dma-channels = <8>;
+   iommus = <_ds1 16>, <_ds1 17>,
+  <_ds1 18>, <_ds1 19>,
+  <_ds1 20>, <_ds1 21>,
+  <_ds1 22>, <_ds1 23>;
};
 
ipmmu_ds0: mmu@e674 {
-- 
2.11.0

[PATCH 06/58] arm64: dts: renesas: r8a77990: Enable PWM for Ebisu board

[Simon Horman]

From: Yoshihiro Shimoda 

This patch adds PWM device nodes and enables PWM3 and PWM5 for
R-Car E3 Ebisu board. These devices are used for backlight control.

Signed-off-by: Yoshihiro Shimoda 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 24 +
 arch/arm64/boot/dts/renesas/r8a77990.dtsi  | 70 ++
 2 files changed, 94 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts 
b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 2bc3a4884b00..31934a310ac3 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -67,6 +67,16 @@
};
};
 
+   pwm3_pins: pwm3 {
+   groups = "pwm3_b";
+   function = "pwm3";
+   };
+
+   pwm5_pins: pwm5 {
+   groups = "pwm5_a";
+   function = "pwm5";
+   };
+
usb0_pins: usb {
groups = "usb0_b";
function = "usb0";
@@ -78,6 +88,20 @@
};
 };
 
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   status = "okay";
+};
+
  {
timeout-sec = <60>;
status = "okay";
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 2c8f1194e6b5..2ee0edfb18d4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -337,6 +337,76 @@
status = "disabled";
};
 
+   pwm0: pwm@e6e3 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e3 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm1: pwm@e6e31000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e31000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm2: pwm@e6e32000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e32000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm3: pwm@e6e33000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e33000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm4: pwm@e6e34000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e34000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm5: pwm@e6e35000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e35000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
+   pwm6: pwm@e6e36000 {
+   compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
+   reg = <0 0xe6e36000 0 0x8>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 523>;
+   #pwm-cells = <2>;
+   status = "disabled";
+   };
+
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77990",
 "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.11.0

[PATCH 37/58] arm64: dts: renesas: r8a774a1: Add USB2.0 phy and host(EHCI/OHCI) device nodes

[Simon Horman]

From: Biju Das 

Add USB2.0 phy and host (EHCI/OHCI) device nodes on RZ/G2M SoC dtsi.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 73 +++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 5d0109a376c2..3868f51e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1320,6 +1320,79 @@
dma-channels = <16>;
};
 
+   ohci0: usb@ee08 {
+   compatible = "generic-ohci";
+   reg = <0 0xee08 0 0x100>;
+   interrupts = ;
+   clocks = < CPG_MOD 703>;
+   phys = <_phy0>;
+   phy-names = "usb";
+   power-domains = < 32>;
+   resets = < 703>;
+   status = "disabled";
+   };
+
+   ohci1: usb@ee0a {
+   compatible = "generic-ohci";
+   reg = <0 0xee0a 0 0x100>;
+   interrupts = ;
+   clocks = < CPG_MOD 702>;
+   phys = <_phy1>;
+   phy-names = "usb";
+   power-domains = < 32>;
+   resets = < 702>;
+   status = "disabled";
+   };
+
+   ehci0: usb@ee080100 {
+   compatible = "generic-ehci";
+   reg = <0 0xee080100 0 0x100>;
+   interrupts = ;
+   clocks = < CPG_MOD 703>;
+   phys = <_phy0>;
+   phy-names = "usb";
+   companion= <>;
+   power-domains = < 32>;
+   resets = < 703>;
+   status = "disabled";
+   };
+
+   ehci1: usb@ee0a0100 {
+   compatible = "generic-ehci";
+   reg = <0 0xee0a0100 0 0x100>;
+   interrupts = ;
+   clocks = < CPG_MOD 702>;
+   phys = <_phy1>;
+   phy-names = "usb";
+   companion= <>;
+   power-domains = < 32>;
+   resets = < 702>;
+   status = "disabled";
+   };
+
+   usb2_phy0: usb-phy@ee080200 {
+   compatible = "renesas,usb2-phy-r8a774a1",
+"renesas,rcar-gen3-usb2-phy";
+   reg = <0 0xee080200 0 0x700>;
+   interrupts = ;
+   clocks = < CPG_MOD 703>;
+   power-domains = < 32>;
+   resets = < 703>;
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
+   usb2_phy1: usb-phy@ee0a0200 {
+   compatible = "renesas,usb2-phy-r8a774a1",
+"renesas,rcar-gen3-usb2-phy";
+   reg = <0 0xee0a0200 0 0x700>;
+   clocks = < CPG_MOD 702>;
+   power-domains = < 32>;
+   resets = < 702>;
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
sdhi0: sd@ee10 {
compatible = "renesas,sdhi-r8a774a1",
 "renesas,rcar-gen3-sdhi";
-- 
2.11.0

[PATCH 01/58] arm64: dts: renesas: r8a77980: add RWDT support

[Simon Horman]

From: Sergei Shtylyov 

Describe RWDT in the R8A77980 SoC device tree.

Enable RWDT on the Condor and V3H Starter Kit boards.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77980-condor.dts |  5 +
 arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts  |  5 +
 arch/arm64/boot/dts/renesas/r8a77980.dtsi   | 10 ++
 3 files changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts 
b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 9f25c407dfd7..494f4ef37a4e 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -156,6 +156,11 @@
};
 };
 
+ {
+   timeout-sec = <60>;
+   status = "okay";
+};
+
  {
pinctrl-0 = <_pins>, <_clk_pins>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts 
b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
index 9dac42f8f804..9147d8564557 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -71,6 +71,11 @@
};
 };
 
+ {
+   timeout-sec = <60>;
+   status = "okay";
+};
+
  {
pinctrl-0 = <_pins>, <_clk_pins>;
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index b8c9a56562f2..4a1097e32551 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -118,6 +118,16 @@
#size-cells = <2>;
ranges;
 
+   rwdt: watchdog@e602 {
+   compatible = "renesas,r8a77980-wdt",
+"renesas,rcar-gen3-wdt";
+   reg = <0 0xe602 0 0x0c>;
+   clocks = < CPG_MOD 402>;
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+   resets = < 402>;
+   status = "disabled";
+   };
+
gpio0: gpio@e605 {
compatible = "renesas,gpio-r8a77980",
 "renesas,rcar-gen3-gpio";
-- 
2.11.0

[PATCH 11/58] arm64: dts: renesas: r8a77980: add CSI2/VIN support

[Simon Horman]

From: Sergei Shtylyov 

Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.

Signed-off-by: Sergei Shtylyov 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++
 1 file changed, 374 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4bc99d6763ce..c099053cf5fe 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
 
+   vin0: video@e6ef {
+   compatible = "renesas,vin-r8a77980";
+   reg = <0 0xe6ef 0 0x1000>;
+   interrupts = ;
+   clocks = < CPG_MOD 811>;
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+   resets = < 811>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg = <1>;
+
+   vin0csi40: endpoint@2 {
+   reg = <2>;
+   remote-endpoint= <>;
+   };
+   };
+   };
+   };
+
+   vin1: video@e6ef1000 {
+   compatible = "renesas,vin-r8a77980";
+   reg = <0 0xe6ef1000 0 0x1000>;
+   interrupts = ;
+   clocks = < CPG_MOD 810>;
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+   status = "disabled";
+   resets = < 810>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg = <1>;
+
+   vin1csi40: endpoint@2 {
+   reg = <2>;
+   remote-endpoint= <>;
+   };
+   };
+   };
+   };
+
+   vin2: video@e6ef2000 {
+   compatible = "renesas,vin-r8a77980";
+   reg = <0 0xe6ef2000 0 0x1000>;
+   interrupts = ;
+   clocks = < CPG_MOD 809>;
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+   resets = < 809>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg = <1>;
+
+   vin2csi40: endpoint@2 {
+   reg = <2>;
+   remote-endpoint= <>;
+   };
+   };
+   };
+   };
+
+   vin3: video@e6ef3000 {
+   compatible = "renesas,vin-r8a77980";
+   reg = <0 0xe6ef3000 0 0x1000>;
+   interrupts = ;
+   clocks = < CPG_MOD 808>;
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+   resets = < 808>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg = <1>;
+
+   vin3csi40: endpoint@2 {
+   reg = <2>;
+   remote-endpoint= <>;
+   };
+   };
+   };
+   };
+
+   vin4: video@e6ef4000 {
+   compatible = "renesas,vin-r8a77980";

[PATCH 15/58] arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes

[Simon Horman]

From: Eugeniu Rosca 

According to R-Car Gen3 HW manual rev1.00, R-Car M3-N has two CAN
interfaces, similar to H3, M3-W and other SoCs from the same family.

Add CAN placeholder nodes to avoid below DTC errors:
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:19.1-6 Label or path can0 not 
found
Error: arch/arm64/boot/dts/renesas/ulcb-kf.dtsi:25.1-6 Label or path can1 not 
found

These errors occur *after* the addition of r8a77965-m3nulcb-kf.dts.
Fix them beforehand.

CAN support is inspired from below commits:
 - v4.7 commit 308b7e4ba62e ("arm64: dts: r8a7795: Add CAN support")
 - v4.11 commit 909c16252415 ("arm64: dts: r8a7796: Add CAN support")
 - v4.12 commit bec0948e810f ("arm64: dts: r8a7796: Add reset control 
properties")

Signed-off-by: Eugeniu Rosca 
Reviewed-by: Kieran Bingham 
[simon: make placeholder minimal by only including reg property]
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 7a75c351edd2..e7128fb65e33 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -862,6 +862,16 @@
status = "disabled";
};
 
+   can0: can@e6c3 {
+   reg = <0 0xe6c3 0 0x1000>;
+   /* placeholder */
+   };
+
+   can1: can@e6c38000 {
+   reg = <0 0xe6c38000 0 0x1000>;
+   /* placeholder */
+   };
+
pwm0: pwm@e6e3 {
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
reg = <0 0xe6e3 0 8>;
-- 
2.11.0

[PATCH 09/58] arm64: dts: renesas: r8a77965: Add SATA controller node

[Simon Horman]

From: Takeshi Kihara 

This patch adds SATA controller node for the R8A77965 SoC.

Signed-off-by: Takeshi Kihara 
[wsa: rebased to upstream base]
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Wolfram Sang 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 9c4f40589cbd..52205be430d0 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1507,6 +1507,17 @@
status = "disabled";
};
 
+   sata: sata@ee30 {
+   compatible = "renesas,sata-r8a77965",
+"renesas,rcar-gen3-sata";
+   reg = <0 0xee30 0 0x20>;
+   interrupts = ;
+   clocks = < CPG_MOD 815>;
+   power-domains = < R8A77965_PD_ALWAYS_ON>;
+   resets = < 815>;
+   status = "disabled";
+   };
+
gic: interrupt-controller@f101 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
-- 
2.11.0

[PATCH 29/58] arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS support

[Simon Horman]

From: Biju Das 

Add the I2C[0-6] and IIC Bus Interface for DVFS (IIC for DVFS)
devices nodes to the r8a774a1 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Reviewed-by: Simon Horman 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 142 ++
 1 file changed, 142 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 51ac94f266ae..ced254601364 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -14,6 +14,17 @@
#address-cells = <2>;
#size-cells = <2>;
 
+   aliases {
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   i2c3 = 
+   i2c4 = 
+   i2c5 = 
+   i2c6 = 
+   i2c7 = _dvfs;
+   };
+
/*
 * The external audio clocks are configured as 0 Hz fixed frequency
 * clocks by default.
@@ -295,6 +306,137 @@
resets = < 407>;
};
 
+   i2c0: i2c@e650 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe650 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 931>;
+   power-domains = < 32>;
+   resets = < 931>;
+   dmas = < 0x91>, < 0x90>,
+  < 0x91>, < 0x90>;
+   dma-names = "tx", "rx", "tx", "rx";
+   i2c-scl-internal-delay-ns = <110>;
+   status = "disabled";
+   };
+
+   i2c1: i2c@e6508000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe6508000 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 930>;
+   power-domains = < 32>;
+   resets = < 930>;
+   dmas = < 0x93>, < 0x92>,
+  < 0x93>, < 0x92>;
+   dma-names = "tx", "rx", "tx", "rx";
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c2: i2c@e651 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe651 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 929>;
+   power-domains = < 32>;
+   resets = < 929>;
+   dmas = < 0x95>, < 0x94>,
+  < 0x95>, < 0x94>;
+   dma-names = "tx", "rx", "tx", "rx";
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c3: i2c@e66d {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe66d 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 928>;
+   power-domains = < 32>;
+   resets = < 928>;
+   dmas = < 0x97>, < 0x96>;
+   dma-names = "tx", "rx";
+   i2c-scl-internal-delay-ns = <110>;
+   status = "disabled";
+   };
+
+   i2c4: i2c@e66d8000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a774a1",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe66d8000 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 927>;
+   power-domains = < 32>;
+   resets = < 927>;
+   dmas = < 0x99>, < 0x98>;
+   dma-names = "tx", "rx";
+   i2c-scl-internal-delay-ns = <110>;
+   status = "disabled";
+   };
+
+   i2c5: i2c@e66e {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a774a1",
+ 

[PATCH 05/58] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support

[Simon Horman]

From: Sergei Shtylyov 

Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
the R8A77980 SoC's device tree.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index d3532fd4c94a..1013da3e2ec4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,15 @@
clock-frequency = <0>;
};
 
+   pmu_a53 {
+   compatible = "arm,cortex-a53-pmu";
+   interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-affinity = <_0>, <_1>, <_2>, <_3>;
+   };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
-- 
2.11.0

[PATCH 16/58] arm64: dts: renesas: r8a77965: m3nulcb: Initial device tree

[Simon Horman]

From: Eugeniu Rosca 

Allow the bare M3-N-based ULCB board to boot.

Signed-off-by: Eugeniu Rosca 
Reviewed-by: Jacopo Mondi 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/Makefile |  1 +
 arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts | 33 
 2 files changed, 34 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile 
b/arch/arm64/boot/dts/renesas/Makefile
index 9e2394bc3c62..eb158d1f90e9 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb 
r8a7796-m3ulcb.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
 dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
+dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-m3nulcb.dtb
 dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
 dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
 dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts 
b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts
new file mode 100644
index ..964078b6cc49
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77965-m3nulcb.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77965.dtsi"
+#include "ulcb.dtsi"
+
+/ {
+   model = "Renesas M3NULCB board based on r8a77965";
+   compatible = "renesas,m3nulcb", "renesas,r8a77965";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+};
+
+ {
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 721>,
+< 1>,
+< 3>,
+< 2>;
+   clock-names = "du.0", "du.1", "du.3",
+ "dclkin.0", "dclkin.1", "dclkin.3";
+};
-- 
2.11.0

[PATCH 14/58] arm64: dts: renesas: r8a77965: Attach the SYS-DMAC to the IPMMU

[Simon Horman]

From: Magnus Damm 

For R-Car M3-N hook up SYS-DMAC0, SYS-DMAC1 and SYS-DMAC2 to
IPMMU-DS0 and IPMMU-DS1 in same way as for R-Car M3-W.
This follows the R-Car Gen3 Rev.1.00 (April 2018) datasheet.

Signed-off-by: Magnus Damm 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 24 
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 52205be430d0..7a75c351edd2 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -634,6 +634,14 @@
resets = < 219>;
#dma-cells = <1>;
dma-channels = <16>;
+   iommus = <_ds0 0>, <_ds0 1>,
+  <_ds0 2>, <_ds0 3>,
+  <_ds0 4>, <_ds0 5>,
+  <_ds0 6>, <_ds0 7>,
+  <_ds0 8>, <_ds0 9>,
+  <_ds0 10>, <_ds0 11>,
+  <_ds0 12>, <_ds0 13>,
+  <_ds0 14>, <_ds0 15>;
};
 
dmac1: dma-controller@e730 {
@@ -668,6 +676,14 @@
resets = < 218>;
#dma-cells = <1>;
dma-channels = <16>;
+   iommus = <_ds1 0>, <_ds1 1>,
+  <_ds1 2>, <_ds1 3>,
+  <_ds1 4>, <_ds1 5>,
+  <_ds1 6>, <_ds1 7>,
+  <_ds1 8>, <_ds1 9>,
+  <_ds1 10>, <_ds1 11>,
+  <_ds1 12>, <_ds1 13>,
+  <_ds1 14>, <_ds1 15>;
};
 
dmac2: dma-controller@e731 {
@@ -702,6 +718,14 @@
resets = < 217>;
#dma-cells = <1>;
dma-channels = <16>;
+   iommus = <_ds1 16>, <_ds1 17>,
+  <_ds1 18>, <_ds1 19>,
+  <_ds1 20>, <_ds1 21>,
+  <_ds1 22>, <_ds1 23>,
+  <_ds1 24>, <_ds1 25>,
+  <_ds1 26>, <_ds1 27>,
+  <_ds1 28>, <_ds1 29>,
+  <_ds1 30>, <_ds1 31>;
};
 
ipmmu_ds0: mmu@e674 {
-- 
2.11.0

[PATCH 07/58] arm64: dts: renesas: r8a77980: move IPMMU nodes

[Simon Horman]

From: Sergei Shtylyov 

The IPMMU nodes should follow the GEther node, not the CAN-FD node,
according to the  part of the startng IPMMU-DS1 node.
While moving the nodes, also do sort them by label alphanumerically...

Signed-off-by: Sergei Shtylyov 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi | 126 +++---
 1 file changed, 63 insertions(+), 63 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 1013da3e2ec4..fbfe65476443 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -462,69 +462,6 @@
};
};
 
-   ipmmu_ds1: mmu@e774 {
-   compatible = "renesas,ipmmu-r8a77980";
-   reg = <0 0xe774 0 0x1000>;
-   renesas,ipmmu-main = <_mm 0>;
-   power-domains = < R8A77980_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
-   ipmmu_vip0: mmu@e7b0 {
-   compatible = "renesas,ipmmu-r8a77980";
-   reg = <0 0xe7b0 0 0x1000>;
-   power-domains = < R8A77980_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
-   ipmmu_vip1: mmu@e796 {
-   compatible = "renesas,ipmmu-r8a77980";
-   reg = <0 0xe796 0 0x1000>;
-   power-domains = < R8A77980_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
-   ipmmu_ir: mmu@ff8b {
-   compatible = "renesas,ipmmu-r8a77980";
-   reg = <0 0xff8b 0 0x1000>;
-   renesas,ipmmu-main = <_mm 3>;
-   power-domains = < R8A77980_PD_A3IR>;
-   #iommu-cells = <1>;
-   };
-
-   ipmmu_mm: mmu@e67b {
-   compatible = "renesas,ipmmu-r8a77980";
-   reg = <0 0xe67b 0 0x1000>;
-   interrupts = ,
-;
-   power-domains = < R8A77980_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
-   ipmmu_rt: mmu@ffc8 {
-   compatible = "renesas,ipmmu-r8a77980";
-   reg = <0 0xffc8 0 0x1000>;
-   renesas,ipmmu-main = <_mm 10>;
-   power-domains = < R8A77980_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
-   ipmmu_vc0: mmu@fe6b {
-   compatible = "renesas,ipmmu-r8a77980";
-   reg = <0 0xfe6b 0 0x1000>;
-   renesas,ipmmu-main = <_mm 12>;
-   power-domains = < R8A77980_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
-   ipmmu_vi0: mmu@febd {
-   compatible = "renesas,ipmmu-r8a77980";
-   reg = <0 0xfebd 0 0x1000>;
-   renesas,ipmmu-main = <_mm 14>;
-   power-domains = < R8A77980_PD_ALWAYS_ON>;
-   #iommu-cells = <1>;
-   };
-
avb: ethernet@e680 {
compatible = "renesas,etheravb-r8a77980",
 "renesas,etheravb-rcar-gen3";
@@ -722,6 +659,69 @@
status = "disabled";
};
 
+   ipmmu_ds1: mmu@e774 {
+   compatible = "renesas,ipmmu-r8a77980";
+   reg = <0 0xe774 0 0x1000>;
+   renesas,ipmmu-main = <_mm 0>;
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_ir: mmu@ff8b {
+   compatible = "renesas,ipmmu-r8a77980";
+   reg = <0 0xff8b 0 0x1000>;
+   renesas,ipmmu-main = <_mm 3>;
+   power-domains = < R8A77980_PD_A3IR>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_mm: mmu@e67b {
+   compatible = "renesas,ipmmu-r8a77980";
+   reg = <0 0xe67b 0 0x1000>;
+   interrupts = ,
+;
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+   #iommu-cells = <1>;
+   };
+
+   ipmmu_rt: mmu@ffc8 {
+   compatible = "renesas,ipmmu-r8a77980";
+   reg = <0 0xffc8 0 0x1000>;
+   renesas,ipmmu-main = <_mm 10>;
+   power-domains = < R8A77980_PD_ALWAYS_ON>;
+

[PATCH 18/58] arm64: dts: renesas: r8a77970: add MMC support

[Simon Horman]

From: Sergei Shtylyov 

Define the generic R8A77970 part of the MMC0 (SDHI2) device node.

Based on the original (and large) patches by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77970.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 6c0832f23811..b71f3eca35bd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -754,6 +754,18 @@
#iommu-cells = <1>;
};
 
+   mmc0: mmc@ee14 {
+   compatible = "renesas,sdhi-r8a77970",
+"renesas,rcar-gen3-sdhi";
+   reg = <0 0xee14 0 0x2000>;
+   interrupts = ;
+   clocks = < CPG_MOD 314>;
+   power-domains = < R8A77970_PD_ALWAYS_ON>;
+   resets = < 314>;
+   max-frequency = <2>;
+   status = "disabled";
+   };
+
gic: interrupt-controller@f101 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
-- 
2.11.0

[PATCH 41/58] arm64: dts: renesas: condor: add PCIe support

[Simon Horman]

From: Sergei Shtylyov 

Enable PCIe PHY and PCIEC and specify the PCIe bus clock for the Condor
board.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov 
Signed-off-by: Sergei Shtylyov 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts 
b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
index 59db4c152fb8..fe2e2c051cc9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -223,6 +223,18 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
+_bus_clk {
+   clock-frequency = <1>;
+};
+
+_phy {
+   status = "okay";
+};
+
  {
avb_pins: avb {
groups = "avb_mdio", "avb_rgmii";
-- 
2.11.0

[PATCH 44/58] arm64: dts: renesas: v3hsk: Move lvds0 node

[Simon Horman]

From: Geert Uytterhoeven 

To preserve alphabetical sort order.

Fixes: 4edac426aff11a37 ("arm64: dts: renesas: condor/v3hsk: add DU/LVDS/HDMI 
support")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts 
b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
index 44ab7344f8aa..dd14a41b32cd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -119,18 +119,6 @@
};
 };
 
- {
-   status = "okay";
-
-   ports {
-   port@1 {
-   lvds0_out: endpoint {
-   remote-endpoint = <_in>;
-   };
-   };
-   };
-};
-
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
@@ -177,6 +165,18 @@
};
 };
 
+ {
+   status = "okay";
+
+   ports {
+   port@1 {
+   lvds0_out: endpoint {
+   remote-endpoint = <_in>;
+   };
+   };
+   };
+};
+
  {
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
-- 
2.11.0

[PATCH 47/58] arm64: dts: renesas: r8a77965: Fix clock/reset for usb2_phy1

[Simon Horman]

From: Geert Uytterhoeven 

usb2_phy1 accidentally uses the same clock/reset as usb2_phy0.

Fixes: b5857630a829a8d5 ("arm64: dts: renesas: r8a77965: add usb2_phy nodes")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Yoshihiro Shimoda 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 108f53cfef5c..77fb909cc839 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1530,9 +1530,9 @@
compatible = "renesas,usb2-phy-r8a77965",
 "renesas,rcar-gen3-usb2-phy";
reg = <0 0xee0a0200 0 0x700>;
-   clocks = < CPG_MOD 703>;
+   clocks = < CPG_MOD 702>;
power-domains = < R8A77965_PD_ALWAYS_ON>;
-   resets = < 703>;
+   resets = < 702>;
#phy-cells = <0>;
status = "disabled";
};
-- 
2.11.0

[PATCH 49/58] arm64: dts: renesas: r8a77990: Use CPG/MSSR and SYSC binding definitions

[Simon Horman]

From: Geert Uytterhoeven 

Use the SoC-specific CPG/MSSR include file to allow future use of
R8A77990_CLK_* symbols.
Replace the hardcoded power domain indices by R8A77990_PD_* symbols.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 36 +++
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 2ee0edfb18d4..e2c2d1480a68 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -5,7 +5,7 @@
  * Copyright (C) 2018 Renesas Electronics Corp.
  */
 
-#include 
+#include 
 #include 
 #include 
 
@@ -22,7 +22,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>;
device_type = "cpu";
-   power-domains = < 5>;
+   power-domains = < R8A77990_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
};
@@ -31,14 +31,14 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <1>;
device_type = "cpu";
-   power-domains = < 6>;
+   power-domains = < R8A77990_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
};
 
L2_CA53: cache-controller-0 {
compatible = "cache";
-   power-domains = < 21>;
+   power-domains = < R8A77990_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
@@ -75,7 +75,7 @@
 "renesas,rcar-gen3-wdt";
reg = <0 0xe602 0 0x0c>;
clocks = < CPG_MOD 402>;
-   power-domains = < 32>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 402>;
status = "disabled";
};
@@ -91,7 +91,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = < CPG_MOD 912>;
-   power-domains = < 32>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 912>;
};
 
@@ -106,7 +106,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = < CPG_MOD 911>;
-   power-domains = < 32>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 911>;
};
 
@@ -121,7 +121,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = < CPG_MOD 910>;
-   power-domains = < 32>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 910>;
};
 
@@ -136,7 +136,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = < CPG_MOD 909>;
-   power-domains = < 32>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 909>;
};
 
@@ -151,7 +151,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = < CPG_MOD 908>;
-   power-domains = < 32>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 908>;
};
 
@@ -166,7 +166,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = < CPG_MOD 907>;
-   power-domains = < 32>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 907>;
};
 
@@ -181,7 +181,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = < CPG_MOD 906>;
-   power-domains = < 32>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 906>;
};
 
@@ -329,7 +329,7 @@
  "ch20", "ch21", "ch22", "ch23",
  "ch24";
clocks = < CPG_MOD 812>;
-   power-domains = < 32>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 812>;
phy-mode = "rgmii";

[PATCH 23/58] arm64: dts: renesas: r8a774a1: Add INTC-EX device node

[Simon Horman]

From: Biju Das 

Add support for the Interrupt Controller for External Devices
(INTC-EX) on RZ/G2M.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 81fba7f19d44..15d7785fb177 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,22 @@
#power-domain-cells = <1>;
};
 
+   intc_ex: interrupt-controller@e61c {
+   compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   reg = <0 0xe61c 0 0x200>;
+   interrupts = ;
+   clocks = < CPG_MOD 407>;
+   power-domains = < 32>;
+   resets = < 407>;
+   };
+
hscif0: serial@e654 {
compatible = "renesas,hscif-r8a774a1",
 "renesas,rcar-gen3-hscif",
-- 
2.11.0

[PATCH 51/58] arm64: dts: renesas: r8a7795: Move arm_cc630p node

[Simon Horman]

From: Geert Uytterhoeven 

To preserve by-address-per-group sort order.

Fixes: 0f6d237cafda2e06 ("arm64: dts: renesas: r8a7795: add ccree to device 
tree")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index c417d4a098df..abb361e41ef6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -525,15 +525,6 @@
status = "disabled";
};
 
-   arm_cc630p: crypto@e6601000 {
-   compatible = "arm,cryptocell-630p-ree";
-   interrupts = ;
-   reg = <0x0 0xe6601000 0 0x1000>;
-   clocks = < CPG_MOD 229>;
-   resets = < 229>;
-   power-domains = < R8A7795_PD_ALWAYS_ON>;
-   };
-
i2c3: i2c@e66d {
#address-cells = <1>;
#size-cells = <0>;
@@ -805,6 +796,15 @@
status = "disabled";
};
 
+   arm_cc630p: crypto@e6601000 {
+   compatible = "arm,cryptocell-630p-ree";
+   interrupts = ;
+   reg = <0x0 0xe6601000 0 0x1000>;
+   clocks = < CPG_MOD 229>;
+   resets = < 229>;
+   power-domains = < R8A7795_PD_ALWAYS_ON>;
+   };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a7795",
 "renesas,rcar-dmac";
-- 
2.11.0

[PATCH 58/58] arm64: dts: r8a77965: add FDP1 device nodes

[Simon Horman]

From: Hoan Nguyen An 

The r8a77965 has a single FDP1 instance.

Signed-off-by: Hoan Nguyen An 
Reviewed-by: Laurent Pinchart 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 77fb909cc839..3437d5e34f6a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1667,6 +1667,16 @@
status = "disabled";
};
 
+   fdp1@fe94 {
+   compatible = "renesas,fdp1";
+   reg = <0 0xfe94 0 0x2400>;
+   interrupts = ;
+   clocks = < CPG_MOD 119>;
+   power-domains = < R8A77965_PD_A3VP>;
+   resets = < 119>;
+   renesas,fcp = <>;
+   };
+
fcpf0: fcp@fe95 {
compatible = "renesas,fcpf";
reg = <0 0xfe95 0 0x200>;
-- 
2.11.0

[PATCH 55/58] arm64: dts: renesas: r8a77990: Add SYS-DMAC device nodes

[Simon Horman]

From: Takeshi Kihara 

This patch adds SYS-DMAC{0,1,2} device nodes for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 102 ++
 1 file changed, 102 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 58610b048ed4..5ce268cda03b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -341,6 +341,108 @@
#power-domain-cells = <1>;
};
 
+   dmac0: dma-controller@e670 {
+   compatible = "renesas,dmac-r8a77990",
+"renesas,rcar-dmac";
+   reg = <0 0xe670 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 219>;
+   clock-names = "fck";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 219>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
+   dmac1: dma-controller@e730 {
+   compatible = "renesas,dmac-r8a77990",
+"renesas,rcar-dmac";
+   reg = <0 0xe730 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 218>;
+   clock-names = "fck";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 218>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
+   dmac2: dma-controller@e731 {
+   compatible = "renesas,dmac-r8a77990",
+"renesas,rcar-dmac";
+   reg = <0 0xe731 0 0x1>;
+   interrupts = ;
+   interrupt-names = "error",
+   "ch0", "ch1", "ch2", "ch3",
+   "ch4", "ch5", "ch6", "ch7",
+   "ch8", "ch9", "ch10", "ch11",
+   "ch12", "ch13", "ch14", "ch15";
+   clocks = < CPG_MOD 217>;
+   clock-names = "fck";
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 217>;
+   #dma-cells = <1>;
+   dma-channels = <16>;
+   };
+
ipmmu_ds0: mmu@e674 {
compatible = "renesas,ipmmu-r8a77990";
reg = <0 0xe674 0 0x1000>;
-- 
2.11.0

[PATCH 53/58] arm64: dts: renesas: r8a77990: Add VIN and CSI-2 device nodes

[Simon Horman]

From: Koji Matsuoka 

Add device nodes for VIN4, VIN5 and CSI40 to R-Car E3 R8A77990 device tree.

Signed-off-by: Koji Matsuoka 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Jacopo Mondi 
Reviewed-by: Laurent Pinchart 
Tested-by: Laurent Pinchart 
[simon: sorted nodes by bus address, then IP block]
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 79 +++
 1 file changed, 79 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index e3009c5f5210..c010358ba076 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -481,6 +481,54 @@
status = "disabled";
};
 
+   vin4: video@e6ef4000 {
+   compatible = "renesas,vin-r8a77990";
+   reg = <0 0xe6ef4000 0 0x1000>;
+   interrupts = ;
+   clocks = < CPG_MOD 807>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 807>;
+   renesas,id = <4>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@1 {
+   reg = <1>;
+
+   vin4csi40: endpoint {
+   remote-endpoint= <>;
+   };
+   };
+   };
+   };
+
+   vin5: video@e6ef5000 {
+   compatible = "renesas,vin-r8a77990";
+   reg = <0 0xe6ef5000 0 0x1000>;
+   interrupts = ;
+   clocks = < CPG_MOD 806>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 806>;
+   renesas,id = <5>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@1 {
+   reg = <1>;
+
+   vin5csi40: endpoint {
+   remote-endpoint= <>;
+   };
+   };
+   };
+   };
+
xhci0: usb@ee00 {
compatible = "renesas,xhci-r8a77990",
 "renesas,rcar-gen3-xhci";
@@ -546,6 +594,37 @@
resets = < 408>;
};
 
+   csi40: csi2@feaa {
+   compatible = "renesas,r8a77990-csi2", 
"renesas,rcar-gen3-csi2";
+   reg = <0 0xfeaa 0 0x1>;
+   interrupts = ;
+   clocks = < CPG_MOD 716>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 716>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   reg = <1>;
+
+   csi40vin4: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <>;
+   };
+   csi40vin5: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = <>;
+   };
+   };
+   };
+   };
+
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
-- 
2.11.0

[PATCH 22/58] arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes

[Simon Horman]

From: Fabrizio Castro 

Add the device nodes for all RZ/G2M SCIF and HSCIF serial ports,
incl. clocks, power domains and DMAs.
According to the HW user manual, SCIF[015] and HSCIF[012] are
connected to both SYS-DMAC1 and SYS-DMAC2, while SCIF[34] and
HSCIF[34] are connected to SYS-DMAC0.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Biju Das 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 185 ++
 1 file changed, 185 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 4a4cf352208e..81fba7f19d44 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -144,6 +144,94 @@
#power-domain-cells = <1>;
};
 
+   hscif0: serial@e654 {
+   compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe654 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 520>,
+< CPG_CORE 19>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x31>, < 0x30>,
+  < 0x31>, < 0x30>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 520>;
+   status = "disabled";
+   };
+
+   hscif1: serial@e655 {
+   compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe655 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 519>,
+< CPG_CORE 19>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x33>, < 0x32>,
+  < 0x33>, < 0x32>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 519>;
+   status = "disabled";
+   };
+
+   hscif2: serial@e656 {
+   compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe656 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 518>,
+< CPG_CORE 19>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x35>, < 0x34>,
+  < 0x35>, < 0x34>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 518>;
+   status = "disabled";
+   };
+
+   hscif3: serial@e66a {
+   compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe66a 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 517>,
+< CPG_CORE 19>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x37>, < 0x36>;
+   dma-names = "tx", "rx";
+   power-domains = < 32>;
+   resets = < 517>;
+   status = "disabled";
+   };
+
+   hscif4: serial@e66b {
+   compatible = "renesas,hscif-r8a774a1",
+"renesas,rcar-gen3-hscif",
+"renesas,hscif";
+   reg = <0 0xe66b 0 0x60>;
+   interrupts = ;
+   clocks = < CPG_MOD 516>,
+< CPG_CORE 19>,
+<_clk>;
+   clock-names = "fck", "brg_int", "scif_clk";
+   dmas = < 0x39>, < 0x38>;
+   dma-names = "tx", "rx";
+   power-domains = < 32>;
+   resets = < 516>;
+   status = "disabled";
+   };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a774a1",
 

[PATCH 43/58] arm64: dts: renesas: Fix whitespace around assignments

[Simon Horman]

From: Geert Uytterhoeven 

Signed-off-by: Geert Uytterhoeven 
[simon: updated for a few new cases]
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi|  8 ++---
 arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 16 +-
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 48 ++--
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 48 ++--
 arch/arm64/boot/dts/renesas/r8a77965.dtsi| 36 ++---
 arch/arm64/boot/dts/renesas/r8a77970.dtsi|  8 ++---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi| 16 +-
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi |  2 +-
 8 files changed, 91 insertions(+), 91 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index d2c67f36884d..046fc937da14 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -66,7 +66,7 @@
power-domains = < 0>;
next-level-cache = <_CA57>;
enable-method = "psci";
-   clocks =< CPG_CORE 0>;
+   clocks = < CPG_CORE 0>;
};
 
a57_1: cpu@1 {
@@ -76,7 +76,7 @@
power-domains = < 1>;
next-level-cache = <_CA57>;
enable-method = "psci";
-   clocks =< CPG_CORE 0>;
+   clocks = < CPG_CORE 0>;
};
 
a53_0: cpu@100 {
@@ -1431,7 +1431,7 @@
clocks = < CPG_MOD 703>;
phys = <_phy0>;
phy-names = "usb";
-   companion= <>;
+   companion = <>;
power-domains = < 32>;
resets = < 703>;
status = "disabled";
@@ -1444,7 +1444,7 @@
clocks = < CPG_MOD 702>;
phys = <_phy1>;
phy-names = "usb";
-   companion= <>;
+   companion = <>;
power-domains = < 32>;
resets = < 702>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index d915cff5b1b0..0fb84c219b2f 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -232,7 +232,7 @@
port@1 {
vin0csi21: endpoint@1 {
reg = <1>;
-   remote-endpoint= <>;
+   remote-endpoint = <>;
};
};
};
@@ -243,7 +243,7 @@
port@1 {
vin1csi21: endpoint@1 {
reg = <1>;
-   remote-endpoint= <>;
+   remote-endpoint = <>;
};
};
};
@@ -254,7 +254,7 @@
port@1 {
vin2csi21: endpoint@1 {
reg = <1>;
-   remote-endpoint= <>;
+   remote-endpoint = <>;
};
};
};
@@ -265,7 +265,7 @@
port@1 {
vin3csi21: endpoint@1 {
reg = <1>;
-   remote-endpoint= <>;
+   remote-endpoint = <>;
};
};
};
@@ -276,7 +276,7 @@
port@1 {
vin4csi21: endpoint@1 {
reg = <1>;
-   remote-endpoint= <>;
+   remote-endpoint = <>;
};
};
};
@@ -287,7 +287,7 @@
port@1 {
vin5csi21: endpoint@1 {
reg = <1>;
-   remote-endpoint= <>;
+   remote-endpoint = <>;
};
};
};
@@ -298,7 +298,7 @@
port@1 {
vin6csi21: endpoint@1 {
reg = <1>;
-   remote-endpoint= <>;
+   remote-endpoint = <>;
};
};
};
@@ -309,7 +309,7 @@
port@1 {
vin7csi21: endpoint@1 {
reg = <1>;
-   remote-endpoint= <>;
+   remote-endpoint = <>;
};
};
};
diff --git 

[PATCH 33/58] arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores

[Simon Horman]

From: Biju Das 

This patch adds definitions for L2 cache for the Cortex-A53 CPU
cores (512 KiB in size, organized as 32 KiB x 16 ways), adds
Cortex-A53 CPU cores (setting a total of 6 cores, 2 x Cortex-A57
+ 4 x Cortex-A53), and finally enables the performance monitor
unit for the Cortex-A53 cores on the R8A774A1 SoC.

Based on work done for r8a7796 SoC.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 66 ---
 1 file changed, 61 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index f379de8404cb..dde188004283 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -79,12 +79,59 @@
clocks =< CPG_CORE 0>;
};
 
+   a53_0: cpu@100 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x100>;
+   device_type = "cpu";
+   power-domains = < 5>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   clocks =< CPG_CORE 1>;
+   };
+
+   a53_1: cpu@101 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x101>;
+   device_type = "cpu";
+   power-domains = < 6>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   clocks =< CPG_CORE 1>;
+   };
+
+   a53_2: cpu@102 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x102>;
+   device_type = "cpu";
+   power-domains = < 7>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   clocks =< CPG_CORE 1>;
+   };
+
+   a53_3: cpu@103 {
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x103>;
+   device_type = "cpu";
+   power-domains = < 8>;
+   next-level-cache = <_CA53>;
+   enable-method = "psci";
+   clocks =< CPG_CORE 1>;
+   };
+
L2_CA57: cache-controller-0 {
compatible = "cache";
power-domains = < 12>;
cache-unified;
cache-level = <2>;
};
+
+   L2_CA53: cache-controller-1 {
+   compatible = "cache";
+   power-domains = < 21>;
+   cache-unified;
+   cache-level = <2>;
+   };
};
 
extal_clk: extal {
@@ -108,6 +155,15 @@
clock-frequency = <0>;
};
 
+   pmu_a53 {
+   compatible = "arm,cortex-a53-pmu";
+   interrupts-extended = < GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ < GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-affinity = <_0>, <_1>, <_2>, <_3>;
+   };
+
pmu_a57 {
compatible = "arm,cortex-a57-pmu";
interrupts-extended = < GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
@@ -977,7 +1033,7 @@
  <0x0 0xf104 0 0x2>,
  <0x0 0xf106 0 0x2>;
interrupts = ;
+   (GIC_CPU_MASK_SIMPLE(6) | 
IRQ_TYPE_LEVEL_HIGH)>;
clocks = < CPG_MOD 408>;
clock-names = "clk";
power-domains = < 32>;
@@ -1037,10 +1093,10 @@
 
timer {
compatible = "arm,armv8-timer";
-   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) 
| IRQ_TYPE_LEVEL_LOW)>;
+   interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) 
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) 
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) 
| IRQ_TYPE_LEVEL_LOW)>,
+ < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) 
| IRQ_TYPE_LEVEL_LOW)>;
};
 
/* 

[PATCH 52/58] arm64: dts: renesas: r8a77990: Add all MSIOF nodes

[Simon Horman]

From: Geert Uytterhoeven 

Add the device nodes for all MSIOF SPI controllers, incl. clocks, power
domains, and resets properties.

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 52 +++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 6198768264be..e3009c5f5210 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -429,6 +429,58 @@
status = "disabled";
};
 
+   msiof0: spi@e6e9 {
+   compatible = "renesas,msiof-r8a77990",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6e9 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 211>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 211>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof1: spi@e6ea {
+   compatible = "renesas,msiof-r8a77990",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6ea 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 210>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 210>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof2: spi@e6c0 {
+   compatible = "renesas,msiof-r8a77990",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c0 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 209>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 209>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof3: spi@e6c1 {
+   compatible = "renesas,msiof-r8a77990",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c1 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 208>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 208>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
xhci0: usb@ee00 {
compatible = "renesas,xhci-r8a77990",
 "renesas,rcar-gen3-xhci";
-- 
2.11.0

[PATCH 46/58] arm64: dts: renesas: r8a77965: Fix HS-USB compatible

[Simon Horman]

From: Geert Uytterhoeven 

Should be "renesas,usbhs-r8a77965", not "renesas,usbhs-r8a7796".

Fixes: a06e8af801760a98 ("arm64: dts: renesas: r8a77965: add HS-USB node")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Yoshihiro Shimoda 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 7f477a15fa59..108f53cfef5c 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -589,7 +589,7 @@
};
 
hsusb: usb@e659 {
-   compatible = "renesas,usbhs-r8a7796",
+   compatible = "renesas,usbhs-r8a77965",
 "renesas,rcar-gen3-usbhs";
reg = <0 0xe659 0 0x100>;
interrupts = ;
-- 
2.11.0

[PATCH 25/58] arm64: dts: renesas: r8a774a1: Add RWDT node

[Simon Horman]

From: Biju Das 

Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G2M (r8a774a1) SoC.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b771211a8444..b9a381808417 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -123,6 +123,16 @@
#size-cells = <2>;
ranges;
 
+   rwdt: watchdog@e602 {
+   compatible = "renesas,r8a774a1-wdt",
+"renesas,rcar-gen3-wdt";
+   reg = <0 0xe602 0 0x0c>;
+   clocks = < CPG_MOD 402>;
+   power-domains = < 32>;
+   resets = < 402>;
+   status = "disabled";
+   };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a774a1-cpg-mssr";
reg = <0 0xe615 0 0x0bb0>;
-- 
2.11.0

[PATCH 17/58] arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

[Simon Horman]

From: Dien Pham 

This patch adds OPPs table for CA57{0,1} cpu devices

Signed-off-by: Dien Pham 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
Tested-by: Simon Horman 
[simon: do not give nodes unit names as they have no bus addresses]
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77965.dtsi | 44 +++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index e7128fb65e33..5ce978502ee9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -60,6 +60,46 @@
clock-frequency = <0>;
};
 
+   cluster0_opp: opp_table0 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp-5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp-10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   };
+   opp-15 {
+   opp-hz = /bits/ 64 <15>;
+   opp-microvolt = <83>;
+   clock-latency-ns = <30>;
+   opp-suspend;
+   };
+   opp-16 {
+   opp-hz = /bits/ 64 <16>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp-17 {
+   opp-hz = /bits/ 64 <17>;
+   opp-microvolt = <90>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   opp-18 {
+   opp-hz = /bits/ 64 <18>;
+   opp-microvolt = <96>;
+   clock-latency-ns = <30>;
+   turbo-mode;
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -71,6 +111,8 @@
power-domains = < R8A77965_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
a57_1: cpu@1 {
@@ -80,6 +122,8 @@
power-domains = < R8A77965_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   clocks =< CPG_CORE R8A77965_CLK_Z>;
+   operating-points-v2 = <_opp>;
};
 
L2_CA57: cache-controller-0 {
-- 
2.11.0

[PATCH 54/58] arm64: dts: renesas: r8a77990: Add I2C device nodes

[Simon Horman]

From: Takeshi Kihara 

Add device nodes for I2C ch[0-7] to R-Car E3 R8A77990 device tree.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Jacopo Mondi 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Geert Uytterhoeven 
Reviewed-by: Laurent Pinchart 
Tested-by: Laurent Pinchart 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 123 ++
 1 file changed, 123 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index c010358ba076..58610b048ed4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -14,6 +14,17 @@
#address-cells = <2>;
#size-cells = <2>;
 
+   aliases {
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   i2c3 = 
+   i2c4 = 
+   i2c5 = 
+   i2c6 = 
+   i2c7 = 
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -192,6 +203,118 @@
resets = < 906>;
};
 
+   i2c0: i2c@e650 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77990",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe650 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 931>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 931>;
+   i2c-scl-internal-delay-ns = <110>;
+   status = "disabled";
+   };
+
+   i2c1: i2c@e6508000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77990",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe6508000 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 930>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 930>;
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c2: i2c@e651 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77990",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe651 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 929>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 929>;
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c3: i2c@e66d {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77990",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe66d 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 928>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 928>;
+   i2c-scl-internal-delay-ns = <110>;
+   status = "disabled";
+   };
+
+   i2c4: i2c@e66d8000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77990",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe66d8000 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 927>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 927>;
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c5: i2c@e66e {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "renesas,i2c-r8a77990",
+"renesas,rcar-gen3-i2c";
+   reg = <0 0xe66e 0 0x40>;
+   interrupts = ;
+   clocks = < CPG_MOD 919>;
+   power-domains = < R8A77990_PD_ALWAYS_ON>;
+   resets = < 919>;
+   i2c-scl-internal-delay-ns = <6>;
+   status = "disabled";
+   };
+
+   i2c6: i2c@e66e8000 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   

[GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.20

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM64 based SoC DT updates for v4.20.

I am sending out this pull-request at this time as there are a number
of patches queued up in my arm (32) DT branch and I hope that this
will ease the burden later on in the development cycle. I expect to
send a follow-up pull-request for this branch at the usual pre-rc6 timing.

Highlights of this pull request:
* New SoC: RZ/G2M (r8a774a1)
* New Board: R-Car M3-N (r8a77965) based ULCB
* And, as usual, increased hardware coverage a variety of SoCs and their boards


The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3:

  Linux 4.19-rc1 (2018-08-26 14:11:59 -0700)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
tags/renesas-arm64-dt-for-v4.20

for you to fetch changes up to 450d6079e8d3c40c7ce67ac8bb4a2da9baf56613:

  arm64: dts: r8a77965: add FDP1 device nodes (2018-09-13 09:48:13 +0200)


Renesas ARM64 Based SoC DT Updates for v4.20

* Correct whitespace around assignments

* R-Car Gen-3 SoCs:
  - Enable SDR104 for SD devices
  - Include R-Car product name in DTSI files to ease maintenance
* R-Car Gen-3 SoC based boards: Convert to new LVDS DT bindings
* R-Car Gen 3 Salvator-X and Salvator-XS boards:
  - Override secondary addresses of ADV748x to avoid address conflicts
* R-Car Gen 3 based Salvator-XS board: Enable SATA

* R-Car M3-N (r8a77965) SoC:
  - Add FDP1 device nodes
  - Move arm_cc630p and timer nodes to restore sort-order of file
  - Correct clock/reset for usb2_phy1
  - Correct HS-USB compat string
  - Add OPPs table for cpu devices enabling CPUFreq support
  - Add CAN device placeholder nodes to facilitate adding
initial device tree for KF daughter board
  - Attach SYS-DMAC to the IPMMU
* R-Car M3-N (r8a77965) based ULCB board:
  - Initial device tree for board and KF daughter board

* R-Car E3 (r8a77990) SoC:
  - Add SYS-DMAC, I2C VIN, CSI-2, MSIOF device nodes
  - Add BRG support to SCIF2 which allows an increase in serial clock accuracy
  - Use CPG/MSSR and SYSC binding definitions
* R-Car E3 (r8a77990) based Ebisu board: Enable PWM

* R-Car D3 (r8a77995) SoC: Attach the SYS-DMAC to the IPMMU
* R-Car D3 (r8a77995) based Draak board: Sort device nodes

* R-Car V3H (r8a77980) based V3HSK board:
  - Move lvds0 node to restore sort-order of file
* R-Car V3H (r8a77980) SoC:
  - Add RWDT, CSI2 and VIN, Cortex-A53 PMU nodes
  - Move IPMMU and CAN clock nodes to restore sort-order of file

* R-Car V3M (r8a77970) SoC:
  - Add MMC nodes
  - Move CAN clock node to restore sort-order of file
* R-Car V3M (r8a77970) based V3MSK board: Add eMMC support
* R-Car V3H (r8a77980) based Condor board: Add PCIe, DU, LVDS and HDMI support

* RZ/G2M (r8a774a1) SoC:
  - Initial device tree
  - Add SYS-DMAC, SCIF, HSCIF, INTC-EX, EtherAVB, RWDT, pinctl, GPIO,
SDHI, I2C, IIC-DVFS, thermal, IPMMU, MSIOF, Cortex-A53 CPU core,
PWM, Audio, FCPF, FCPV, USB2.0, USB-DMAC, HSUSB and USB3.0 device nodes


Biju Das (12):
  arm64: dts: renesas: Initial r8a774a1 SoC device tree
  arm64: dts: renesas: r8a774a1: Add SYS-DMAC controller nodes
  arm64: dts: renesas: r8a774a1: Add INTC-EX device node
  arm64: dts: renesas: r8a774a1: Add RWDT node
  arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS support
  arm64: dts: renesas: r8a774a1: Add RZ/G2M thermal support
  arm64: dts: renesas: r8a774a1: Add all MSIOF nodes
  arm64: dts: renesas: r8a774a1: Add Cortex-A53 CPU cores
  arm64: dts: renesas: r8a774a1: Add audio support
  arm64: dts: renesas: r8a774a1: Add USB2.0 phy and host(EHCI/OHCI) device 
nodes
  arm64: dts: renesas: r8a774a1: Add USB-DMAC and HSUSB device nodes
  arm64: dts: renesas: r8a774a1: Add USB3.0 device nodes

Dien Pham (1):
  arm64: dts: renesas: r8a77965: Add OPPs table for cpu devices

Eugeniu Rosca (3):
  arm64: dts: renesas: r8a77965: Add CAN{0,1} placeholder nodes
  arm64: dts: renesas: r8a77965: m3nulcb: Initial device tree
  arm64: dts: renesas: r8a77965: m3nulcb-kf: Initial device tree

Fabrizio Castro (8):
  arm64: dts: renesas: r8a774a1: Add SCIF and HSCIF nodes
  arm64: dts: renesas: r8a774a1: Add Ethernet AVB node
  arm64: dts: renesas: r8a774a1: Add pinctrl device node
  arm64: dts: renesas: r8a774a1: Add GPIO device nodes
  arm64: dts: renesas: r8a774a1: Add SDHI nodes
  arm64: dts: renesas: r8a774a1: Add IPMMU device nodes
  arm64: dts: renesas: r8a774a1: Add PWM device nodes
  arm64: dts: renesas: r8a774a1: Add FCPF and FCPV instances

Geert Uytterhoeven (10):
  arm64: dts: renesas: Fix whitespace around assignments
  arm64: dts: renesas: v3hsk: Move lvds0 node
  arm64: dts: renesas: r8a77965: Move timer node
  arm64: dts: renesas: r8a77965: Fix HS-USB compatible
  

[PATCH 08/58] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node

[Simon Horman]

From: Sergei Shtylyov 

The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
device  trees,  according to  the alphanumeric node sorting rule...

Signed-off-by: Sergei Shtylyov 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a77970.dtsi | 14 +++---
 arch/arm64/boot/dts/renesas/r8a77980.dtsi | 14 +++---
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 18d1aafe2e30..6c0832f23811 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -24,6 +24,13 @@
i2c4 = 
};
 
+   /* External CAN clock - to be overridden by boards that provide it */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -82,13 +89,6 @@
method = "smc";
};
 
-   /* External CAN clock - to be overridden by boards that provide it */
-   can_clk: can {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index fbfe65476443..4bc99d6763ce 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -25,6 +25,13 @@
i2c5 = 
};
 
+   /* External CAN clock - to be overridden by boards that provide it */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -77,13 +84,6 @@
};
};
 
-   /* External CAN clock - to be overridden by boards that provide it */
-   can_clk: can {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <0>;
-   };
-
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
-- 
2.11.0

[PATCH 39/58] arm64: dts: renesas: r8a774a1: Add USB3.0 device nodes

[Simon Horman]

From: Biju Das 

Add usb3.0 phy, host and function device nodes on RZ/G2M SoC dtsi.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Reviewed-by: Simon Horman 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index b42117486b77..d2c67f36884d 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -641,6 +641,19 @@
dma-channels = <2>;
};
 
+   usb3_phy0: usb-phy@e65ee000 {
+   compatible = "renesas,r8a774a1-usb3-phy",
+"renesas,rcar-gen3-usb3-phy";
+   reg = <0 0xe65ee000 0 0x90>;
+   clocks = < CPG_MOD 328>, <_clk>,
+<_extal_clk>;
+   clock-names = "usb3-if", "usb3s_clk", "usb_extal";
+   power-domains = < 32>;
+   resets = < 328>;
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+
dmac0: dma-controller@e670 {
compatible = "renesas,dmac-r8a774a1",
 "renesas,rcar-dmac";
@@ -1365,6 +1378,28 @@
dma-channels = <16>;
};
 
+   xhci0: usb@ee00 {
+   compatible = "renesas,xhci-r8a774a1",
+"renesas,rcar-gen3-xhci";
+   reg = <0 0xee00 0 0xc00>;
+   interrupts = ;
+   clocks = < CPG_MOD 328>;
+   power-domains = < 32>;
+   resets = < 328>;
+   status = "disabled";
+   };
+
+   usb3_peri0: usb@ee02 {
+   compatible = "renesas,r8a774a1-usb3-peri",
+"renesas,rcar-gen3-usb3-peri";
+   reg = <0 0xee02 0 0x400>;
+   interrupts = ;
+   clocks = < CPG_MOD 328>;
+   power-domains = < 32>;
+   resets = < 328>;
+   status = "disabled";
+   };
+
ohci0: usb@ee08 {
compatible = "generic-ohci";
reg = <0 0xee08 0 0x100>;
-- 
2.11.0

[PATCH 32/58] arm64: dts: renesas: r8a774a1: Add all MSIOF nodes

[Simon Horman]

From: Biju Das 

Add the device nodes for all MSIOF SPI controllers on RZ/G2M SoC.

Based on several similar patches of the R8A7796 device tree
by Geert Uytterhoeven 
and Simon Horman .

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 62 +++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 8589122e3c94..f379de8404cb 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -857,6 +857,68 @@
status = "disabled";
};
 
+   msiof0: spi@e6e9 {
+   compatible = "renesas,msiof-r8a774a1",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6e9 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 211>;
+   dmas = < 0x41>, < 0x40>,
+  < 0x41>, < 0x40>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 211>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof1: spi@e6ea {
+   compatible = "renesas,msiof-r8a774a1",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6ea 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 210>;
+   dmas = < 0x43>, < 0x42>,
+  < 0x43>, < 0x42>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < 32>;
+   resets = < 210>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof2: spi@e6c0 {
+   compatible = "renesas,msiof-r8a774a1",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c0 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 209>;
+   dmas = < 0x45>, < 0x44>;
+   dma-names = "tx", "rx";
+   power-domains = < 32>;
+   resets = < 209>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof3: spi@e6c1 {
+   compatible = "renesas,msiof-r8a774a1",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c1 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 208>;
+   dmas = < 0x47>, < 0x46>;
+   dma-names = "tx", "rx";
+   power-domains = < 32>;
+   resets = < 208>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
sdhi0: sd@ee10 {
compatible = "renesas,sdhi-r8a774a1",
 "renesas,rcar-gen3-sdhi";
-- 
2.11.0

[PATCH 34/58] arm64: dts: renesas: r8a774a1: Add PWM device nodes

[Simon Horman]

From: Fabrizio Castro 

This patch adds PWM[0123456] device nodes to the RZ/G2M (a.k.a R8A774A1)
device tree.

Signed-off-by: Fabrizio Castro 
Reviewed-by: Biju Das 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 70 +++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index dde188004283..c9ac545f08f3 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -816,6 +816,76 @@
status = "disabled";
};
 
+   pwm0: pwm@e6e3 {
+   compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+   reg = <0 0xe6e3 0 0x8>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   resets = < 523>;
+   power-domains = < 32>;
+   status = "disabled";
+   };
+
+   pwm1: pwm@e6e31000 {
+   compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+   reg = <0 0xe6e31000 0 0x8>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   resets = < 523>;
+   power-domains = < 32>;
+   status = "disabled";
+   };
+
+   pwm2: pwm@e6e32000 {
+   compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+   reg = <0 0xe6e32000 0 0x8>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   resets = < 523>;
+   power-domains = < 32>;
+   status = "disabled";
+   };
+
+   pwm3: pwm@e6e33000 {
+   compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+   reg = <0 0xe6e33000 0 0x8>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   resets = < 523>;
+   power-domains = < 32>;
+   status = "disabled";
+   };
+
+   pwm4: pwm@e6e34000 {
+   compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+   reg = <0 0xe6e34000 0 0x8>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   resets = < 523>;
+   power-domains = < 32>;
+   status = "disabled";
+   };
+
+   pwm5: pwm@e6e35000 {
+   compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+   reg = <0 0xe6e35000 0 0x8>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   resets = < 523>;
+   power-domains = < 32>;
+   status = "disabled";
+   };
+
+   pwm6: pwm@e6e36000 {
+   compatible = "renesas,pwm-r8a774a1", "renesas,pwm-rcar";
+   reg = <0 0xe6e36000 0 0x8>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   resets = < 523>;
+   power-domains = < 32>;
+   status = "disabled";
+   };
+
scif0: serial@e6e6 {
compatible = "renesas,scif-r8a774a1",
 "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.11.0

[PATCH 04/58] arm64: dts: renesas: Convert to new LVDS DT bindings

[Simon Horman]

From: Laurent Pinchart 

The internal LVDS encoder now has DT bindings separate from the DU. Port
the r8a7795 and r8a7796 device trees over to the new model.

Signed-off-by: Laurent Pinchart 
Signed-off-by: Simon Horman 
---
 .../boot/dts/renesas/r8a7795-es1-salvator-x.dts|  3 +-
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts |  3 +-
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts |  3 +-
 .../arm64/boot/dts/renesas/r8a7795-salvator-xs.dts |  3 +-
 arch/arm64/boot/dts/renesas/r8a7795.dtsi   | 36 ++
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts |  3 +-
 arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts |  3 +-
 arch/arm64/boot/dts/renesas/r8a7796.dtsi   | 36 ++
 8 files changed, 66 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
index 6b5fa91f1d5d..0895503b69d0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
@@ -40,12 +40,11 @@
 < CPG_MOD 723>,
 < CPG_MOD 722>,
 < CPG_MOD 721>,
-< CPG_MOD 727>,
 < 1>,
 <_clk>,
 <_clk>,
 < 2>;
-   clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+   clock-names = "du.0", "du.1", "du.2", "du.3",
  "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
 };
 
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index df50bf46406e..54515eaf0310 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -41,11 +41,10 @@
 < CPG_MOD 723>,
 < CPG_MOD 722>,
 < CPG_MOD 721>,
-< CPG_MOD 727>,
 < 1>,
 < 3>,
 < 4>,
 < 2>;
-   clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+   clock-names = "du.0", "du.1", "du.2", "du.3",
  "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
 };
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index 446822f5751c..1620e8d8dacc 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -40,12 +40,11 @@
 < CPG_MOD 723>,
 < CPG_MOD 722>,
 < CPG_MOD 721>,
-< CPG_MOD 727>,
 < 1>,
 <_clk>,
 <_clk>,
 < 2>;
-   clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+   clock-names = "du.0", "du.1", "du.2", "du.3",
  "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
 };
 
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index 8ded64d0a4d5..8c142affee49 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -40,12 +40,11 @@
 < CPG_MOD 723>,
 < CPG_MOD 722>,
 < CPG_MOD 721>,
-< CPG_MOD 727>,
 < 1>,
 <_clk>,
 <_clk>,
 < 2>;
-   clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
+   clock-names = "du.0", "du.1", "du.2", "du.3",
  "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
 };
 
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index aa0d4c8f6b04..efc24770c0fd 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -2782,9 +2782,7 @@
 
du: display@feb0 {
compatible = "renesas,du-r8a7795";
-   reg = <0 0xfeb0 0 0x8>,
- <0 0xfeb9 0 0x14>;
-   reg-names = "du", "lvds.0";
+   reg = <0 0xfeb0 0 0x8>;
interrupts = ,
 ,
 ,
@@ -2792,9 +2790,8 @@
clocks = < CPG_MOD 724>,
 < CPG_MOD 723>,
 < CPG_MOD 722>,
-< CPG_MOD 721>,
-< CPG_MOD 727>;
-   clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+< CPG_MOD 721>;
+   clock-names = "du.0", "du.1", "du.2", "du.3";
vsps = < 0  0  0  1>;
status = "disabled";
 
@@ -2822,6 +2819,33 @@
port@3 {

[PATCH 02/58] arm64: dts: renesas: Include R-Car product name in DTSI files

[Simon Horman]

From: Magnus Damm 

Browsing the DTS for all the R-Car SoCs with similar part numbers
makes my head hurt, so to improve the user friendliness of the
DTS code base include R-Car product name in each DTSI file.

Product names are derived from
Documentation/devicetree/bindings/arm/shmobile.txt

Signed-off-by: Magnus Damm 
Signed-off-by: Simon Horman 
---
 arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 +-
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +-
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +-
 arch/arm64/boot/dts/renesas/r8a77965.dtsi| 2 +-
 arch/arm64/boot/dts/renesas/r8a77970.dtsi| 2 +-
 arch/arm64/boot/dts/renesas/r8a77980.dtsi| 2 +-
 arch/arm64/boot/dts/renesas/r8a77990.dtsi| 2 +-
 arch/arm64/boot/dts/renesas/r8a77995.dtsi| 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 7b2fbaec9aef..d915cff5b1b0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7795 ES1.x SoC
+ * Device Tree Source for the R-Car H3 (R8A77950) ES1.x SoC
  *
  * Copyright (C) 2015 Renesas Electronics Corp.
  */
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index fb9d08ad7659..aa0d4c8f6b04 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7795 SoC
+ * Device Tree Source for the R-Car H3 (R8A77950) SoC
  *
  * Copyright (C) 2015 Renesas Electronics Corp.
  */
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index cbd35c00b4af..b93596c9c6b1 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a7796 SoC
+ * Device Tree Source for the R-Car M3-W (R8A77960) SoC
  *
  * Copyright (C) 2016-2017 Renesas Electronics Corp.
  */
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 0cd44461a0bd..9c4f40589cbd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a77965 SoC
+ * Device Tree Source for the R-Car M3-N (R8A77965) SoC
  *
  * Copyright (C) 2018 Jacopo Mondi 
  *
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 954168858fed..18d1aafe2e30 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a77970 SoC
+ * Device Tree Source for the R-Car V3M (R8A77970) SoC
  *
  * Copyright (C) 2016-2017 Renesas Electronics Corp.
  * Copyright (C) 2017 Cogent Embedded, Inc.
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4a1097e32551..d3532fd4c94a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a77980 SoC
+ * Device Tree Source for the R-Car V3H (R8A77980) SoC
  *
  * Copyright (C) 2018 Renesas Electronics Corp.
  * Copyright (C) 2018 Cogent Embedded, Inc.
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index ae89260baad9..2c8f1194e6b5 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Device Tree Source for the r8a77990 SoC
+ * Device Tree Source for the R-Car E3 (R8A77990) SoC
  *
  * Copyright (C) 2018 Renesas Electronics Corp.
  */
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi 
b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index fe77bc43c447..c94513ce5b9b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Device Tree Source for the r8a77995 SoC
+ * Device Tree Source for the R-Car D3 (R8A77995) SoC
  *
  * Copyright (C) 2016 Renesas Electronics Corp.
  * Copyright (C) 2017 Glider bvba
-- 
2.11.0

[PATCH 05/13] ARM: dts: rcar-gen2: Convert to new DU DT bindings

[Simon Horman]

From: Laurent Pinchart 

The DU DT bindings have been updated to drop the reg-names property.
Update the r8a7792 and r8a7794 device trees accordingly.

Signed-off-by: Laurent Pinchart 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7792.dtsi | 1 -
 arch/arm/boot/dts/r8a7794.dtsi | 1 -
 2 files changed, 2 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 63a978ec81cc..52d16a260db0 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -829,7 +829,6 @@
du: display@feb0 {
compatible = "renesas,du-r8a7792";
reg = <0 0xfeb0 0 0x4>;
-   reg-names = "du";
interrupts = ,
 ;
clocks = < CPG_MOD 724>,
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index ea2ca4bdaf1c..886135a273cb 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -1349,7 +1349,6 @@
du: display@feb0 {
compatible = "renesas,du-r8a7794";
reg = <0 0xfeb0 0 0x4>;
-   reg-names = "du";
interrupts = ,
 ;
clocks = < CPG_MOD 724>, < CPG_MOD 723>;
-- 
2.11.0

[PATCH 01/13] ARM: dts: rcar: Correct SATA device sizes to 2 MiB

[Simon Horman]

From: Geert Uytterhoeven 

Update the SATA device nodes on R-Car H1, H2, and M2-W to use a 2 MiB
I/O space, as specified in Rev.1.0 of the R-Car H1 and R-Car Gen2
hardware user manuals.

See also commit e9f0089b2d8a3d45 ("arm64: dts: r8a7795: Correct SATA
device size to 2MiB").

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7779.dtsi | 2 +-
 arch/arm/boot/dts/r8a7790.dtsi | 4 ++--
 arch/arm/boot/dts/r8a7791.dtsi | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 6b997bc016ee..03919714645a 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -344,7 +344,7 @@
 
sata: sata@fc60 {
compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
-   reg = <0xfc60 0x2000>;
+   reg = <0xfc60 0x20>;
interrupts = ;
clocks = <_clks R8A7779_CLK_SATA>;
power-domains = < R8A7779_PD_ALWAYS_ON>;
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 0925bdca438f..52a757f47bf0 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -1559,7 +1559,7 @@
sata0: sata@ee30 {
compatible = "renesas,sata-r8a7790",
 "renesas,rcar-gen2-sata";
-   reg = <0 0xee30 0 0x2000>;
+   reg = <0 0xee30 0 0x20>;
interrupts = ;
clocks = < CPG_MOD 815>;
power-domains = < R8A7790_PD_ALWAYS_ON>;
@@ -1570,7 +1570,7 @@
sata1: sata@ee50 {
compatible = "renesas,sata-r8a7790",
 "renesas,rcar-gen2-sata";
-   reg = <0 0xee50 0 0x2000>;
+   reg = <0 0xee50 0 0x20>;
interrupts = ;
clocks = < CPG_MOD 814>;
power-domains = < R8A7790_PD_ALWAYS_ON>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 991ac6feedd5..25b6a99dd87a 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -1543,7 +1543,7 @@
sata0: sata@ee30 {
compatible = "renesas,sata-r8a7791",
 "renesas,rcar-gen2-sata";
-   reg = <0 0xee30 0 0x2000>;
+   reg = <0 0xee30 0 0x20>;
interrupts = ;
clocks = < CPG_MOD 815>;
power-domains = < R8A7791_PD_ALWAYS_ON>;
@@ -1554,7 +1554,7 @@
sata1: sata@ee50 {
compatible = "renesas,sata-r8a7791",
 "renesas,rcar-gen2-sata";
-   reg = <0 0xee50 0 0x2000>;
+   reg = <0 0xee50 0 0x20>;
interrupts = ;
clocks = < CPG_MOD 814>;
power-domains = < R8A7791_PD_ALWAYS_ON>;
-- 
2.11.0

[PATCH 02/13] ARM: dts: r8a77470: Use r8a77470-sysc binding definitions

[Simon Horman]

From: Biju Das 

Replace the hardcoded power domain indices by R8A77470_PD_* symbols.

Signed-off-by: Biju Das 
Reviewed-by: Chris Paterson 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a77470.dtsi | 27 ++-
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 87d32d3e23de..9b218c3ffdbd 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 / {
compatible = "renesas,r8a77470";
#address-cells = <2>;
@@ -23,7 +24,7 @@
reg = <0>;
clock-frequency = <10>;
clocks = < CPG_CORE R8A77470_CLK_Z2>;
-   power-domains = < 5>;
+   power-domains = < R8A77470_PD_CA7_CPU0>;
next-level-cache = <_CA7>;
};
 
@@ -32,7 +33,7 @@
compatible = "cache";
cache-unified;
cache-level = <2>;
-   power-domains = < 21>;
+   power-domains = < R8A77470_PD_CA7_SCU>;
};
};
 
@@ -97,7 +98,7 @@
 ,
 ;
clocks = < CPG_MOD 407>;
-   power-domains = < 32>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 407>;
};
 
@@ -151,7 +152,7 @@
  "ch12", "ch13", "ch14";
clocks = < CPG_MOD 219>;
clock-names = "fck";
-   power-domains = < 32>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 219>;
#dma-cells = <1>;
dma-channels = <15>;
@@ -184,7 +185,7 @@
  "ch12", "ch13", "ch14";
clocks = < CPG_MOD 218>;
clock-names = "fck";
-   power-domains = < 32>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 218>;
#dma-cells = <1>;
dma-channels = <15>;
@@ -196,7 +197,7 @@
reg = <0 0xe680 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = ;
clocks = < CPG_MOD 812>;
-   power-domains = < 32>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 812>;
#address-cells = <1>;
#size-cells = <0>;
@@ -214,7 +215,7 @@
dmas = < 0x29>, < 0x2a>,
   < 0x29>, < 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
-   power-domains = < 32>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 721>;
status = "disabled";
};
@@ -230,7 +231,7 @@
dmas = < 0x2d>, < 0x2e>,
   < 0x2d>, < 0x2e>;
dma-names = "tx", "rx", "tx", "rx";
-   power-domains = < 32>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 720>;
status = "disabled";
};
@@ -246,7 +247,7 @@
dmas = < 0x2b>, < 0x2c>,
   < 0x2b>, < 0x2c>;
dma-names = "tx", "rx", "tx", "rx";
-   power-domains = < 32>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 719>;
status = "disabled";
};
@@ -262,7 +263,7 @@
dmas = < 0x2f>, < 0x30>,
   < 0x2f>, < 0x30>;
dma-names = "tx", "rx", "tx", "rx";
-   power-domains = < 32>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 718>;
status = "disabled";
};
@@ -278,7 +279,7 @@
dmas = < 0xfb>, < 0xfc>,
   < 0xfb>, < 0xfc>;
dma-names = "tx", "rx", "tx", "rx";
-   power-domains = < 32>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
resets = < 715>;
status = "disabled";
};
@@ -294,7 +295,7 @@
dmas = < 0xfd>, < 0xfe>,
   < 0xfd>, < 0xfe>;
  

[GIT PULL] Renesas ARM Based SoC DT Updates for v4.20

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM based SoC DT updates for v4.20.

I am sending out this pull-request at this time as there are a number
of patches queued up in my arm (32) DT branch and I hope that this
will ease the burden later on in the development cycle. I expect to
send a follow-up pull-request for this branch at the usual pre-rc6 timing.


The following changes since commit 5b394b2ddf0347bef56e50c69a58773c94343ff3:

  Linux 4.19-rc1 (2018-08-26 14:11:59 -0700)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
tags/renesas-arm-dt-for-v4.20

for you to fetch changes up to 1926bd6bf20fe306797fbf366902674d2d6c20cc:

  ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions (2018-09-06 
11:31:35 +0200)


Renesas ARM Based SoC DT Updates for v4.20

* R-Car Gen1 SoCs: Include product name in DTSI files for ease of maintenance
* R-Car Gen2 SoCs:
  - Convert to new DU DT bindings
  - Correct SATA device sizes to 2 MiB
* R-Car H2 (r8a7790) based Porter board: Add DA9063 OnKey PMIC node
* R-Car E2 (r8a7794) based Silk board: Add DA9063 PMIC, RTC and OnKey nodes
* R-Car M2-N (r8a7793) based Gose board: Add DA9210 node for CPU DVFS
* RZ/G1C (R8A77470) SoC:
  - Add GPIO nodes
  - Add PFC support
  - Use r8a77470-sysc binding definitions
* RZ/G1C (r8a77470) iW-RainboW-G23S dev platform:
  - Specify EtherAVB PHY IRQ
  - Add pinctl support for scif1
* RZ/N1D (r9a06g032) SoC: Use r9a06g032-sysctrl binding definitions


Biju Das (5):
  ARM: dts: r8a77470: Use r8a77470-sysc binding definitions
  ARM: dts: r8a77470: Add PFC support
  ARM: dts: iwg23s-sbc: Add pinctl support for scif1
  ARM: dts: r8a77470: Add GPIO support
  ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ

Geert Uytterhoeven (2):
  ARM: dts: rcar: Correct SATA device sizes to 2 MiB
  ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitions

Laurent Pinchart (1):
  ARM: dts: rcar-gen2: Convert to new DU DT bindings

Magnus Damm (1):
  ARM: dts: Include R-Car Gen1 product name in DTSI files

Marek Vasut (4):
  ARM: dts: gose: Add DA9210 node for CPU DVFS
  ARM: dts: silk: Add DA9063 PMIC node
  ARM: dts: silk: Add DA9063 RTC and OnKey node
  ARM: dts: stout: Add DA9063 OnKey node

 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts |  12 +++
 arch/arm/boot/dts/r8a77470.dtsi   | 123 ++
 arch/arm/boot/dts/r8a7778.dtsi|   2 +-
 arch/arm/boot/dts/r8a7779.dtsi|   4 +-
 arch/arm/boot/dts/r8a7790-stout.dts   |   4 +
 arch/arm/boot/dts/r8a7790.dtsi|   4 +-
 arch/arm/boot/dts/r8a7791.dtsi|   4 +-
 arch/arm/boot/dts/r8a7792.dtsi|   1 -
 arch/arm/boot/dts/r8a7793-gose.dts|  16 
 arch/arm/boot/dts/r8a7794-silk.dts|  25 ++
 arch/arm/boot/dts/r8a7794.dtsi|   1 -
 arch/arm/boot/dts/r9a06g032.dtsi  |   7 +-
 12 files changed, 178 insertions(+), 25 deletions(-)

[PATCH 03/13] ARM: dts: r8a77470: Add PFC support

[Simon Horman]

From: Biju Das 

Define the generic R8A77470 part of the PFC device node.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a77470.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 9b218c3ffdbd..af65fa031d84 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -61,6 +61,11 @@
#size-cells = <2>;
ranges;
 
+   pfc: pin-controller@e606 {
+   compatible = "renesas,pfc-r8a77470";
+   reg = <0 0xe606 0 0x118>;
+   };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a77470-cpg-mssr";
reg = <0 0xe615 0 0x1000>;
-- 
2.11.0

[PATCH 07/13] ARM: dts: silk: Add DA9063 PMIC node

[Simon Horman]

From: Marek Vasut 

Add DA9063 PMIC node to the I2C bus.

Signed-off-by: Marek Vasut 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7794-silk.dts | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794-silk.dts 
b/arch/arm/boot/dts/r8a7794-silk.dts
index daec965889d3..6ea60e1faf75 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -405,6 +405,23 @@
clock-frequency = <40>;
 };
 
+ {
+   status = "okay";
+   clock-frequency = <10>;
+
+   pmic@58 {
+   compatible = "dlg,da9063";
+   reg = <0x58>;
+   interrupt-parent = <>;
+   interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+   interrupt-controller;
+
+   wdt {
+   compatible = "dlg,da9063-watchdog";
+   };
+   };
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
-- 
2.11.0

[PATCH 04/13] ARM: dts: iwg23s-sbc: Add pinctl support for scif1

[Simon Horman]

From: Biju Das 

Adding pinctrl support for scif1 interface.

Signed-off-by: Biju Das 
Reviewed-by: Chris Paterson 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts 
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index e3585daafdd6..56182eec81fb 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -43,6 +43,16 @@
clock-frequency = <2000>;
 };
 
+ {
+   scif1_pins: scif1 {
+   groups = "scif1_data_b";
+   function = "scif1";
+   };
+};
+
  {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
status = "okay";
 };
-- 
2.11.0

[PATCH 11/13] ARM: dts: stout: Add DA9063 OnKey node

[Simon Horman]

From: Marek Vasut 

Add DA9063 OnKey subnode to DA9063 PMIC node on Stout.

Signed-off-by: Marek Vasut 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7790-stout.dts | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7790-stout.dts 
b/arch/arm/boot/dts/r8a7790-stout.dts
index a13a92c26645..629da4cee1b9 100644
--- a/arch/arm/boot/dts/r8a7790-stout.dts
+++ b/arch/arm/boot/dts/r8a7790-stout.dts
@@ -318,6 +318,10 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
 
+   onkey {
+   compatible = "dlg,da9063-onkey";
+   };
+
rtc {
compatible = "dlg,da9063-rtc";
};
-- 
2.11.0

[PATCH 10/13] ARM: dts: silk: Add DA9063 RTC and OnKey node

[Simon Horman]

From: Marek Vasut 

Add DA9063 RTC and OnKey subnode to DA9063 PMIC node on Silk.

Signed-off-by: Marek Vasut 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7794-silk.dts | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7794-silk.dts 
b/arch/arm/boot/dts/r8a7794-silk.dts
index 6ea60e1faf75..60e91ebfa65d 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -416,6 +416,14 @@
interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
 
+   onkey {
+   compatible = "dlg,da9063-onkey";
+   };
+
+   rtc {
+   compatible = "dlg,da9063-rtc";
+   };
+
wdt {
compatible = "dlg,da9063-watchdog";
};
-- 
2.11.0

[PATCH 08/13] ARM: dts: r8a77470: Add GPIO support

[Simon Horman]

From: Biju Das 

Describe GPIO blocks in the R8A77470 device tree.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a77470.dtsi | 91 +
 1 file changed, 91 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index af65fa031d84..c053a28cd132 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -61,6 +61,97 @@
#size-cells = <2>;
ranges;
 
+   gpio0: gpio@e605 {
+   compatible = "renesas,gpio-r8a77470",
+"renesas,rcar-gen2-gpio";
+   reg = <0 0xe605 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 0 23>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 912>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
+   resets = < 912>;
+   };
+
+   gpio1: gpio@e6051000 {
+   compatible = "renesas,gpio-r8a77470",
+"renesas,rcar-gen2-gpio";
+   reg = <0 0xe6051000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 32 23>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 911>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
+   resets = < 911>;
+   };
+
+   gpio2: gpio@e6052000 {
+   compatible = "renesas,gpio-r8a77470",
+"renesas,rcar-gen2-gpio";
+   reg = <0 0xe6052000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 64 32>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 910>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
+   resets = < 910>;
+   };
+
+   gpio3: gpio@e6053000 {
+   compatible = "renesas,gpio-r8a77470",
+"renesas,rcar-gen2-gpio";
+   reg = <0 0xe6053000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 96 30>;
+   gpio-reserved-ranges = <17 10>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 909>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
+   resets = < 909>;
+   };
+
+   gpio4: gpio@e6054000 {
+   compatible = "renesas,gpio-r8a77470",
+"renesas,rcar-gen2-gpio";
+   reg = <0 0xe6054000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 128 26>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 908>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
+   resets = < 908>;
+   };
+
+   gpio5: gpio@e6055000 {
+   compatible = "renesas,gpio-r8a77470",
+"renesas,rcar-gen2-gpio";
+   reg = <0 0xe6055000 0 0x50>;
+   interrupts = ;
+   #gpio-cells = <2>;
+   gpio-controller;
+   gpio-ranges = < 0 160 32>;
+   #interrupt-cells = <2>;
+   interrupt-controller;
+   clocks = < CPG_MOD 907>;
+   power-domains = < R8A77470_PD_ALWAYS_ON>;
+   resets = < 907>;
+   };
+
pfc: pin-controller@e606 {
compatible = "renesas,pfc-r8a77470";
reg = <0 0xe606 0 0x118>;
-- 
2.11.0

[PATCH 09/13] ARM: dts: iwg23s-sbc: specify EtherAVB PHY IRQ

[Simon Horman]

From: Biju Das 

Specify  EtherAVB PHY IRQ  in the board specific device tree, now that we
have GPIO support.

Signed-off-by: Biju Das 
Reviewed-by: Fabrizio Castro 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts 
b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 56182eec81fb..22da819f186b 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -35,6 +35,8 @@
 
phy3: ethernet-phy@3 {
reg = <3>;
+   interrupt-parent = <>;
+   interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <1>;
};
 };
-- 
2.11.0

[PATCH 06/13] ARM: dts: gose: Add DA9210 node for CPU DVFS

[Simon Horman]

From: Marek Vasut 

Add DA9210 DVFS node to the I2C bus and link it to CPU0 for DVFS.

Signed-off-by: Marek Vasut 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Simon Horman 
---
 arch/arm/boot/dts/r8a7793-gose.dts | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7793-gose.dts 
b/arch/arm/boot/dts/r8a7793-gose.dts
index 6b2f3a4fd13d..f51601af89a2 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -596,6 +596,10 @@
status = "okay";
 };
 
+ {
+   cpu0-supply = <_dvfs>;
+};
+
  {
timeout-sec = <60>;
status = "okay";
@@ -725,6 +729,18 @@
compatible = "dlg,da9063-watchdog";
};
};
+
+   vdd_dvfs: regulator@68 {
+   compatible = "dlg,da9210";
+   reg = <0x68>;
+   interrupt-parent = <>;
+   interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+
+   regulator-min-microvolt = <100>;
+   regulator-max-microvolt = <100>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
 };
 
  {
-- 
2.11.0

Re: [PATCH 1/2] clocksource/drivers/ostm: Delay driver registration

[Geert Uytterhoeven]

Hi Daniel,

On Thu, Sep 13, 2018 at 3:17 PM Daniel Lezcano
 wrote:
> On 11/09/2018 20:42, Chris Brandt wrote:
> > On Tuesday, September 11, 2018 1, Rob Herring wrote:
> >> Well before we get to initcalls, the kernel calls the arch specific
> >> time_init() which (on ARM) calls of_clk_init (for all the reasons
> >> above) and then timer_probe(). When timer_probe returns, it is
> >> expected that you have setup a clocksource and clockevent. If you
> >> haven't, then at some point before we get to initcalls we should hang
> >> because we're not getting any timer interrupts and time is not
> >> advancing.
> >
> > What I get now is:
> >
> > [0.00] timer_probe: no matching timers found
> > ...
> > ...
> >  [0.00] clocksource: jiffies: mask: 0x max_cycles: 
> > 0x, max_idle_ns: 1911260446275 ns
> > ...
> > ...
> >
> >
> > But then later on in boot, I'll get (with my subsys_initcall timer fix)
> >
> > ...
> > ...
> > [0.00] SCSI subsystem initialized
> > [0.00] usbcore: registered new interface driver usbfs
> > [0.00] usbcore: registered new interface driver hub
> > [0.00] usbcore: registered new device driver usb
> > [0.00] clocksource: ostm: mask: 0x max_cycles: 0x, 
> > max_idle_ns: 28958491609 ns
> > [0.000619] sched_clock: 32 bits at 66MHz, resolution 15ns, wraps every 
> > 32537631224ns
> > [0.008599] ostm: used for clocksource
> > [0.018926] ostm: used for clock events
> > [0.19] clocksource: Switched to clocksource ostm
> > [0.821474] NET: Registered protocol family 2
> > [0.840624] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 
> > 4096 bytes)
> > [0.850549] TCP established hash table entries: 1024 (order: 0, 4096 
> > bytes)
> > ...
> > ...
> >
> >
> >
> >> Maybe you
> >> just get lucky and it works as long as no thread blocks (e.g. on a
> >> msleep).
> >
> > You're right. If I put in a msleep() before my timer is up and running, it 
> > hangs.
> >
> > As far as I can tell, nothing before device_initcall seems to call anything 
> > like msleep.
> >
> >> If things changed and you can setup a timer in an initcall,
> >> then why are folks still trying to do things like early platform
> >> drivers. Regular drivers would work and we should be able to
> >> completely remove CLK_OF_DECLARE and TIMER_OF_DECLARE.
> >
> > I wonder if the reason is because you can't assign a priority to your
> > driver when you declare it with xxx_initcall( ). So, your driver ends up
> > in the same table as all the other drivers and you are not guaranteed the
> > order in which they probe. So, the answer was to make a NEW table and
> > register it using TIMER_OF_DECLARE and CLOCK_OF_DECLARE.
> >
> > I wonder they just didn't make a clock_initcall() and timer_initcall()
> > instead.
>
> What happens if you place the clk_init() before board_time_init() ? in
> arch/sh/kernel/time.c

Nothing, as Chris is using an ARM platform ;-)

The clock driver is drivers/clk/renesas/renesas-cpg-mssr.c, which is a
platform_driver registered from subsys_initcall().

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] clocksource: sh_cmt: fix clocksource width for 32-bit machines

[Daniel Lezcano]

On 10/09/2018 22:22, Sergei Shtylyov wrote:
> The driver seems to abuse *unsigned long* not only for the (32-bit)
> register values but also for the 'sh_cmt_channel::total_cycles' which
> needs to always be 64-bit -- as a result, the clocksource's mask is
> needlessly clamped down to 32-bits on the 32-bit machines...
> 
> Reported-by: Geert Uytterhoeven 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
> This patch is against the 'tip.git' repo's 'timers/core' branch plus the fixup
> for the 64-bit machines reposted last Saturday...

Why not against timers/urgent ?



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[PATCH v3] mmc: renesas_sdhi_internal_dmac: set scatter/gather max segment size

[Wolfram Sang]

From: Niklas Söderlund 

Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a
device_dma_parameters structure and filling in the max segment size. The
size used is the result of a discussion with Renesas hardware engineers
and unfortunately not found in the datasheet.

  renesas_sdhi_internal_dmac ee14.sd: DMA-API: mapping sg segment
  longer than device claims to support [len=126976] [max=65536]

Reported-by: Geert Uytterhoeven 
Signed-off-by: Niklas Söderlund 
[wsa: simplified some logic after validating intended dma_parms life cycle
  and added comment]
Signed-off-by: Wolfram Sang 
---

After discussing with DMA maintainers [1], this really seems the intended way
of using dma_parms. Took Niklas patch V2 and simplified the logic a bit more
given the information from above (but I'll still tackle the dangling pointer
issue in the DMA core seperately).

[1] https://www.spinics.net/lists/iommu/msg29861.html

 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c 
b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index ca0b43973769..e0823acaa3c2 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -309,12 +309,20 @@ static const struct soc_device_attribute 
gen3_soc_whitelist[] = {
 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
 {
const struct soc_device_attribute *soc = 
soc_device_match(gen3_soc_whitelist);
+   struct device *dev = >dev;
 
if (!soc)
return -ENODEV;
 
global_flags |= (unsigned long)soc->data;
 
+   dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
+   if (!dev->dma_parms)
+   return -ENOMEM;
+
+   /* value is max of SD_SECCNT. Confirmed by HW engineers */
+   dma_set_max_seg_size(dev, 0x);
+
return renesas_sdhi_probe(pdev, _sdhi_internal_dmac_dma_ops);
 }
 
-- 
2.11.0

Re: [PATCH 1/2] clocksource/drivers/ostm: Delay driver registration

[Daniel Lezcano]

On 11/09/2018 20:42, Chris Brandt wrote:
> On Tuesday, September 11, 2018 1, Rob Herring wrote:
>> Well before we get to initcalls, the kernel calls the arch specific
>> time_init() which (on ARM) calls of_clk_init (for all the reasons
>> above) and then timer_probe(). When timer_probe returns, it is
>> expected that you have setup a clocksource and clockevent. If you
>> haven't, then at some point before we get to initcalls we should hang
>> because we're not getting any timer interrupts and time is not
>> advancing.
> 
> What I get now is:
> 
> [0.00] timer_probe: no matching timers found
> ...
> ...
>  [0.00] clocksource: jiffies: mask: 0x max_cycles: 
> 0x, max_idle_ns: 1911260446275 ns
> ...
> ...
> 
> 
> But then later on in boot, I'll get (with my subsys_initcall timer fix)
> 
> ...
> ...
> [0.00] SCSI subsystem initialized
> [0.00] usbcore: registered new interface driver usbfs
> [0.00] usbcore: registered new interface driver hub
> [0.00] usbcore: registered new device driver usb
> [0.00] clocksource: ostm: mask: 0x max_cycles: 0x, 
> max_idle_ns: 28958491609 ns
> [0.000619] sched_clock: 32 bits at 66MHz, resolution 15ns, wraps every 
> 32537631224ns
> [0.008599] ostm: used for clocksource
> [0.018926] ostm: used for clock events
> [0.19] clocksource: Switched to clocksource ostm
> [0.821474] NET: Registered protocol family 2
> [0.840624] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 
> 4096 bytes)
> [0.850549] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
> ...
> ...
> 
> 
> 
>> Maybe you
>> just get lucky and it works as long as no thread blocks (e.g. on a
>> msleep).
> 
> You're right. If I put in a msleep() before my timer is up and running, it 
> hangs.
> 
> As far as I can tell, nothing before device_initcall seems to call anything 
> like msleep.
> 
>> If things changed and you can setup a timer in an initcall,
>> then why are folks still trying to do things like early platform
>> drivers. Regular drivers would work and we should be able to
>> completely remove CLK_OF_DECLARE and TIMER_OF_DECLARE.
> 
> I wonder if the reason is because you can't assign a priority to your 
> driver when you declare it with xxx_initcall( ). So, your driver ends up 
> in the same table as all the other drivers and you are not guaranteed the
> order in which they probe. So, the answer was to make a NEW table and 
> register it using TIMER_OF_DECLARE and CLOCK_OF_DECLARE.
> 
> I wonder they just didn't make a clock_initcall() and timer_initcall() 
> instead.

What happens if you place the clk_init() before board_time_init() ? in
arch/sh/kernel/time.c

void __init time_init(void)
{
if (board_time_init)
board_time_init();

clk_init();

late_time_init = sh_late_time_init;
}



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Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support

[Sergei Shtylyov]

On 09/12/2018 12:39 PM, Simon Horman wrote:

>> Describe TMUs in the R8A779{7|8}0 device trees.
>>
>> Based on the original (and large) patches by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov 
>> Signed-off-by: Sergei Shtylyov 
>>
>> ---
>> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
>> Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
>> the CMT support).
>>
>> The R8A779{7|8}0 TMU DT binding update have been just posted...
>>
>>  arch/arm64/boot/dts/renesas/r8a77970.dtsi |   66 
>> ++
>>  arch/arm64/boot/dts/renesas/r8a77980.dtsi |   66 
>> ++
>>  2 files changed, 132 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> ===
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
>> @@ -316,6 +316,72 @@
>>  resets = < 407>;
>>  };
>>  
>> +tmu0: timer@e61e {
>> +compatible = "renesas,tmu-r8a77970", 
>> "renesas,tmu";
>> +reg = <0 0xe61e 0 0x30>;
>> +interrupts = ,
>> + ,
>> + ;
>> +clocks = < CPG_MOD 125>;
>> +clock-names = "fck";
>> +power-domains = < R8A77970_PD_ALWAYS_ON>;
>> +resets = < 125>;
>> +status = "disabled";
>> +};
>> +
>> +tmu1: timer@e6fc {
>> +compatible = "renesas,tmu-r8a77970", 
>> "renesas,tmu";
>> +reg = <0 0xe6fc 0 0x30>;
>> +interrupts = ,
>> + ,
>> + ;
>> +clocks = < CPG_MOD 124>;
>> +clock-names = "fck";
>> +power-domains = < R8A77970_PD_ALWAYS_ON>;
>> +resets = < 124>;
>> +status = "disabled";
>> +};
>> +
>> +tmu2: timer@e6fd {
>> +compatible = "renesas,tmu-r8a77970", 
>> "renesas,tmu";
>> +reg = <0 0xe6fd 0 0x30>;
>> +interrupts = ,
>> + ,
>> + ;
>
> Should GIC_SPI 306 also be here for TMU 2 channel 3?> 
> And likewise for the r8a77980 (V3H)

There are only 3 channels per TMU according to the beginning of the TMU 
 chapter.

> The documentation seems inconsistent as I see this listed in the
> interrupt controller documentation. But I do not see that channel
> documented in the TMU documentation.

Right!

>> +clocks = < CPG_MOD 123>;
>> +clock-names = "fck";
>> +power-domains = < R8A77970_PD_ALWAYS_ON>;
>> +resets = < 123>;
>> +status = "disabled";
>> +};
>> +
>> +tmu3: timer@e6fe {
>> +compatible = "renesas,tmu-r8a7797", 
>> "renesas,tmu";
>> +reg = <0 0xe6fe 0 0x30>;
>> +interrupts = ,
>> + ,
>> + ;
>> +clocks = < CPG_MOD 122>;
>> +clock-names = "fck";
>> +power-domains = < R8A77970_PD_ALWAYS_ON>;
>> +resets = < 122>;
>> +status = "disabled";
>> +};
>> +
>> +tmu4: timer@ffc0 {
>> +compatible = "renesas,tmu-r8a7797", 
>> "renesas,tmu";
>> +reg = <0 0xffc0 0 0x30>;
>> +interrupts = ,
>> + ,
>> + ,
>> + ;
>
> Should GIC_SPI 369 for TMU 4 channel 3 be present not here for
> the r8a77970 (V3M) but rather below for the r8a77980 (V3H) ?

I don't think it should be pesent in either place, and I thought I had 
 removed
 the 4th IRQ from every node before posting... :-/

> As per my note above, the documentation seems inconsistent 

Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: add TMU support

[Sergei Shtylyov]

On 09/11/2018 09:35 PM, Sergei Shtylyov wrote:

> Describe TMUs in the R8A779{7|8}0 device trees.
>
> Based on the original (and large) patches by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 
>
> ---
> This patch is against the 'renesas-devel-20180906-v4.19-rc2' branch of
> Simon Horman's 'renesas.git' repo plus the R8A779{7|8}0 DT patch adding
> the CMT support).
>
> The R8A779{7|8}0 TMU DT binding update have been just posted...
>
>  arch/arm64/boot/dts/renesas/r8a77970.dtsi |   66 
> ++
>  arch/arm64/boot/dts/renesas/r8a77980.dtsi |   66 
> ++
>  2 files changed, 132 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> ===
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
> @@ -316,6 +316,72 @@
>   resets = < 407>;
>   };
>  
> + tmu0: timer@e61e {
> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> + reg = <0 0xe61e 0 0x30>;
> + interrupts = ,
> +  ,
> +  ;
> + clocks = < CPG_MOD 125>;
> + clock-names = "fck";
> + power-domains = < R8A77970_PD_ALWAYS_ON>;
> + resets = < 125>;
> + status = "disabled";
> + };
> +
> + tmu1: timer@e6fc {
> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> + reg = <0 0xe6fc 0 0x30>;
> + interrupts = ,
> +  ,
> +  ;
> + clocks = < CPG_MOD 124>;
> + clock-names = "fck";
> + power-domains = < R8A77970_PD_ALWAYS_ON>;
> + resets = < 124>;
> + status = "disabled";
> + };
> +
> + tmu2: timer@e6fd {
> + compatible = "renesas,tmu-r8a77970", "renesas,tmu";
> + reg = <0 0xe6fd 0 0x30>;
> + interrupts = ,
> +  ,
> +  ;

 Should GIC_SPI 306 also be here for TMU 2 channel 3?> 
 And likewise for the r8a77980 (V3H)
>>>
>>>There are only 3 channels per TMU according to the beginning of the TMU 
>>> chapter.
>>>
 The documentation seems inconsistent as I see this listed in the
 interrupt controller documentation. But I do not see that channel
 documented in the TMU documentation.
>>>
>>>Right!
>>>
> + clocks = < CPG_MOD 123>;
> + clock-names = "fck";
> + power-domains = < R8A77970_PD_ALWAYS_ON>;
> + resets = < 123>;
> + status = "disabled";
> + };
> +
> + tmu3: timer@e6fe {
> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
> + reg = <0 0xe6fe 0 0x30>;
> + interrupts = ,
> +  ,
> +  ;
> + clocks = < CPG_MOD 122>;
> + clock-names = "fck";
> + power-domains = < R8A77970_PD_ALWAYS_ON>;
> + resets = < 122>;
> + status = "disabled";
> + };
> +
> + tmu4: timer@ffc0 {
> + compatible = "renesas,tmu-r8a7797", "renesas,tmu";
> + reg = <0 0xffc0 0 0x30>;
> + interrupts = ,
> +  ,
> +  ,
> +  ;

 Should GIC_SPI 369 for TMU 4 channel 3 be present not here for
 the r8a77970 (V3M) but rather below for the r8a77980 (V3H) ?
>>>
>>>I don't think it should be pesent in either place, and I thought I had 
>>> removed
>>> the 4th IRQ from every node before posting... :-/
>>>
 As per my note above, the documentation seems inconsistent here.
>>>
>>>Yes.
>>
>> Lets go with no 4th IRQ anywhere :)
> 
>After having studied the manual, 4th IRQ might have sometging to do with 
> the input capture channel capability which uses an extra IRQ output.
> 
>> Could you send an updated patch?
> 
>Sure. I'll verify and repost.

   No, the extra IRQ doesn't match the existing of the input capture hardware.

MBR, Sergei

Re: [PATCH v3] clocksource: sh_cmt: fixup for 64-bit machines

[Daniel Lezcano]

On 08/09/2018 22:54, Sergei Shtylyov wrote:
> When trying to use CMT for clockevents on R-Car gen3 SoCs, I noticed
> that 'max_delta_ns' for the broadcast timer (CMT) was shown as 1000 in
> /proc/timer_list. It turned out that when calculating it, the driver did
> 1 << 32 (causing what I think was undefined behavior) resulting in a zero
> delta, later clamped to 1000 by cev_delta2ns(). The root cause turned out
> to be that the driver abused *unsigned long* for the CMT register values
> (which are 16/32-bit), so that the calculation of 'ch->max_match_value'
> in sh_cmt_setup_channel() used the wrong branch. Using more proper 'u32'
> instead fixed 'max_delta_ns' and even fixed the switching an active
> clocksource to CMT (which caused the system to turn non-interactive
> before).
> 
> Signed-off-by: Sergei Shtylyov 

Geert any comments ?

Sergei, in the future please Cc people who did comments on your patch.

Thanks

  -- Daniel

> ---
> This patch is against the 'tip.git' repo's 'timers/core' branch.
> The CMT driver wasn't ever used on SH64; on R-Car gen3 (ARM64) I'm only
> enabling building of this driver now, so not sure how urgent is this...
> 
> Changes in version 3:
> - made the 'overflow_bit' and 'clear_bits' members of 'struct sh_cmt_info'
>   'u32';
> - made the 2nd parameter of sh_cmt_write_cmstr() 'u32';
> - made the result, the 2nd parameter, and 'o{1|2}' local variables of
>   sh_cmt_get_counter() 'u32';
> - made the 'has_wrapped' local variables 'u32' in sh_cmt_clocksource_read()
>   and sh_cmt_clock_event_program_verify();
> - fixed a typo in the patch description.
> 
> Changes in version 2:
> - completely redid the patch, fixing abuse of *unsigned long* for the CMT
>   register values.
> 
>  drivers/clocksource/sh_cmt.c |   72 
> +++
>  1 file changed, 33 insertions(+), 39 deletions(-)
> 
> Index: tip/drivers/clocksource/sh_cmt.c
> ===
> --- tip.orig/drivers/clocksource/sh_cmt.c
> +++ tip/drivers/clocksource/sh_cmt.c
> @@ -78,18 +78,17 @@ struct sh_cmt_info {
>   unsigned int channels_mask;
>  
>   unsigned long width; /* 16 or 32 bit version of hardware block */
> - unsigned long overflow_bit;
> - unsigned long clear_bits;
> + u32 overflow_bit;
> + u32 clear_bits;
>  
>   /* callbacks for CMSTR and CMCSR access */
> - unsigned long (*read_control)(void __iomem *base, unsigned long offs);
> + u32 (*read_control)(void __iomem *base, unsigned long offs);
>   void (*write_control)(void __iomem *base, unsigned long offs,
> -   unsigned long value);
> +   u32 value);
>  
>   /* callbacks for CMCNT and CMCOR access */
> - unsigned long (*read_count)(void __iomem *base, unsigned long offs);
> - void (*write_count)(void __iomem *base, unsigned long offs,
> - unsigned long value);
> + u32 (*read_count)(void __iomem *base, unsigned long offs);
> + void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
>  };
>  
>  struct sh_cmt_channel {
> @@ -103,9 +102,9 @@ struct sh_cmt_channel {
>  
>   unsigned int timer_bit;
>   unsigned long flags;
> - unsigned long match_value;
> - unsigned long next_match_value;
> - unsigned long max_match_value;
> + u32 match_value;
> + u32 next_match_value;
> + u32 max_match_value;
>   raw_spinlock_t lock;
>   struct clock_event_device ced;
>   struct clocksource cs;
> @@ -160,24 +159,22 @@ struct sh_cmt_device {
>  #define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)
>  #define SH_CMT32_CMCSR_CKS_MASK  (7 << 0)
>  
> -static unsigned long sh_cmt_read16(void __iomem *base, unsigned long offs)
> +static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
>  {
>   return ioread16(base + (offs << 1));
>  }
>  
> -static unsigned long sh_cmt_read32(void __iomem *base, unsigned long offs)
> +static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
>  {
>   return ioread32(base + (offs << 2));
>  }
>  
> -static void sh_cmt_write16(void __iomem *base, unsigned long offs,
> -unsigned long value)
> +static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
>  {
>   iowrite16(value, base + (offs << 1));
>  }
>  
> -static void sh_cmt_write32(void __iomem *base, unsigned long offs,
> -unsigned long value)
> +static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
>  {
>   iowrite32(value, base + (offs << 2));
>  }
> @@ -242,7 +239,7 @@ static const struct sh_cmt_info sh_cmt_i
>  #define CMCNT 1 /* channel register */
>  #define CMCOR 2 /* channel register */
>  
> -static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
> +static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
>  {
>   if (ch->iostart)
>   return 

Re: [PATCH] clocksource: sh_cmt: fix clocksource width for 32-bit machines

[Sergei Shtylyov]

Hello!

On 09/13/2018 04:25 PM, Daniel Lezcano wrote:

>> The driver seems to abuse *unsigned long* not only for the (32-bit)
>> register values but also for the 'sh_cmt_channel::total_cycles' which
>> needs to always be 64-bit -- as a result, the clocksource's mask is
>> needlessly clamped down to 32-bits on the 32-bit machines...
>>
>> Reported-by: Geert Uytterhoeven 
>> Signed-off-by: Sergei Shtylyov 
>>
>> ---
>> This patch is against the 'tip.git' repo's 'timers/core' branch plus the 
>> fixup
>> for the 64-bit machines reposted last Saturday...
> 
> Why not against timers/urgent ?

   Mhm... nothing blows up because of this apparently (the bug is quite old).

MBR, Sergei