Re: [PATCH] clk: cs2000: Fix the setting of saved_rate during the resume process

[Kuninori Morimoto]

Hi

> From: Gaku Inami 
> 
> In the resume process, there is the case that other drivers call
> cs2000_enable before cs2000_resume is called. Since the order of
> resume process is not guaranteed, it is needed to reset the clk
> rate in any cases before cs2000 is used.
> 
> Also, the current cs2000 driver is using resume_early function.
> The using .resume_early is bad idea because the dependency with
> other drivers is to be complicated.
> 
> This patch adds to reset the clk rate in cs2000_enable and
> changes to use from .resume_early to .resume.
> 
> Signed-off-by: Gaku Inami 
> Signed-off-by: Hiroyuki Yokoyama 
> Signed-off-by: Yoshihiro Kaneko 
> ---

Acked-by: Kuninori Morimoto 

Re: [PATCH] clk: cs2000: Add cs2000_set_saved_rate

[Kuninori Morimoto]

Hi

> From: Gaku Inami 
> 
> This patch adds the common function to reset the clk rate in order to
> be able to use it in other cases.
> 
> Signed-off-by: Gaku Inami 
> Signed-off-by: Hiroyuki Yokoyama 
> Signed-off-by: Yoshihiro Kaneko 
> ---

Acked-by: Kuninori Morimoto 

Re: Re: Re: "mm: move pcp and lru-pcp draining into single wq" broke resume from s2ram

[Linus Torvalds]

On Wed, Apr 19, 2017 at 1:17 AM, Michal Hocko  wrote:
>
> Thanks for the testing. Linus will you take the patch from this thread
> or you prefer a resend?

I'll take it from this branch since I'm looking at it now, but in
general I prefer resends just because finding patches deep in some
discussion is very iffy.

I get too much email, so it really helps to make the patches more
explicit than this...

  Linus

Re: [PATCH v2] pinctrl: sh-pfc: r8a7794: add R8A7745 support

[Rob Herring]

On Thu, Apr 13, 2017 at 11:19:24PM +0300, Sergei Shtylyov wrote:
> Renesas  RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794),
> however  it doesn't have several automotive specific peripherals.

Is a single space between words really so hard for you? You've been told 
to write proper sentences multiple times.

Yes, kernel developers suffer from OCD. Sorry.

> Annotate all the items that only exist on the R-Car SoCs and only
> supply the pin groups/functions existing on a given SoC (that required
> splitting  of the AVB function)...
> 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
> This patch is  against the 'devel' branch of Linus Walleij's 
> 'linux-pinctrl.git'
> repo plus  R8A7794 PFC fix and R8A7743 PFC support patch...
> 
> Changes in version 2:
> - fixed indentation to use tabs instead of spaces;
> - updated the PFC bindings.
> 
>  Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt |1 

But given it's a one line DT change:

Acked-by: Rob Herring 

>  drivers/pinctrl/sh-pfc/Kconfig|5 
>  drivers/pinctrl/sh-pfc/Makefile   |1 
>  drivers/pinctrl/sh-pfc/core.c |6 
>  drivers/pinctrl/sh-pfc/pfc-r8a7794.c  | 1970 
> +-
>  drivers/pinctrl/sh-pfc/sh_pfc.h   |1 
>  6 files changed, 1140 insertions(+), 844 deletions(-)

Re: [PATCH v3] pinctrl: sh-pfc: r8a7791: add R8A7743 support

[Rob Herring]

On Thu, Apr 13, 2017 at 11:13:32PM +0300, Sergei Shtylyov wrote:
> Renesas RZ/G1M (R8A7743) is pin compatible with R-Car M2-W/N (R8A7791/3),
> however it doesn't have several automotive specific peripherals. Annotate
> all the items that only exist on the R-Car SoCs and only supply  the pin
> groups/functions existing on a given SoC...
> 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
> This patch is against the 'devel' branch of Linus Walleij's 
> 'linux-pinctrl.git'
> repo plus  4  R8A7791 PFC fixes and the "grand I2C rename" patch...
> 
> Changes in version 3:
> - updated the PFC bindings.
> 
> Changes in version 2:
> - switch to supplying exactly the groups/functions existing on a given SoC,
>   update the patch descriptions accordingly;
> - resolved rejects due to the "grand I2C rename" patch being updated.
> 
>  Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt |1 

Acked-by: Rob Herring 

>  drivers/pinctrl/sh-pfc/Kconfig|5 
>  drivers/pinctrl/sh-pfc/Makefile   |1 
>  drivers/pinctrl/sh-pfc/core.c |6 
>  drivers/pinctrl/sh-pfc/pfc-r8a7791.c  | 1889 
> +-
>  drivers/pinctrl/sh-pfc/sh_pfc.h   |1 
>  6 files changed, 1023 insertions(+), 880 deletions(-)

Re: [PATCH v2] sh_eth: unmap DMA buffers when freeing rings

[David Miller]

From: Sergei Shtylyov 
Date: Wed, 19 Apr 2017 22:09:51 +0300

> On 04/17/2017 11:10 PM, David Miller wrote:
> 
>>> The DMA API debugging (when enabled) causes:
>>>
>>> WARNING: CPU: 0 PID: 1445 at lib/dma-debug.c:519
>>> add_dma_entry+0xe0/0x12c
>>> DMA-API: exceeded 7 overlapping mappings of cacheline 0x01b2974d
>>>
>>> to be  printed after repeated initialization of the Ether device, e.g.
>>> suspend/resume or 'ifconfig' up/down. This is because DMA buffers
>>> mapped
>>> using dma_map_single() in sh_eth_ring_format() and sh_eth_start_xmit()
>>> are
>>> never unmapped. Resolve this problem by unmapping the buffers when
>>> freeing
>>> the descriptor rings; in order to do it right, we'd have to add an
>>> extra
>>> parameter to sh_eth_txfree() (we rename this function to
>>> sh_eth_tx_free(),
>>> while at it).
>>>
>>> Based on the commit a47b70ea86bd ("ravb: unmap descriptors when
>>> freeing
>>> rings").
>>>
>>> Signed-off-by: Sergei Shtylyov 
>>
>> Applied, thanks.
> 
>Please don;t forget to send it to -stable.
>The bug seems to be there from the very beginning.

Ok, queued up.

Re: [PATCH v2] sh_eth: unmap DMA buffers when freeing rings

[Sergei Shtylyov]

On 04/17/2017 11:10 PM, David Miller wrote:


The DMA API debugging (when enabled) causes:

WARNING: CPU: 0 PID: 1445 at lib/dma-debug.c:519 add_dma_entry+0xe0/0x12c
DMA-API: exceeded 7 overlapping mappings of cacheline 0x01b2974d

to be  printed after repeated initialization of the Ether device, e.g.
suspend/resume or 'ifconfig' up/down. This is because DMA buffers mapped
using dma_map_single() in sh_eth_ring_format() and sh_eth_start_xmit() are
never unmapped. Resolve this problem by unmapping the buffers when freeing
the descriptor  rings;  in order  to do it right, we'd have to add an extra
parameter to sh_eth_txfree() (we rename this function to sh_eth_tx_free(),
while at it).

Based on the commit a47b70ea86bd ("ravb: unmap descriptors when freeing
rings").

Signed-off-by: Sergei Shtylyov 


Applied, thanks.


   Please don't forget to send this to -stable.
   The bug seems to be there from the very beginning.

MBR, Sergei

Re: [PATCH v2] sh_eth: unmap DMA buffers when freeing rings

[Sergei Shtylyov]

On 04/17/2017 11:10 PM, David Miller wrote:


The DMA API debugging (when enabled) causes:

WARNING: CPU: 0 PID: 1445 at lib/dma-debug.c:519 add_dma_entry+0xe0/0x12c
DMA-API: exceeded 7 overlapping mappings of cacheline 0x01b2974d

to be  printed after repeated initialization of the Ether device, e.g.
suspend/resume or 'ifconfig' up/down. This is because DMA buffers mapped
using dma_map_single() in sh_eth_ring_format() and sh_eth_start_xmit() are
never unmapped. Resolve this problem by unmapping the buffers when freeing
the descriptor  rings;  in order  to do it right, we'd have to add an extra
parameter to sh_eth_txfree() (we rename this function to sh_eth_tx_free(),
while at it).

Based on the commit a47b70ea86bd ("ravb: unmap descriptors when freeing
rings").

Signed-off-by: Sergei Shtylyov 


Applied, thanks.


   Please don;t forget to send it to -stable.
   The bug seems to be there from the very beginning.

MBR, Sergei

Re: [PATCH i2c-tools-3.1] i2c-tools: add new tool 'i2ctransfer'

[Wolfram Sang]

On Fri, Apr 07, 2017 at 02:44:03PM +0200, Wolfram Sang wrote:
> This tool allows to construct and concat multiple I2C messages into one
> single transfer. Its aim is to test I2C master controllers, and so there
> is no SMBus fallback.
> 
> I've been missing such a tool a number of times now, so I finally got
> around to writing it myself. As with all I2C tools, it can be dangerous,
> but it can also be very useful when developing.
> 
> It has been tested with various Renesas I2C IP cores as well as Tegra,
> i.MX and AT91.
> 
> Signed-off-by: Wolfram Sang 
> ---

Pushed to i2c-tools-3.1.



signature.asc
Description: PGP signature

[PATCH] clk: renesas: r8a7796: Add HDMI clock

[Yoshihiro Kaneko]

From: Koji Matsuoka 

This patch adds HDMI-IF0 clock for R8A7796 SoC.

Signed-off-by: Koji Matsuoka 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 9d114b3..1d8c5c2 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -106,6 +106,7 @@ enum clk_ids {
DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
DEF_DIV6P1("csi0",  R8A7796_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
DEF_DIV6P1("mso",   R8A7796_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
+   DEF_DIV6P1("hdmi",  R8A7796_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),
 
DEF_DIV6_RO("osc",  R8A7796_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
DEF_DIV6_RO("r_int",CLK_RINT,  CLK_EXTAL, CPG_RCKCR, 32),
@@ -170,6 +171,7 @@ enum clk_ids {
DEF_MOD("du1",   723,   R8A7796_CLK_S2D1),
DEF_MOD("du0",   724,   R8A7796_CLK_S2D1),
DEF_MOD("lvds",  727,   R8A7796_CLK_S2D1),
+   DEF_MOD("hdmi0", 729,   R8A7796_CLK_HDMI),
DEF_MOD("vin7",  804,   R8A7796_CLK_S0D2),
DEF_MOD("vin6",  805,   R8A7796_CLK_S0D2),
DEF_MOD("vin5",  806,   R8A7796_CLK_S0D2),
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add Z clock

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds Z clock for R8A7796 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 877fc75..a5399f7 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -74,6 +74,7 @@ enum clk_ids {
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2,  2, 1),
 
/* Core Clock Outputs */
+   DEF_BASE("z",   R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_FIXED("ztr",R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
DEF_FIXED("ztrd2",  R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7796_CLK_ZT,CLK_PLL1_DIV2,  4, 1),
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: add PWM clock

[Yoshihiro Kaneko]

From: Ryo Kodama 

This patch adds PWM clock for PWM.

Signed-off-by: Ryo Kodama 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index c5523aa..64714ca 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -156,6 +156,7 @@ enum clk_ids {
DEF_MOD("hscif1",519,   R8A7796_CLK_S3D1),
DEF_MOD("hscif0",520,   R8A7796_CLK_S3D1),
DEF_MOD("thermal",   522,   R8A7796_CLK_CP),
+   DEF_MOD("pwm",   523,   R8A7796_CLK_S3D4),
DEF_MOD("fcpvd2",601,   R8A7796_CLK_S0D2),
DEF_MOD("fcpvd1",602,   R8A7796_CLK_S0D2),
DEF_MOD("fcpvd0",603,   R8A7796_CLK_S0D2),
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add INTC-EX clock

[Yoshihiro Kaneko]

From: Takeshi Kihara 

Add the "intc-ex" clock to the R8A7796 CPG MSSR driver.

According to information from the hardware team the INTC-EX
parent clock is CP. The next data sheet version will include
this information.

[takeshi.kihara.df: Ported from commit f099aa075749 ("clk: shmobile:
 r8a7795: Add INTC-EX clock") to drivers/clk/renesas/r8a7796-cpg-mssr.c]
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index a5399f7..4d1d496 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -142,6 +142,7 @@ enum clk_ids {
DEF_MOD("pcie0", 319,   R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac0", 330,   R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac1", 331,   R8A7796_CLK_S3D1),
+   DEF_MOD("intc-ex",   407,   R8A7796_CLK_CP),
DEF_MOD("intc-ap",   408,   R8A7796_CLK_S3D1),
DEF_MOD("audmac0",   502,   R8A7796_CLK_S3D4),
DEF_MOD("audmac1",   501,   R8A7796_CLK_S3D4),
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add PCIe clocks

[Yoshihiro Kaneko]

From: Harunobu Kurokawa 

This patch adds PCIEC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Harunobu Kurokawa 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 64714ca..877fc75 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -137,6 +137,8 @@ enum clk_ids {
DEF_MOD("sdif1", 313,   R8A7796_CLK_SD1),
DEF_MOD("sdif0", 314,   R8A7796_CLK_SD0),
DEF_MOD("rwdt",  402,   R8A7796_CLK_R),
+   DEF_MOD("pcie1", 318,   R8A7796_CLK_S3D1),
+   DEF_MOD("pcie0", 319,   R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac0", 330,   R8A7796_CLK_S3D1),
DEF_MOD("usb-dmac1", 331,   R8A7796_CLK_S3D1),
DEF_MOD("intc-ap",   408,   R8A7796_CLK_S3D1),
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add Sound SRC clock

[Yoshihiro Kaneko]

From: Kazuya Mizuguchi 

This patch adds SCU(all), SCU(SRC{0,1,2,3,4,5,6,7,8,9}), SCU(CTU00,
CTU01, CTU02, CTU03, MIX0) and SCU (CTU10, CTU11, CTU12, CTU13, MIX1)
clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 9be8187..9a18cb7 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -219,6 +219,19 @@ enum clk_ids {
DEF_MOD("ssi2", 1013,   MOD_CLK_ID(1005)),
DEF_MOD("ssi1", 1014,   MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015,   MOD_CLK_ID(1005)),
+   DEF_MOD("scu-all",  1017,   R8A7796_CLK_S3D4),
+   DEF_MOD("scu-ctu1-mix1",1020,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-ctu0-mix0",1021,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src9", 1022,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src8", 1023,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src7", 1024,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src6", 1025,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src5", 1026,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src4", 1027,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src3", 1028,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src2", 1029,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src1", 1030,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-src0", 1031,   MOD_CLK_ID(1017)),
 };
 
 static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add Sound DVC clocks

[Yoshihiro Kaneko]

From: Kazuya Mizuguchi 

This patch adds adds SCU(DVC{0,1}) clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 9a18cb7..1e16b17 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -220,6 +220,8 @@ enum clk_ids {
DEF_MOD("ssi1", 1014,   MOD_CLK_ID(1005)),
DEF_MOD("ssi0", 1015,   MOD_CLK_ID(1005)),
DEF_MOD("scu-all",  1017,   R8A7796_CLK_S3D4),
+   DEF_MOD("scu-dvc1", 1018,   MOD_CLK_ID(1017)),
+   DEF_MOD("scu-dvc0", 1019,   MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1",1020,   MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0",1021,   MOD_CLK_ID(1017)),
DEF_MOD("scu-src9", 1022,   MOD_CLK_ID(1017)),
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add HS-USB clock

[Yoshihiro Kaneko]

From: Kazuya Mizuguchi 

This patch adds HS-USB-IF clock for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 1e16b17..c5523aa 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -171,6 +171,7 @@ enum clk_ids {
DEF_MOD("vspi0", 631,   R8A7796_CLK_S0D1),
DEF_MOD("ehci1", 702,   R8A7796_CLK_S3D4),
DEF_MOD("ehci0", 703,   R8A7796_CLK_S3D4),
+   DEF_MOD("hsusb", 704,   R8A7796_CLK_S3D4),
DEF_MOD("csi20", 714,   R8A7796_CLK_CSI0),
DEF_MOD("csi40", 716,   R8A7796_CLK_CSI0),
DEF_MOD("du2",   722,   R8A7796_CLK_S2D1),
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add Sound SSI clock

[Yoshihiro Kaneko]

From: Kazuya Mizuguchi 

This patch adds SSI(all) and SSI{0,1,2,3,4,5,6,7,8,9} clocks for R8A7796
SoC.

Signed-off-by: Kazuya Mizuguchi 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 27afd48..9be8187 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -208,6 +208,17 @@ enum clk_ids {
DEF_MOD("i2c2",  929,   R8A7796_CLK_S3D2),
DEF_MOD("i2c1",  930,   R8A7796_CLK_S3D2),
DEF_MOD("i2c0",  931,   R8A7796_CLK_S3D2),
+   DEF_MOD("ssi-all",  1005,   R8A7796_CLK_S3D4),
+   DEF_MOD("ssi9", 1006,   MOD_CLK_ID(1005)),
+   DEF_MOD("ssi8", 1007,   MOD_CLK_ID(1005)),
+   DEF_MOD("ssi7", 1008,   MOD_CLK_ID(1005)),
+   DEF_MOD("ssi6", 1009,   MOD_CLK_ID(1005)),
+   DEF_MOD("ssi5", 1010,   MOD_CLK_ID(1005)),
+   DEF_MOD("ssi4", 1011,   MOD_CLK_ID(1005)),
+   DEF_MOD("ssi3", 1012,   MOD_CLK_ID(1005)),
+   DEF_MOD("ssi2", 1013,   MOD_CLK_ID(1005)),
+   DEF_MOD("ssi1", 1014,   MOD_CLK_ID(1005)),
+   DEF_MOD("ssi0", 1015,   MOD_CLK_ID(1005)),
 };
 
 static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
-- 
1.9.1

[PATCH] clk: cs2000: Fix the setting of saved_rate during the resume process

[Yoshihiro Kaneko]

From: Gaku Inami 

In the resume process, there is the case that other drivers call
cs2000_enable before cs2000_resume is called. Since the order of
resume process is not guaranteed, it is needed to reset the clk
rate in any cases before cs2000 is used.

Also, the current cs2000 driver is using resume_early function.
The using .resume_early is bad idea because the dependency with
other drivers is to be complicated.

This patch adds to reset the clk rate in cs2000_enable and
changes to use from .resume_early to .resume.

Signed-off-by: Gaku Inami 
Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/clk-cs2000-cp.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
index 5b3516d..de6e8c6 100644
--- a/drivers/clk/clk-cs2000-cp.c
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -338,6 +338,10 @@ static int cs2000_enable(struct clk_hw *hw)
struct cs2000_priv *priv = hw_to_priv(hw);
int ret;
 
+   ret = cs2000_set_saved_rate(priv);
+   if (ret < 0)
+   return ret;
+
ret = cs2000_enable_dev_config(priv, true);
if (ret < 0)
return ret;
@@ -530,7 +534,7 @@ static int cs2000_resume(struct device *dev)
 }
 
 static const struct dev_pm_ops cs2000_pm_ops = {
-   .resume_early   = cs2000_resume,
+   .resume = cs2000_resume,
 };
 
 static struct i2c_driver cs2000_driver = {
-- 
1.9.1

[PATCH] clk: renesas: rcar-gen3: Fix error return code in cpg_sd_clock_recalc_rate

[Yoshihiro Kaneko]

From: Takeshi Kihara 

In .recalc_rate of struct clk_ops, it is desirable to return 0 if an
error occurs, but -EINVAL is returned. This patch fixes it.

Fixes: 5b1defde7054 ("clk: renesas: cpg-mssr: Extract common R-Car Gen3 support 
code")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/rcar-gen3-cpg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c 
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 4ab76b1..48c6e98 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -287,7 +287,7 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw 
*hw,
break;
 
if (i >= clock->div_num)
-   return -EINVAL;
+   return 0;
 
return DIV_ROUND_CLOSEST(rate, clock->div_table[i].div);
 }
-- 
1.9.1

[PATCH] clk: renesas: rcar-gen3: Fix SD divider setting

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixed the SD divider settiing for corresponding to the change
in the HS200/HS400 mode.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/rcar-gen3-cpg.c | 41 +++--
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c 
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 8419f27..4ab76b1 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -1,6 +1,7 @@
 /*
  * R-Car Gen3 Clock Pulse Generator
  *
+ * Copyright (C) 2017 Renesas Electronics Corp.
  * Copyright (C) 2015-2016 Glider bvba
  *
  * Based on clk-rcar-gen3.c
@@ -205,29 +206,29 @@ struct sd_clock {
  * sd_srcfc   sd_fc   div
  * stp_hck   stp_ck(div)  (div) = sd_srcfc x sd_fc
  *---
- *  0 0 0 (1)  1 (4)  4
- *  0 0 1 (2)  1 (4)  8
- *  1 0 2 (4)  1 (4) 16
- *  1 0 3 (8)  1 (4) 32
- *  1 0 4 (16) 1 (4) 64
- *  0 0 0 (1)  0 (2)  2
- *  0 0 1 (2)  0 (2)  4
- *  1 0 2 (4)  0 (2)  8
- *  1 0 3 (8)  0 (2) 16
- *  1 0 4 (16) 0 (2) 32
+ *  0 0 1 (2)  0 (-)  2 : HS400
+ *  0 0 0 (1)  1 (4)  4 : SDR104 / HS200
+ *  0 0 1 (2)  1 (4)  8 : SDR50
+ *  1 0 2 (4)  1 (4) 16 : HS / SDR25
+ *  1 0 3 (8)  1 (4) 32 : NS / SDR12
+ *  0 0 0 (1)  0 (2)  2 : (no case)
+ *  1 0 2 (4)  0 (2)  8 : (no case)
+ *  1 0 3 (8)  0 (2) 16 : (no case)
+ *  1 0 4 (16) 0 (2) 32 : (no case)
+ *  1 0 4 (16) 1 (4) 64 : (no case)
  */
 static const struct sd_div_table cpg_sd_div_table[] = {
 /* CPG_SD_DIV_TABLE_DATA(stp_hck,  stp_ck,   sd_srcfc,   sd_fc,  sd_div) */
-   CPG_SD_DIV_TABLE_DATA(0,0,0,  1,4),
-   CPG_SD_DIV_TABLE_DATA(0,0,1,  1,8),
-   CPG_SD_DIV_TABLE_DATA(1,0,2,  1,   16),
-   CPG_SD_DIV_TABLE_DATA(1,0,3,  1,   32),
-   CPG_SD_DIV_TABLE_DATA(1,0,4,  1,   64),
-   CPG_SD_DIV_TABLE_DATA(0,0,0,  0,2),
-   CPG_SD_DIV_TABLE_DATA(0,0,1,  0,4),
-   CPG_SD_DIV_TABLE_DATA(1,0,2,  0,8),
-   CPG_SD_DIV_TABLE_DATA(1,0,3,  0,   16),
-   CPG_SD_DIV_TABLE_DATA(1,0,4,  0,   32),
+   CPG_SD_DIV_TABLE_DATA(0,0,1,  0,2),
+   CPG_SD_DIV_TABLE_DATA(0,0,0,  1,4),
+   CPG_SD_DIV_TABLE_DATA(0,0,1,  1,8),
+   CPG_SD_DIV_TABLE_DATA(1,0,2,  1,   16),
+   CPG_SD_DIV_TABLE_DATA(1,0,3,  1,   32),
+   CPG_SD_DIV_TABLE_DATA(0,0,0,  0,2),
+   CPG_SD_DIV_TABLE_DATA(1,0,2,  0,8),
+   CPG_SD_DIV_TABLE_DATA(1,0,3,  0,   16),
+   CPG_SD_DIV_TABLE_DATA(1,0,4,  0,   32),
+   CPG_SD_DIV_TABLE_DATA(1,0,4,  1,   64),
 };
 
 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add EHCI/OHCI clocks

[Yoshihiro Kaneko]

From: Kazuya Mizuguchi 

This patch adds EHCI/OHCI{0,1} clocks for R8A7796 SoC.

Signed-off-by: Kazuya Mizuguchi 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 1d8c5c2..c6c5026 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -165,6 +165,8 @@ enum clk_ids {
DEF_MOD("vspd0", 623,   R8A7796_CLK_S0D2),
DEF_MOD("vspb",  626,   R8A7796_CLK_S0D1),
DEF_MOD("vspi0", 631,   R8A7796_CLK_S0D1),
+   DEF_MOD("ehci1", 702,   R8A7796_CLK_S3D4),
+   DEF_MOD("ehci0", 703,   R8A7796_CLK_S3D4),
DEF_MOD("csi20", 714,   R8A7796_CLK_CSI0),
DEF_MOD("csi40", 716,   R8A7796_CLK_CSI0),
DEF_MOD("du2",   722,   R8A7796_CLK_S2D1),
-- 
1.9.1

[PATCH] clk: cs2000: Add cs2000_set_saved_rate

[Yoshihiro Kaneko]

From: Gaku Inami 

This patch adds the common function to reset the clk rate in order to
be able to use it in other cases.

Signed-off-by: Gaku Inami 
Signed-off-by: Hiroyuki Yokoyama 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/clk-cs2000-cp.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
index 4df38c5..5b3516d 100644
--- a/drivers/clk/clk-cs2000-cp.c
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -324,6 +324,15 @@ static int cs2000_set_rate(struct clk_hw *hw,
return __cs2000_set_rate(priv, ch, rate, parent_rate);
 }
 
+static int cs2000_set_saved_rate(struct cs2000_priv *priv)
+{
+   int ch = 0; /* it uses ch0 only at this point */
+
+   return __cs2000_set_rate(priv, ch,
+priv->saved_rate,
+priv->saved_parent_rate);
+}
+
 static int cs2000_enable(struct clk_hw *hw)
 {
struct cs2000_priv *priv = hw_to_priv(hw);
@@ -516,11 +525,8 @@ static int cs2000_probe(struct i2c_client *client,
 static int cs2000_resume(struct device *dev)
 {
struct cs2000_priv *priv = dev_get_drvdata(dev);
-   int ch = 0; /* it uses ch0 only at this point */
 
-   return __cs2000_set_rate(priv, ch,
-priv->saved_rate,
-priv->saved_parent_rate);
+   return cs2000_set_saved_rate(priv);
 }
 
 static const struct dev_pm_ops cs2000_pm_ops = {
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add USB-DMAC clocks

[Yoshihiro Kaneko]

From: Hiromitsu Yamasaki 

This patch adds USB-DMAC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index f217796..27afd48 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -137,6 +137,8 @@ enum clk_ids {
DEF_MOD("sdif1", 313,   R8A7796_CLK_SD1),
DEF_MOD("sdif0", 314,   R8A7796_CLK_SD0),
DEF_MOD("rwdt",  402,   R8A7796_CLK_R),
+   DEF_MOD("usb-dmac0", 330,   R8A7796_CLK_S3D1),
+   DEF_MOD("usb-dmac1", 331,   R8A7796_CLK_S3D1),
DEF_MOD("intc-ap",   408,   R8A7796_CLK_S3D1),
DEF_MOD("audmac0",   502,   R8A7796_CLK_S3D4),
DEF_MOD("audmac1",   501,   R8A7796_CLK_S3D4),
-- 
1.9.1

[PATCH] clk: renesas: r8a7796: Add Audio-DMAC clocks

[Yoshihiro Kaneko]

From: Hiromitsu Yamasaki 

This patch adds A-DMAC{0,1} clocks for R8A7796 SoC.

Signed-off-by: Hiromitsu Yamasaki 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index c6c5026..f217796 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -138,6 +138,8 @@ enum clk_ids {
DEF_MOD("sdif0", 314,   R8A7796_CLK_SD0),
DEF_MOD("rwdt",  402,   R8A7796_CLK_R),
DEF_MOD("intc-ap",   408,   R8A7796_CLK_S3D1),
+   DEF_MOD("audmac0",   502,   R8A7796_CLK_S3D4),
+   DEF_MOD("audmac1",   501,   R8A7796_CLK_S3D4),
DEF_MOD("drif7", 508,   R8A7796_CLK_S3D2),
DEF_MOD("drif6", 509,   R8A7796_CLK_S3D2),
DEF_MOD("drif5", 510,   R8A7796_CLK_S3D2),
-- 
1.9.1

[PATCH] clk: renesas: r8a7795: Add USB-DMAC ch3 clock

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch supports the clock of USB-DMAC ch3 module added from R8A7795
ES2.0 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c 
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index e48d5cf..fd4dbc6 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -142,8 +142,10 @@ enum clk_ids {
DEF_MOD("sdif0", 314,   R8A7795_CLK_SD0),
DEF_MOD("pcie1", 318,   R8A7795_CLK_S3D1),
DEF_MOD("pcie0", 319,   R8A7795_CLK_S3D1),
+   DEF_MOD("usb-dmac30",326,   R8A7795_CLK_S3D1),
DEF_MOD("usb3-if1",  327,   R8A7795_CLK_S3D1), /* ES1.x */
DEF_MOD("usb3-if0",  328,   R8A7795_CLK_S3D1),
+   DEF_MOD("usb-dmac31",329,   R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac0", 330,   R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac1", 331,   R8A7795_CLK_S3D1),
DEF_MOD("rwdt",  402,   R8A7795_CLK_R),
-- 
1.9.1

[PATCH] clk: renesas: r8a7795: Add HS-USB ch3 clock

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds valid HS-USB ch3 clock from R8A7795 ES2.0 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c 
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index fd4dbc6..41cd108 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -197,6 +197,7 @@ enum clk_ids {
DEF_MOD("ehci1", 702,   R8A7795_CLK_S3D4),
DEF_MOD("ehci0", 703,   R8A7795_CLK_S3D4),
DEF_MOD("hsusb", 704,   R8A7795_CLK_S3D4),
+   DEF_MOD("hsusb3",705,   R8A7795_CLK_S3D4),
DEF_MOD("csi21", 713,   R8A7795_CLK_CSI0), /* ES1.x */
DEF_MOD("csi20", 714,   R8A7795_CLK_CSI0),
DEF_MOD("csi41", 715,   R8A7795_CLK_CSI0),
-- 
1.9.1

[PATCH] clk: renesas: r8a7795: Add Z clock

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds Z clock for R8A7795 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c 
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index eaa98b4..a9ee68e 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -74,6 +74,7 @@ enum clk_ids {
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2,  2, 1),
 
/* Core Clock Outputs */
+   DEF_BASE("z",   R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
DEF_FIXED("ztr",R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
DEF_FIXED("ztrd2",  R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7795_CLK_ZT,CLK_PLL1_DIV2,  4, 1),
-- 
1.9.1

[PATCH] clk: renesas: r8a7795: Add EHCI/OHCI ch3 clock

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch supports the clock of EHCI/OHCI ch3 module added from R8A7795
ES2.0 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c 
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index a9ee68e..e48d5cf 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -190,6 +190,7 @@ enum clk_ids {
DEF_MOD("vspi2", 629,   R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("vspi1", 630,   R8A7795_CLK_S0D1),
DEF_MOD("vspi0", 631,   R8A7795_CLK_S0D1),
+   DEF_MOD("ehci3", 700,   R8A7795_CLK_S3D4),
DEF_MOD("ehci2", 701,   R8A7795_CLK_S3D4),
DEF_MOD("ehci1", 702,   R8A7795_CLK_S3D4),
DEF_MOD("ehci0", 703,   R8A7795_CLK_S3D4),
-- 
1.9.1

[PATCH] clk: renesas: rcar-gen3: Add Z clock divider support

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch adds Z clock divider support for R-Car Gen3 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
This patch is based on the clk-next branch of linux-clk tree.

 drivers/clk/renesas/rcar-gen3-cpg.c | 143 
 drivers/clk/renesas/rcar-gen3-cpg.h |   1 +
 2 files changed, 144 insertions(+)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c 
b/drivers/clk/renesas/rcar-gen3-cpg.c
index 3dee900..8419f27 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -29,6 +29,145 @@
 #define CPG_PLL2CR 0x002c
 #define CPG_PLL4CR 0x01f4
 
+/** Modify for Z-clock
+ * 
-
+ * Z Clock
+ *
+ * Traits of this clock:
+ * prepare - clk_prepare only ensures that parents are prepared
+ * enable - clk_enable only ensures that parents are enabled
+ * rate - rate is adjustable.  clk->rate = parent->rate * mult / 32
+ * parent - fixed parent.  No clk_set_parent support
+ */
+#define CPG_FRQCRB 0x0004
+#define CPG_FRQCRB_KICKBIT(31)
+#define CPG_FRQCRC 0x00e0
+#define CPG_FRQCRC_ZFC_MASK(0x1f << 8)
+#define CPG_FRQCRC_ZFC_SHIFT   8
+
+
+struct cpg_z_clk {
+   struct clk_hw hw;
+   void __iomem *reg;
+   void __iomem *kick_reg;
+};
+
+#define to_z_clk(_hw)  container_of(_hw, struct cpg_z_clk, hw)
+
+static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
+  unsigned long parent_rate)
+{
+   struct cpg_z_clk *zclk = to_z_clk(hw);
+   unsigned int mult;
+   unsigned int val;
+   unsigned long rate;
+
+   val = (clk_readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK)
+   >> CPG_FRQCRC_ZFC_SHIFT;
+   mult = 32 - val;
+
+   rate = div_u64((u64)parent_rate * mult + 16, 32);
+   /* Round to closest value at 100MHz unit */
+   rate = 1*DIV_ROUND_CLOSEST(rate, 1);
+   return rate;
+}
+
+static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+unsigned long *parent_rate)
+{
+   unsigned long prate  = *parent_rate;
+   unsigned int mult;
+
+   if (!prate)
+   prate = 1;
+
+   mult = div_u64((u64)rate * 32 + prate/2, prate);
+   mult = clamp(mult, 1U, 32U);
+
+   return *parent_rate / 32 * mult;
+}
+
+static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+   struct cpg_z_clk *zclk = to_z_clk(hw);
+   unsigned int mult;
+   u32 val, kick;
+   unsigned int i;
+
+   mult = div_u64((u64)rate * 32 + parent_rate/2, parent_rate);
+   mult = clamp(mult, 1U, 32U);
+
+   if (clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
+   return -EBUSY;
+
+   val = clk_readl(zclk->reg);
+   val &= ~CPG_FRQCRC_ZFC_MASK;
+   val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
+   clk_writel(val, zclk->reg);
+
+   /*
+* Set KICK bit in FRQCRB to update hardware setting and wait for
+* clock change completion.
+*/
+   kick = clk_readl(zclk->kick_reg);
+   kick |= CPG_FRQCRB_KICK;
+   clk_writel(kick, zclk->kick_reg);
+
+   /*
+* Note: There is no HW information about the worst case latency.
+*
+* Using experimental measurements, it seems that no more than
+* ~10 iterations are needed, independently of the CPU rate.
+* Since this value might be dependent of external xtal rate, pll1
+* rate or even the other emulation clocks rate, use 1000 as a
+* "super" safe value.
+*/
+   for (i = 1000; i; i--) {
+   if (!(clk_readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
+   return 0;
+
+   cpu_relax();
+   }
+
+   return -ETIMEDOUT;
+}
+
+static const struct clk_ops cpg_z_clk_ops = {
+   .recalc_rate = cpg_z_clk_recalc_rate,
+   .round_rate = cpg_z_clk_round_rate,
+   .set_rate = cpg_z_clk_set_rate,
+};
+
+static struct clk * __init cpg_z_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *reg)
+{
+   struct clk_init_data init;
+   struct cpg_z_clk *zclk;
+   struct clk *clk;
+
+   zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
+   if (!zclk)
+   return ERR_PTR(-ENOMEM);
+
+   init.name = name;
+   init.ops = _z_clk_ops;
+   init.flags = 0;
+   init.parent_names = _name;
+   init.num_parents = 1;
+
+   zclk->reg = reg + CPG_FRQCRC;
+   zclk->kick_reg = reg + CPG_FRQCRB;
+   zclk->hw.init = 
+
+   clk = clk_register(NULL, >hw);
+   if 

Re: [PATCH 0/3] clk: cs2000: tidyup missing settings

[Stephen Boyd]

On 04/18, Kuninori Morimoto wrote:
> 
> Hi Stephen
> 
> These are missing settings for current cs2000.
> it is working without these settings, thus, not urgent.
> But, necessary for correct/safety operation.

Thanks. Applied all to clk-next. 

> 
> Kuninori Morimoto (3):
>   clk: cs2000: enable clock skipping mode
>   clk: cs2000: tidyup DEVICE_CFG2 settings
>   clk: cs2000: select 12.20 High Accuracy on LFRatioCfg
> 
>  drivers/clk/clk-cs2000-cp.c | 25 ++---
>  1 file changed, 22 insertions(+), 3 deletions(-)
> 
> -- 
> 1.9.1
> 

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Applied "ASoC: rsnd: rsnd_mod_make_sure() is not under DEBUG" to the asoc tree

[Mark Brown]

The patch

   ASoC: rsnd: rsnd_mod_make_sure() is not under DEBUG

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 9ca5e57d78446c8bd42adff3dcae693703f91d9c Mon Sep 17 00:00:00 2001
From: Kuninori Morimoto 
Date: Wed, 19 Apr 2017 00:41:24 +
Subject: [PATCH] ASoC: rsnd: rsnd_mod_make_sure() is not under DEBUG

rsnd_mod_make_sure() will be used any situation,
thus, under DEBUG is not realistic.
This patch move it to non DEBUG area

Signed-off-by: Kuninori Morimoto 
Signed-off-by: Mark Brown 
---
 sound/soc/sh/rcar/core.c | 2 --
 sound/soc/sh/rcar/rsnd.h | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/sound/soc/sh/rcar/core.c b/sound/soc/sh/rcar/core.c
index f8eb9d3d1949..1744015408c3 100644
--- a/sound/soc/sh/rcar/core.c
+++ b/sound/soc/sh/rcar/core.c
@@ -110,7 +110,6 @@ MODULE_DEVICE_TABLE(of, rsnd_of_match);
 /*
  * rsnd_mod functions
  */
-#ifdef DEBUG
 void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type)
 {
if (mod->type != type) {
@@ -121,7 +120,6 @@ void rsnd_mod_make_sure(struct rsnd_mod *mod, enum 
rsnd_mod_type type)
 rsnd_mod_name(mod), rsnd_mod_id(mod));
}
 }
-#endif
 
 char *rsnd_mod_name(struct rsnd_mod *mod)
 {
diff --git a/sound/soc/sh/rcar/rsnd.h b/sound/soc/sh/rcar/rsnd.h
index 3dc9e06f5943..dbf4163427e8 100644
--- a/sound/soc/sh/rcar/rsnd.h
+++ b/sound/soc/sh/rcar/rsnd.h
@@ -727,8 +727,8 @@ void rsnd_cmd_remove(struct rsnd_priv *priv);
 int rsnd_cmd_attach(struct rsnd_dai_stream *io, int id);
 struct rsnd_mod *rsnd_cmd_mod_get(struct rsnd_priv *priv, int id);
 
-#ifdef DEBUG
 void rsnd_mod_make_sure(struct rsnd_mod *mod, enum rsnd_mod_type type);
+#ifdef DEBUG
 #define rsnd_mod_confirm_ssi(mssi) rsnd_mod_make_sure(mssi, RSND_MOD_SSI)
 #define rsnd_mod_confirm_src(msrc) rsnd_mod_make_sure(msrc, RSND_MOD_SRC)
 #define rsnd_mod_confirm_dvc(mdvc) rsnd_mod_make_sure(mdvc, RSND_MOD_DVC)
-- 
2.11.0

Applied "ASoC: ak4613: use snd_soc_update_bits() to avoid Reserve bit on I/O CTRL" to the asoc tree

[Mark Brown]

The patch

   ASoC: ak4613: use snd_soc_update_bits() to avoid Reserve bit on I/O CTRL

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 4898b61e40d62ca1652af40935dbbb5d2e5fd93d Mon Sep 17 00:00:00 2001
From: Kuninori Morimoto 
Date: Wed, 19 Apr 2017 00:40:38 +
Subject: [PATCH] ASoC: ak4613: use snd_soc_update_bits() to avoid Reserve bit
 on I/O CTRL

Signed-off-by: Kuninori Morimoto 
Signed-off-by: Mark Brown 
---
 sound/soc/codecs/ak4613.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/ak4613.c b/sound/soc/codecs/ak4613.c
index e819dd8c82fd..b2dfddead227 100644
--- a/sound/soc/codecs/ak4613.c
+++ b/sound/soc/codecs/ak4613.c
@@ -75,6 +75,12 @@
 #define DFS_DOUBLE_SPEED   (1 << 2)
 #define DFS_QUAD_SPEED (2 << 2)
 
+/* ICTRL */
+#define ICTRL_MASK (0x3)
+
+/* OCTRL */
+#define OCTRL_MASK (0x3F)
+
 struct ak4613_formats {
unsigned int width;
unsigned int fmt;
@@ -365,8 +371,8 @@ static int ak4613_dai_hw_params(struct snd_pcm_substream 
*substream,
snd_soc_update_bits(codec, CTRL1, FMT_MASK, fmt_ctrl);
snd_soc_update_bits(codec, CTRL2, DFS_MASK, ctrl2);
 
-   snd_soc_write(codec, ICTRL, priv->ic);
-   snd_soc_write(codec, OCTRL, priv->oc);
+   snd_soc_update_bits(codec, ICTRL, ICTRL_MASK, priv->ic);
+   snd_soc_update_bits(codec, OCTRL, OCTRL_MASK, priv->oc);
 
 hw_params_end:
if (ret < 0)
-- 
2.11.0

Applied "ASoC: rsnd: enable clock-frequency for both 44.1kHz/48kHz" to the asoc tree

[Mark Brown]

The patch

   ASoC: rsnd: enable clock-frequency for both 44.1kHz/48kHz

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 25165f79adc76b812bfb4d8f2ab120aafb28d0e6 Mon Sep 17 00:00:00 2001
From: Kuninori Morimoto 
Date: Wed, 19 Apr 2017 00:45:52 +
Subject: [PATCH] ASoC: rsnd: enable clock-frequency for both 44.1kHz/48kHz

Current clock-frequency allows only 1 clock, but ADG can
handle both 44.1kHz/48kHz base clocks. This patch enables these.

On Salvator-X board, AUDIO_CLKOUT which is generated by ADG
is connected to ak4613 MCKI, and it should be synchronized with
LRCK. Thus, we need both 44.1kHz/48kHz base clock-frequency.
Otherwise, either one sounds strange in high frequency sound.

Signed-off-by: Kuninori Morimoto 
Tested-by: Hiroyuki Yokoyama 
Signed-off-by: Mark Brown 
---
 sound/soc/sh/rcar/adg.c | 39 ++-
 1 file changed, 26 insertions(+), 13 deletions(-)

diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c
index 214a9ce90bb4..96fef91b480c 100644
--- a/sound/soc/sh/rcar/adg.c
+++ b/sound/soc/sh/rcar/adg.c
@@ -43,6 +43,7 @@ struct rsnd_adg {
 };
 
 #define LRCLK_ASYNC(1 << 0)
+#define AUDIO_OUT_48   (1 << 1)
 #define adg_mode_flags(adg)(adg->flags)
 
 #define for_each_rsnd_clk(pos, adg, i) \
@@ -364,7 +365,10 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, 
unsigned int rate)
 
rsnd_adg_set_ssi_clk(ssi_mod, data);
 
-   if (!(adg_mode_flags(adg) & LRCLK_ASYNC)) {
+   if (adg_mode_flags(adg) & LRCLK_ASYNC) {
+   if (adg_mode_flags(adg) & AUDIO_OUT_48)
+   ckr = 0x8000;
+   } else {
if (0 == (rate % 8000))
ckr = 0x8000;
}
@@ -427,11 +431,14 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
struct clk *clk;
struct device *dev = rsnd_priv_to_dev(priv);
struct device_node *np = dev->of_node;
+   struct property *prop;
u32 ckr, rbgx, rbga, rbgb;
-   u32 rate, req_rate = 0, div;
+   u32 rate, div;
+#define REQ_SIZE 2
+   u32 req_rate[REQ_SIZE] = {};
uint32_t count = 0;
unsigned long req_48kHz_rate, req_441kHz_rate;
-   int i;
+   int i, req_size;
const char *parent_clk_name = NULL;
static const char * const clkout_name[] = {
[CLKOUT]  = "audio_clkout",
@@ -452,13 +459,18 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
 * ADG supports BRRA/BRRB output only
 * this means all clkout0/1/2/3 will be same rate
 */
-   of_property_read_u32(np, "clock-frequency", _rate);
+   prop = of_find_property(np, "clock-frequency", NULL);;
+   req_size = prop->length / sizeof(u32);
+
+   of_property_read_u32_array(np, "clock-frequency", req_rate, req_size);
req_48kHz_rate = 0;
req_441kHz_rate = 0;
-   if (0 == (req_rate % 44100))
-   req_441kHz_rate = req_rate;
-   if (0 == (req_rate % 48000))
-   req_48kHz_rate = req_rate;
+   for (i = 0; i < req_size; i++) {
+   if (0 == (req_rate[i] % 44100))
+   req_441kHz_rate = req_rate[i];
+   if (0 == (req_rate[i] % 48000))
+   req_48kHz_rate = req_rate[i];
+   }
 
/*
 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
@@ -505,10 +517,8 @@ static void rsnd_adg_get_clkout(struct rsnd_priv *priv,
rbgb = rbgx;
adg->rbgb_rate_for_48khz = rate / div;
ckr |= brg_table[i] << 16;
-   if (req_48kHz_rate) {
+   if (req_48kHz_rate)
parent_clk_name = __clk_get_name(clk);
-   ckr |= 0x8000;
-   }
}
}
}
@@ -523,7 +533,7 @@ static void rsnd_adg_get_clkout(struct rsnd_priv 

Re: [PATCH 2/2] arm64: Fix power-of-ten vs. power-of-two prefixes in comments etc.

[Olof Johansson]

On Tue, Apr 18, 2017 at 03:13:12PM +0100, Catalin Marinas wrote:
> On Mon, Apr 17, 2017 at 01:54:49PM +0200, Geert Uytterhoeven wrote:
> > On Mon, Apr 17, 2017 at 1:12 AM, Simon Horman  wrote:
> > > On Thu, Apr 13, 2017 at 01:18:58PM +0100, David Woodhouse wrote:
> > >> Less important than in user-visible messages, but still good practice as
> > >> there's still no excuse for ARM64 code to look like it was written before
> > >> 1996.
> > >>
> > >> Signed-off-by: David Woodhouse 
> > >
> > > Hi David,
> > >
> > > I'd be happy to take the Renesas portions of this change if they were
> > > broken out into a separate patch. The reason I would prefer a separate
> > > patch is to avoid the possibility of conflicts, even trivial ones.
> > 
> > s/possibility/reality/, unless this series goes in before v4.12-rc1.
> 
> Maybe the arm-soc guys can take both patches on top of the other series
> they pull, in which case, for both patches:
> 
> Acked-by: Catalin Marinas 

Sure, please resend to a...@kernel.org with collected acks.

-Olo

Re: [GIT PULL] Renesas ARM Based SoC Sysc Updates for v4.12

[Olof Johansson]

Hi,

On Fri, Apr 07, 2017 at 02:14:07PM -0400, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
> 
> Please consider these Renesas ARM based SoC sysc updates for v4.12.
> 
> This pull request is based on the soc-device-match-tag2 tag of
> Geert Uytterhoeven's renesas-drivers tree which he has already
> sent a pull-request for.

Geert's pull request wasn't cc:d to a...@kernel.org, so I had actually missed it
when it was originally sent (since my inbox tends to get quite a few emails
directly to it).

Merged now, thanks!


-Olof

Re: [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.12

[Olof Johansson]

On Fri, Apr 07, 2017 at 11:58:21AM -0400, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
> 
> Please consider these second round of Renesas ARM based SoC DT updates for
> v4.12.
> 
> This pull request is based on the previous round of
> such requests, tagged as renesas-dt-for-v4.12,
> which you have already pulled.
> 
> 
> The following changes since commit d01ff18992218f3a13f45f45a886b3bf8f250f14:
> 
>   ARM: dts: silk: Drop superfluous status update for frequency override 
> (2017-03-13 10:19:35 +0100)
> 
> are available in the git repository at:
> 
>   https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
> tags/renesas-dt2-for-v4.12
> 
> for you to fetch changes up to eb77d7260c4c25206e2a455be0dbe6443e0856b5:
> 
>   ARM: dts: r8a7791: Drop _clk suffix from external CAN clock node name 
> (2017-04-05 14:16:34 -0400)
> 
> 
> Second Round of Renesas ARM Based SoC DT Updates for v4.12
> 
> Corrections:
> * Correct clock frequency of X2 DU clock input for r8a7791/koelsch board
> * Correct Z clock for r8a7792 SoC
> * Correct parent of SSI[0-9] clocks for r8a779[013] SoCs
> * Correct ethernet clock parent on r7s72100 SoC
> * Correct DU clock for r8a7794/silk board
> 
> Cleanups:
> * Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs
> 
> Enhancements:
> * Enable rtc r7s72100/genmai board
> * Add Z2 clock for r8a7794 SoC
> * Add DU clock for r8a7794 SoC
> * Add power-domains to SDHI for r8a7794 and r7s72100 SoCs
> * Add reset control properties for r8a774[35] SoCs

Merged, thanks!


-Olof

Re: [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v4.12

[Olof Johansson]

On Fri, Apr 07, 2017 at 11:57:59AM -0400, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
> 
> Please consider these second round of Renesas ARM64 based SoC DT updates
> for v4.12.
> 
> This pull request is based on the previous round of
> such requests, tagged as renesas-arm64-dt-for-v4.12,
> which you have already pulled.
> 
> 
> The following changes since commit 3cbe33367d4fd480a92fbc131a96fa925be9e95d:
> 
>   arm64: dts: r8a7796: salvator-x: Drop superfluous status update for 
> frequency override (2017-03-13 10:21:16 +0100)
> 
> are available in the git repository at:
> 
>   https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git 
> tags/renesas-arm64-dt2-for-v4.12
> 
> for you to fetch changes up to 6922bd71adab0a7fe8ffbdc3e72a46431fa29656:
> 
>   arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name 
> (2017-04-05 14:17:19 -0400)
> 
> 
> Second Round of Renesas ARM64 Based SoC DT Updates for v4.12
> 
> Corrections:
> * r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC
> 
> Cleanup:
> * Drop _clk suffix from X12 clock node name for r8a7795 SoC
> 
> Enhancements:
> * Add reset control properties for r8a779[56]
> 

Merged, thanks.


-Olof

[PATCH 4/5] arm64: dts: r8a7796-salvator-x: Add PWM device support

[Ulrich Hecht]

From: Ryo Kodama 

This patch adds support of PWM{1,2} device for Salvator-X board on
R8A7796 SoC.

Signed-off-by: Ryo Kodama 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts 
b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 14d9e51..b4ff1b6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -105,6 +105,18 @@
};
 };
 
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "okay";
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "okay";
+};
+
  {
pinctrl-0 = <_clk_pins>;
pinctrl-names = "default";
@@ -114,6 +126,15 @@
function = "avb";
};
 
+   pwm1_pins: pwm1 {
+   groups = "pwm1_a", "pwm1_b";
+   function = "pwm1";
+   };
+   pwm2_pins: pwm2 {
+   groups = "pwm2_a", "pwm2_b";
+   function = "pwm2";
+   };
+
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
-- 
2.7.4

[PATCH 3/5] arm64: dts: r8a7796: Add PWM device nodes

[Ulrich Hecht]

From: Takeshi Kihara 

This patch adds PWM{0,1,2,3,4,5,6} device nodes for R8A7796 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 63 
 1 file changed, 63 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 798fe0f..578b318 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -455,6 +455,69 @@
status = "disabled";
};
 
+   pwm0: pwm@e6e3 {
+   compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+   reg = <0 0xe6e3 0 0x10>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   pwm1: pwm@e6e31000 {
+   compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+   reg = <0 0xe6e31000 0 0x10>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   pwm2: pwm@e6e32000 {
+   compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+   reg = <0 0xe6e32000 0 0x10>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   pwm3: pwm@e6e33000 {
+   compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+   reg = <0 0xe6e33000 0 0x10>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   pwm4: pwm@e6e34000 {
+   compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+   reg = <0 0xe6e34000 0 0x10>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   pwm5: pwm@e6e35000 {
+   compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+   reg = <0 0xe6e35000 0 0x10>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
+   pwm6: pwm@e6e36000 {
+   compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
+   reg = <0 0xe6e36000 0 0x10>;
+   #pwm-cells = <2>;
+   clocks = < CPG_MOD 523>;
+   power-domains = < R8A7796_PD_ALWAYS_ON>;
+   status = "disabled";
+   };
+
i2c0: i2c@e650 {
#address-cells = <1>;
#size-cells = <0>;
-- 
2.7.4

[PATCH 5/5] arm64: dts: r8a7795-salvator-x: Enable PWM

[Ulrich Hecht]

From: Takeshi Kihara 

This patch enables PWM{1,2} for Salvator-X board on R8A7795 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index bf4674e..842b0dd 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -282,6 +282,18 @@
};
 };
 
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "okay";
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+   status = "okay";
+};
+
  {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
@@ -324,6 +336,16 @@
pinctrl-0 = <_clk_pins>;
pinctrl-names = "default";
 
+   pwm1_pins: pwm1 {
+   groups = "pwm1_a", "pwm1_b";
+   function = "pwm1";
+   };
+
+   pwm2_pins: pwm2 {
+   groups = "pwm2_a", "pwm2_b";
+   function = "pwm2";
+   };
+
scif1_pins: scif1 {
groups = "scif1_data_a", "scif1_ctrl";
function = "scif1";
-- 
2.7.4

[PATCH 1/5] pinctrl: sh-pfc: r8a7796: Add PWM pins, groups and functions

[Ulrich Hecht]

From: Takeshi Kihara 

This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to
R8A7796 SoC.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 153 +++
 1 file changed, 153 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index b0362ae..668c688 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -2955,6 +2955,105 @@ static const unsigned int msiof3_rxd_e_mux[] = {
MSIOF3_RXD_E_MARK,
 };
 
+/* - PWM0 
*/
+static const unsigned int pwm0_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 6),
+};
+static const unsigned int pwm0_mux[] = {
+   PWM0_MARK,
+};
+/* - PWM1 
*/
+static const unsigned int pwm1_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 7),
+};
+static const unsigned int pwm1_a_mux[] = {
+   PWM1_A_MARK,
+};
+static const unsigned int pwm1_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 8),
+};
+static const unsigned int pwm1_b_mux[] = {
+   PWM1_B_MARK,
+};
+/* - PWM2 
*/
+static const unsigned int pwm2_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 8),
+};
+static const unsigned int pwm2_a_mux[] = {
+   PWM2_A_MARK,
+};
+static const unsigned int pwm2_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 11),
+};
+static const unsigned int pwm2_b_mux[] = {
+   PWM2_B_MARK,
+};
+/* - PWM3 
*/
+static const unsigned int pwm3_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 0),
+};
+static const unsigned int pwm3_a_mux[] = {
+   PWM3_A_MARK,
+};
+static const unsigned int pwm3_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 2),
+};
+static const unsigned int pwm3_b_mux[] = {
+   PWM3_B_MARK,
+};
+/* - PWM4 
*/
+static const unsigned int pwm4_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 1),
+};
+static const unsigned int pwm4_a_mux[] = {
+   PWM4_A_MARK,
+};
+static const unsigned int pwm4_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 3),
+};
+static const unsigned int pwm4_b_mux[] = {
+   PWM4_B_MARK,
+};
+/* - PWM5 
*/
+static const unsigned int pwm5_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 2),
+};
+static const unsigned int pwm5_a_mux[] = {
+   PWM5_A_MARK,
+};
+static const unsigned int pwm5_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 4),
+};
+static const unsigned int pwm5_b_mux[] = {
+   PWM5_B_MARK,
+};
+/* - PWM6 
*/
+static const unsigned int pwm6_a_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(1, 3),
+};
+static const unsigned int pwm6_a_mux[] = {
+   PWM6_A_MARK,
+};
+static const unsigned int pwm6_b_pins[] = {
+   /* PWM */
+   RCAR_GP_PIN(2, 5),
+};
+static const unsigned int pwm6_b_mux[] = {
+   PWM6_B_MARK,
+};
+
 /* - SCIF0 -- 
*/
 static const unsigned int scif0_data_pins[] = {
/* RX, TX */
@@ -3565,6 +3664,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(msiof3_ss2_e),
SH_PFC_PIN_GROUP(msiof3_txd_e),
SH_PFC_PIN_GROUP(msiof3_rxd_e),
+   SH_PFC_PIN_GROUP(pwm0),
+   SH_PFC_PIN_GROUP(pwm1_a),
+   SH_PFC_PIN_GROUP(pwm1_b),
+   SH_PFC_PIN_GROUP(pwm2_a),
+   SH_PFC_PIN_GROUP(pwm2_b),
+   SH_PFC_PIN_GROUP(pwm3_a),
+   SH_PFC_PIN_GROUP(pwm3_b),
+   SH_PFC_PIN_GROUP(pwm4_a),
+   SH_PFC_PIN_GROUP(pwm4_b),
+   SH_PFC_PIN_GROUP(pwm5_a),
+   SH_PFC_PIN_GROUP(pwm5_b),
+   SH_PFC_PIN_GROUP(pwm6_a),
+   SH_PFC_PIN_GROUP(pwm6_b),
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -3879,6 +3991,40 @@ static const char * const msiof3_groups[] = {
"msiof3_rxd_e",
 };
 
+static const char * const pwm0_groups[] = {
+   "pwm0",
+};
+
+static const char * const pwm1_groups[] = {
+   "pwm1_a",
+   "pwm1_b",
+};
+
+static const char * const pwm2_groups[] = {
+   "pwm2_a",
+   "pwm2_b",
+};
+
+static const char * const pwm3_groups[] = {
+   "pwm3_a",
+   "pwm3_b",
+};
+
+static const char * const pwm4_groups[] = {
+   "pwm4_a",
+   "pwm4_b",
+};
+
+static const char * const pwm5_groups[] = {
+   "pwm5_a",
+   "pwm5_b",
+};
+
+static const char * const pwm6_groups[] = {
+   "pwm6_a",
+   "pwm6_b",
+};
+
 static const char 

[PATCH 2/5] clk: renesas: r8a7796: add PWM clock

[Ulrich Hecht]

From: Ryo Kodama 

This patch adds PWM clock for PWM.

Signed-off-by: Ryo Kodama 
Signed-off-by: Takeshi Kihara 
Signed-off-by: Ulrich Hecht 
---
 drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c 
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 9d114b3..be0fc00 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -151,6 +151,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] 
__initconst = {
DEF_MOD("hscif1",519,   R8A7796_CLK_S3D1),
DEF_MOD("hscif0",520,   R8A7796_CLK_S3D1),
DEF_MOD("thermal",   522,   R8A7796_CLK_CP),
+   DEF_MOD("pwm",   523,   R8A7796_CLK_S3D4),
DEF_MOD("fcpvd2",601,   R8A7796_CLK_S0D2),
DEF_MOD("fcpvd1",602,   R8A7796_CLK_S0D2),
DEF_MOD("fcpvd0",603,   R8A7796_CLK_S0D2),
-- 
2.7.4

Re: [PATCH] pinctrl: sh-pfc: r8a7791: grand I2C rename

[Geert Uytterhoeven]

Hi Sergei,

On Fri, Apr 7, 2017 at 10:02 PM, Sergei Shtylyov
 wrote:
> The R8A7791 PFC driver  was apparently based on the preliminary revisions
> of  the  user's manual, which called all the I2C signals {SCL|SDA} and
> MOD_SEL register fields SEL_IIC without making a difference between two
> types of the I2C controllers used. The recent manual calls the signals
> {I2C|IIC}_{SCL|SDA> and the MOD_SEL fields SEL_{I2C|IIC} finally
> making this difference. Follow the suit...

Thanks for your patch!

> Signed-off-by: Sergei Shtylyov 

No difference in the generated binary, good!

Reviewed-by: Geert Uytterhoeven 
i.e. will queue in sh-pfc-for-v4.13.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] ASoC: ak4613: use snd_soc_update_bits() to avoid Reserve bit on I/O CTRL

[Sergei Shtylyov]

Hello!

On 4/19/2017 3:40 AM, Kuninori Morimoto wrote:


From: Kuninori Morimoto 

Signed-off-by: Kuninori Morimoto 
---
 sound/soc/codecs/ak4613.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/sound/soc/codecs/ak4613.c b/sound/soc/codecs/ak4613.c
index e819dd8..b2dfdde 100644
--- a/sound/soc/codecs/ak4613.c
+++ b/sound/soc/codecs/ak4613.c
@@ -75,6 +75,12 @@
 #define DFS_DOUBLE_SPEED   (1 << 2)
 #define DFS_QUAD_SPEED (2 << 2)

+/* ICTRL */
+#define ICTRL_MASK (0x3)
+
+/* OCTRL */
+#define OCTRL_MASK (0x3F)


   Parens not needed here and above, these are not expressions.

WBR, Sergei

[PATCH 7/8] [RFC] arm64: dts: renesas: Migrate H3ULCB to r8j7795-4x1g.dtsi

[Geert Uytterhoeven]

The Renesas R-Car Starter Kit Premier (H3ULCB) development board is
equipped with an r8j7795 SiP with 4 GiB of RAM.

Hence migrate from r8a7795.dtsi to r8j7795-4x1g.dtsi.

Signed-off-by: Geert Uytterhoeven 
---
Questions:
  - Should this file be renamed to r8j7795-h3ulcb.dts?
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 27 +++---
 1 file changed, 3 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index 3574965e074718d8..fe7eca39490eb1a2 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -10,13 +10,13 @@
  */
 
 /dts-v1/;
-#include "r8a7795.dtsi"
+#include "r8j7795-4x1g.dtsi"
 #include 
 #include 
 
 / {
-   model = "Renesas H3ULCB board based on r8a7795";
-   compatible = "renesas,h3ulcb", "renesas,r8a7795";
+   model = "Renesas H3ULCB board based on r8j7795";
+   compatible = "renesas,h3ulcb", "renesas,r8j7795", "renesas,r8a7795";
 
aliases {
serial0 = 
@@ -27,27 +27,6 @@
stdout-path = "serial0:115200n8";
};
 
-   memory@4800 {
-   device_type = "memory";
-   /* first 128MB is reserved for secure area. */
-   reg = <0x0 0x4800 0x0 0x3800>;
-   };
-
-   memory@5 {
-   device_type = "memory";
-   reg = <0x5 0x 0x0 0x4000>;
-   };
-
-   memory@6 {
-   device_type = "memory";
-   reg = <0x6 0x 0x0 0x4000>;
-   };
-
-   memory@7 {
-   device_type = "memory";
-   reg = <0x7 0x 0x0 0x4000>;
-   };
-
leds {
compatible = "gpio-leds";
 
-- 
2.7.4

[PATCH 4/8] [RFC] arm64: dts: renesas: Add R-Car M3-W SiP (2 x 2 GiB) support

[Geert Uytterhoeven]

Add support for the R-Car M3-W System-in-Package (r8j7796), which contains:
  - an R-Car M3-W SoC (r8a7796),
  - 2 channels of 2 GiB of RAM (4 GiB total),
  - HyperFlash (not yet described).

Signed-off-by: Geert Uytterhoeven 
---
Questions:
  - Should this file be named r8j7796-4g.dtsi instead?
  - What's the official name of r8j7796 with 2 x 2 GiB of RAM?
---
 arch/arm64/boot/dts/renesas/r8j7796-2x2g.dtsi | 26 ++
 1 file changed, 26 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8j7796-2x2g.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8j7796-2x2g.dtsi 
b/arch/arm64/boot/dts/renesas/r8j7796-2x2g.dtsi
new file mode 100644
index ..9623bd2b4a914ae3
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8j7796-2x2g.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Device Tree Source for the r8a7796 SiP with 2 channels of 2 GiB RAM
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7796.dtsi"
+
+/ {
+   compatible = "renesas,r8j7796", "renesas,r8a7796";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x7800>;
+   };
+
+   memory@6 {
+   device_type = "memory";
+   reg = <0x6 0x 0x0 0x8000>;
+   };
+};
-- 
2.7.4

[PATCH 5/8] [RFC] arm64: dts: renesas: Migrate R-Car H3 Salvator-X to r8j7795-4x1g.dtsi

[Geert Uytterhoeven]

The Renesas R-Car H3 Salvator-X development board is equipped with an
r8j7795 SiP with 4 GiB of RAM.

Hence migrate from r8a7795.dtsi to r8j7795-4x1g.dtsi.

Signed-off-by: Geert Uytterhoeven 
---
Questions:
  - Should this file be renamed to r8j7795-salvator-x.dts?
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 27 +++---
 1 file changed, 3 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index ff68bac4cd7ed2f5..e5b9409bf2d218d8 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -32,12 +32,12 @@
  */
 
 /dts-v1/;
-#include "r8a7795.dtsi"
+#include "r8j7795-4x1g.dtsi"
 #include 
 
 / {
-   model = "Renesas Salvator-X board based on r8a7795";
-   compatible = "renesas,salvator-x", "renesas,r8a7795";
+   model = "Renesas Salvator-X board based on r8j7795";
+   compatible = "renesas,salvator-x", "renesas,r8j7795", "renesas,r8a7795";
 
aliases {
serial0 = 
@@ -50,27 +50,6 @@
stdout-path = "serial0:115200n8";
};
 
-   memory@4800 {
-   device_type = "memory";
-   /* first 128MB is reserved for secure area. */
-   reg = <0x0 0x4800 0x0 0x3800>;
-   };
-
-   memory@5 {
-   device_type = "memory";
-   reg = <0x5 0x 0x0 0x4000>;
-   };
-
-   memory@6 {
-   device_type = "memory";
-   reg = <0x6 0x 0x0 0x4000>;
-   };
-
-   memory@7 {
-   device_type = "memory";
-   reg = <0x7 0x 0x0 0x4000>;
-   };
-
x12_clk: x12 {
compatible = "fixed-clock";
#clock-cells = <0>;
-- 
2.7.4

[PATCH 2/8] [RFC] arm64: dts: renesas: Add R-Car H3 SiP (4 x 1 GiB) support

[Geert Uytterhoeven]

Add support for the R-Car H3 System-in-Package (r8j7795), which contains:
  - an R-Car H3 SoC (r8a7795),
  - 4 channels of 1 GiB of RAM (4 GiB total),
  - HyperFlash (not yet described).

Signed-off-by: Geert Uytterhoeven 
---
Questions:
  - Should this file be named r8j7795-4g.dtsi instead?
  - Do other versions (different memory configuration) of r8j7795 exist?
If yes, how are they named?
---
 arch/arm64/boot/dts/renesas/r8j7795-4x1g.dtsi | 36 +++
 1 file changed, 36 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8j7795-4x1g.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8j7795-4x1g.dtsi 
b/arch/arm64/boot/dts/renesas/r8j7795-4x1g.dtsi
new file mode 100644
index ..02e0ff4a60c53704
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8j7795-4x1g.dtsi
@@ -0,0 +1,36 @@
+/*
+ * Device Tree Source for the r8j7795 SiP with 4 channels of 1 GiB RAM
+ *
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7795.dtsi"
+
+/ {
+   compatible = "renesas,r8j7795", "renesas,r8a7795";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x3800>;
+   };
+
+   memory@5 {
+   device_type = "memory";
+   reg = <0x5 0x 0 0x4000>;
+   };
+
+   memory@6 {
+   device_type = "memory";
+   reg = <0x6 0x 0 0x4000>;
+   };
+
+   memory@7 {
+   device_type = "memory";
+   reg = <0x7 0x 0 0x4000>;
+   };
+};
-- 
2.7.4

[PATCH 3/8] [RFC] arm64: dts: renesas: Add R-Car M3-W SiP (2 x 1 GiB) support

[Geert Uytterhoeven]

Add support for the R-Car M3-W System-in-Package (r8j7796), which contains:
  - an R-Car M3-W SoC (r8a7796),
  - 2 channels of 1 GiB of RAM (2 GiB total),
  - HyperFlash (not yet described).

Signed-off-by: Geert Uytterhoeven 
---
Questions:
  - Should this file be named r8j7796-2g.dtsi instead?
  - What's the official name of r8j7796 with 2 x 1 GiB of RAM?
---
 arch/arm64/boot/dts/renesas/r8j7796-2x1g.dtsi | 26 ++
 1 file changed, 26 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8j7796-2x1g.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8j7796-2x1g.dtsi 
b/arch/arm64/boot/dts/renesas/r8j7796-2x1g.dtsi
new file mode 100644
index ..ba274c132e6dd984
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8j7796-2x1g.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Device Tree Source for the r8a7796 SiP with 2 channels of 1 GiB RAM
+ *
+ * Copyright (C) 2016 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7796.dtsi"
+
+/ {
+   compatible = "renesas,r8j7796", "renesas,r8a7796";
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0x0 0x4800 0x0 0x3800>;
+   };
+
+   memory@6 {
+   device_type = "memory";
+   reg = <0x6 0x 0x0 0x4000>;
+   };
+};
-- 
2.7.4

[PATCH 1/8] [RFC] dt-bindings: renesas: Document R-Car H3 and M3-W SiP DT bindings

[Geert Uytterhoeven]

Document the SiP ("System-in-Package") versions of the R-Car H3 and M3-W
SoCs, which contain an R-Car H3 or M3-W SoC, RAM, and HyperFlash.

Add their compatible values to all boards equipped with R-Car Gen3 SiPs.

Signed-off-by: Geert Uytterhoeven 
---
Questions:
  - Do we need more compatible values, for different configurations?
At least r8j7796 is available with either 2 GiB or 4 GiB of RAM,
possibly using RAM parts from different vendors.
---
 Documentation/devicetree/bindings/arm/shmobile.txt | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt 
b/Documentation/devicetree/bindings/arm/shmobile.txt
index 170fe0562c637eab..8ca3f64fec21d8b0 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -41,6 +41,14 @@ SoCs:
 compatible = "renesas,r8a7796"
 
 
+SiPs:
+
+  - R-Car H3 SiP (R8J77950)
+compatible = "renesas,r8j7795", "renesas,r8a7795"
+  - R-Car M3-W SiP (R8J77960)
+compatible = "renesas,r8j7796", "renesas,r8a7796"
+
+
 Boards:
 
   - Alt (RTP0RC7794SEB00010S)
@@ -58,7 +66,7 @@ Boards:
   - Gose (RTP0RC7793SEB00010S)
 compatible = "renesas,gose", "renesas,r8a7793"
   - H3ULCB (R-Car Starter Kit Premier, RTP0RC7795SKB00010S)
-compatible = "renesas,h3ulcb", "renesas,r8a7795";
+compatible = "renesas,h3ulcb", "renesas,r8j7795", "renesas,r8a7795";
   - Henninger
 compatible = "renesas,henninger", "renesas,r8a7791"
   - Koelsch (RTP0RC7791SEB00010S)
@@ -70,7 +78,7 @@ Boards:
   - Lager (RTP0RC7790SEB00010S)
 compatible = "renesas,lager", "renesas,r8a7790"
   - M3ULCB (R-Car Starter Kit Pro, RTP0RC7796SKB00010S)
-compatible = "renesas,m3ulcb", "renesas,r8a7796";
+compatible = "renesas,m3ulcb", "renesas,r8j7796", "renesas,r8a7796";
   - Marzen (R0P7779A00010S)
 compatible = "renesas,marzen", "renesas,r8a7779"
   - Porter (M2-LCDP)
@@ -78,9 +86,9 @@ Boards:
   - RSKRZA1 (YR0K77210C000BE)
 compatible = "renesas,rskrza1", "renesas,r7s72100"
   - Salvator-X (RTP0RC7795SIPB0010S)
-compatible = "renesas,salvator-x", "renesas,r8a7795";
+compatible = "renesas,salvator-x", "renesas,r8j7795", "renesas,r8a7795";
   - Salvator-X (RTP0RC7796SIPB0011S)
-compatible = "renesas,salvator-x", "renesas,r8a7796";
+compatible = "renesas,salvator-x", "renesas,r8j7796", "renesas,r8a7796";
   - SILK (RTP0RC7794LCB00011S)
 compatible = "renesas,silk", "renesas,r8a7794"
   - SK-RZG1E (YR8A77450S000BE)
-- 
2.7.4

[PATCH 0/8] arm64: dts: renesas: Break out R-Car H3 and M3-W SiP

[Geert Uytterhoeven]

Hi all,

Renesas R-Car H3 and M3-W are available as SoC (r8a779[56]) or SiP
(r8j779[56]).  The latter is an integrated package
("System-in-Package"), containing an SoC, RAM, and HyperFlash.

This patch series adds DT bindings for the SiPs, breaks out hardware
descriptions for the SiPs into separate .dtsi files, and migrates the
board-specific DTSes from the SoC-specific to the SiP-specific .dtsi
files.

The motivations for this are:
  - Provide a better description of the hardware hierarchy,
  - Share more DTS fragments (not that visible due to boilerplate and
limited number of boards),
  - Some quirks may be SiP-specific.
I believe this is the case for the limitation of RAVB Ethernet to
10/100 Mbps on H3 ES1.0.

Questions (reiterated in the individual patches):
  - Do we need more compatible values, for different configurations?
At least r8j7796 is available with either 2 GiB or 4 GiB of RAM,
possibly using RAM parts from different vendors.
  - How are the different SiP versions named officially?
  - How should the .dtsi files be named?
  - Should the board-specific files be renamed from -.dts to
-.dts?
Probably not, as this would inconvenience downstream developers even
more than the H3 ES1.x rename, and  is not that incorrect.

DTB changes have been inspected using scripts/dtc/dtx_diff.
This has been tested on Salvator-X (both H3 and M3-W).

Thanks for your comments!

Geert Uytterhoeven (8):
  [RFC] dt-bindings: renesas: Document R-Car H3 and M3-W SiP DT bindings
  [RFC] arm64: dts: renesas: Add R-Car H3 SiP (4 x 1 GiB) support
  [RFC] arm64: dts: renesas: Add R-Car M3-W SiP (2 x 1 GiB) support
  [RFC] arm64: dts: renesas: Add R-Car M3-W SiP (2 x 2 GiB) support
  [RFC] arm64: dts: renesas: Migrate R-Car H3 Salvator-X to
r8j7795-4x1g.dtsi
  [RFC] arm64: dts: renesas: Migrate R-Car M3-W Salvator-X to
r8j7796-2x2g.dtsi
  [RFC] arm64: dts: renesas: Migrate H3ULCB to r8j7795-4x1g.dtsi
  [RFC] arm64: dts: renesas: Migrate M3ULCB to r8j7796-2x1g.dtsi

 Documentation/devicetree/bindings/arm/shmobile.txt | 16 +++---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 27 ++--
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 27 ++--
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 17 ++
 arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 17 ++
 arch/arm64/boot/dts/renesas/r8j7795-4x1g.dtsi  | 36 ++
 arch/arm64/boot/dts/renesas/r8j7796-2x1g.dtsi  | 26 
 arch/arm64/boot/dts/renesas/r8j7796-2x2g.dtsi  | 26 
 8 files changed, 112 insertions(+), 80 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r8j7795-4x1g.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r8j7796-2x1g.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r8j7796-2x2g.dtsi

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 8/8] [RFC] arm64: dts: renesas: Migrate M3ULCB to r8j7796-2x1g.dtsi

[Geert Uytterhoeven]

The Renesas R-Car Starter Kit Pro (M3ULCB) development board is equipped
with an r8j7796 SiP with 2 GiB of RAM.

Hence migrate from r8a7796.dtsi to r8j7796-2x1g.dtsi.

Signed-off-by: Geert Uytterhoeven 
---
Questions:
  - Should this file be renamed to r8j7796-m3ulcb.dts?
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 17 +++--
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts 
b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index c2a4549d3738f81c..533d03662e98982b 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -10,13 +10,13 @@
  */
 
 /dts-v1/;
-#include "r8a7796.dtsi"
+#include "r8j7796-2x1g.dtsi"
 #include 
 #include 
 
 / {
-   model = "Renesas M3ULCB board based on r8a7796";
-   compatible = "renesas,m3ulcb", "renesas,r8a7796";
+   model = "Renesas M3ULCB board based on r8j7796";
+   compatible = "renesas,m3ulcb", "renesas,r8j7796", "renesas,r8a7796";
 
aliases {
serial0 = 
@@ -27,17 +27,6 @@
stdout-path = "serial0:115200n8";
};
 
-   memory@4800 {
-   device_type = "memory";
-   /* first 128MB is reserved for secure area. */
-   reg = <0x0 0x4800 0x0 0x3800>;
-   };
-
-   memory@6 {
-   device_type = "memory";
-   reg = <0x6 0x 0x0 0x4000>;
-   };
-
leds {
compatible = "gpio-leds";
 
-- 
2.7.4

Re: [PATCH v5 4/4] arm64: dts: salvator-x: Add current sense amplifiers

[Geert Uytterhoeven]

Hi Jacopo,

On Thu, Apr 6, 2017 at 4:20 PM, Jacopo Mondi  wrote:
> [PATCH v5 4/4] arm64: dts: salvator-x: Add current sense amplifiers

This should be "arm64: dts: r8a7796: salvator-x: Add current sense amplifiers".
Perhaps Simon can just fix that himself while applying?

> Add device nodes for two Maxim max961x current sense amplifiers
> sensing VDD_08 and DVFS_08 lines.
>
> Signed-off-by: Jacopo Mondi 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2] arm64: dts: r8a7795: salvator-x: Add current sense amplifiers

[Geert Uytterhoeven]

Add device nodes for two Maxim max961x current sense amplifiers
sensing the VDD_0.8V and DVFS_0.8V lines.

Based on a patch for r8a7796-salvator-x.dts by Jacopo Mondi.

Signed-off-by: Geert Uytterhoeven 
---
Bindings and driver are now in staging-next.

v2:
  - Use shunt-resistor-micro-ohms to match updated bindings.
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index ff68bac4cd7ed2f5..bd6cccb0d4a75561 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -415,6 +415,24 @@
};
 };
 
+ {
+   status = "okay";
+
+   csa_vdd: adc@7c {
+   compatible = "maxim,max9611";
+   reg = <0x7c>;
+
+   shunt-resistor-micro-ohms = <5000>;
+   };
+
+   csa_dvfs: adc@7f {
+   compatible = "maxim,max9611";
+   reg = <0x7f>;
+
+   shunt-resistor-micro-ohms = <5000>;
+   };
+};
+
 _sound {
pinctrl-0 = <_pins _clk_pins>;
pinctrl-names = "default";
-- 
2.7.4

[PATCH] arm64: dts: r8a7795: salvator-x: Add current sense amplifiers

[Geert Uytterhoeven]

Add device nodes for two Maxim max961x current sense amplifiers
sensing the VDD_0.8V and DVFS_0.8V lines.

Based on a patch for r8a7796-salvator-x.dts by Jacopo Mondi.

Signed-off-by: Geert Uytterhoeven 
---
Bindings and driver are now in staging-next.

v2:
  - Use shunt-resistor-micro-ohms to match updated bindings.
---
 arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index ff68bac4cd7ed2f5..bd6cccb0d4a75561 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -415,6 +415,24 @@
};
 };
 
+ {
+   status = "okay";
+
+   csa_vdd: adc@7c {
+   compatible = "maxim,max9611";
+   reg = <0x7c>;
+
+   shunt-resistor-micro-ohms = <5000>;
+   };
+
+   csa_dvfs: adc@7f {
+   compatible = "maxim,max9611";
+   reg = <0x7f>;
+
+   shunt-resistor-micro-ohms = <5000>;
+   };
+};
+
 _sound {
pinctrl-0 = <_pins _clk_pins>;
pinctrl-names = "default";
-- 
2.7.4

Re: Re: Re: "mm: move pcp and lru-pcp draining into single wq" broke resume from s2ram

[Michal Hocko]

On Wed 19-04-17 10:09:12, Geert Uytterhoeven wrote:
> Hi Michal, Tetsuo,
> 
> On Wed, Apr 19, 2017 at 9:57 AM, Michal Hocko  wrote:
> > From f3c6e287042259d6ae9916f1ff66392c46ce2a3c Mon Sep 17 00:00:00 2001
> > From: Michal Hocko 
> > Date: Wed, 19 Apr 2017 09:52:46 +0200
> > Subject: [PATCH] mm: make mm_percpu_wq non freezable
> >
> > Geert has reported a freeze during PM resume and some additional
> > debugging has shown that the device_resume worker cannot make a forward
> > progress because it waits for an event which is stuck waiting in
> > drain_all_pages:
> > [  243.691979] INFO: task kworker/u4:0:5 blocked for more than 120 seconds.
> > [  243.698684]   Not tainted 
> > 4.11.0-rc7-koelsch-00029-g005882e53d62f25d-dirty #3476
> > [  243.706439] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables 
> > this message.
> > [  243.714276] kworker/u4:0D0 5  2 0x
> > [  243.719780] Workqueue: events_unbound async_run_entry_fn
> > [  243.725118] [] (__schedule) from [] 
> > (schedule+0xb0/0xcc)
> > [  243.732181] [] (schedule) from [] 
> > (schedule_timeout+0x18/0x1f4)
> > [  243.739840] [] (schedule_timeout) from [] 
> > (wait_for_common+0x100/0x19c)
> > [  243.748207] [] (wait_for_common) from [] 
> > (dpm_wait_for_superior+0x14/0x5c)
> > [  243.756836] [] (dpm_wait_for_superior) from [] 
> > (device_resume+0x40/0x1a0)
> > [  243.765380] [] (device_resume) from [] 
> > (async_resume+0x18/0x44)
> > [  243.773055] [] (async_resume) from [] 
> > (async_run_entry_fn+0x44/0x114)
> > [  243.781245] [] (async_run_entry_fn) from [] 
> > (process_one_work+0x1cc/0x31c)
> > [  243.789876] [] (process_one_work) from [] 
> > (worker_thread+0x2b8/0x3f0)
> > [  243.798080] [] (worker_thread) from [] 
> > (kthread+0x120/0x140)
> > [  243.805500] [] (kthread) from [] 
> > (ret_from_fork+0x14/0x2c)
> > [...]
> > [  249.441198] bashD0  1703   1694 0x
> > [  249.446702] [] (__schedule) from [] 
> > (schedule+0xb0/0xcc)
> > [  249.453764] [] (schedule) from [] 
> > (schedule_timeout+0x18/0x1f4)
> > [  249.461427] [] (schedule_timeout) from [] 
> > (wait_for_common+0x100/0x19c)
> > [  249.469797] [] (wait_for_common) from [] 
> > (flush_work+0x128/0x158)
> > [  249.477650] [] (flush_work) from [] 
> > (drain_all_pages+0x198/0x1f0)
> > [  249.485503] [] (drain_all_pages) from [] 
> > (start_isolate_page_range+0xd8/0x1ac)
> > [  249.494484] [] (start_isolate_page_range) from [] 
> > (alloc_contig_range+0xc4/0x304)
> > [  249.503724] [] (alloc_contig_range) from [] 
> > (cma_alloc+0x134/0x1bc)
> > [  249.511739] [] (cma_alloc) from [] 
> > (__alloc_from_contiguous+0x30/0xa0)
> > [  249.520023] [] (__alloc_from_contiguous) from [] 
> > (cma_allocator_alloc+0x40/0x48)
> > [  249.529173] [] (cma_allocator_alloc) from [] 
> > (__dma_alloc+0x1d4/0x2e8)
> > [  249.537455] [] (__dma_alloc) from [] 
> > (arm_dma_alloc+0x40/0x4c)
> > [  249.545047] [] (arm_dma_alloc) from [] 
> > (sh_eth_ring_init+0xec/0x1b8)
> > [  249.553160] [] (sh_eth_ring_init) from [] 
> > (sh_eth_open+0x88/0x1e0)
> > [  249.561086] [] (sh_eth_open) from [] 
> > (sh_eth_resume+0x7c/0xc0)
> > [  249.568678] [] (sh_eth_resume) from [] 
> > (dpm_run_callback+0x48/0xc8)
> > [  249.576702] [] (dpm_run_callback) from [] 
> > (device_resume+0x15c/0x1a0)
> > [  249.584898] [] (device_resume) from [] 
> > (dpm_resume+0xe4/0x244)
> > [  249.592485] [] (dpm_resume) from [] 
> > (dpm_resume_end+0xc/0x18)
> > [  249.599977] [] (dpm_resume_end) from [] 
> > (suspend_devices_and_enter+0x3c8/0x490)
> > [  249.609042] [] (suspend_devices_and_enter) from [] 
> > (pm_suspend+0x228/0x280)
> > [  249.617759] [] (pm_suspend) from [] 
> > (state_store+0xac/0xcc)
> > [  249.625089] [] (state_store) from [] 
> > (kernfs_fop_write+0x164/0x1a0)
> > [  249.633116] [] (kernfs_fop_write) from [] 
> > (__vfs_write+0x20/0x108)
> > [  249.641043] [] (__vfs_write) from [] 
> > (vfs_write+0xb8/0x144)
> > [  249.648373] [] (vfs_write) from [] 
> > (SyS_write+0x40/0x80)
> > [  249.655437] [] (SyS_write) from [] 
> > (ret_fast_syscall+0x0/0x34)
> > [...]
> > [  254.753928] Showing busy workqueues and worker pools:
> > [...]
> > [  254.854225] workqueue mm_percpu_wq: flags=0xc
> > [  254.858583]   pwq 2: cpus=1 node=0 flags=0x0 nice=0 active=0/0
> > [  254.864428] delayed: drain_local_pages_wq, vmstat_update
> > [  254.870111]   pwq 0: cpus=0 node=0 flags=0x0 nice=0 active=0/0
> > [  254.875957] delayed: drain_local_pages_wq BAR(1703), vmstat_update
> >
> > Tetsuo has properly noted that mm_percpu_wq is created as WQ_FREEZABLE
> > so it is frozen this early during resume so we are effectively deadlocked.
> > Fix this by dropping WQ_FREEZABLE when creating mm_percpu_wq. We really 
> > want to
> > have it operational all the time.
> >
> > Fixes: ce612879ddc7 ("mm: move pcp and lru-pcp draining into single wq")
> > Reported-by: Geert Uytterhoeven 
> > Debugged-by: Tetsuo Handa 

Re: Re: Re: "mm: move pcp and lru-pcp draining into single wq" broke resume from s2ram

[Geert Uytterhoeven]

Hi Michal, Tetsuo,

On Wed, Apr 19, 2017 at 9:57 AM, Michal Hocko  wrote:
> From f3c6e287042259d6ae9916f1ff66392c46ce2a3c Mon Sep 17 00:00:00 2001
> From: Michal Hocko 
> Date: Wed, 19 Apr 2017 09:52:46 +0200
> Subject: [PATCH] mm: make mm_percpu_wq non freezable
>
> Geert has reported a freeze during PM resume and some additional
> debugging has shown that the device_resume worker cannot make a forward
> progress because it waits for an event which is stuck waiting in
> drain_all_pages:
> [  243.691979] INFO: task kworker/u4:0:5 blocked for more than 120 seconds.
> [  243.698684]   Not tainted 
> 4.11.0-rc7-koelsch-00029-g005882e53d62f25d-dirty #3476
> [  243.706439] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables 
> this message.
> [  243.714276] kworker/u4:0D0 5  2 0x
> [  243.719780] Workqueue: events_unbound async_run_entry_fn
> [  243.725118] [] (__schedule) from [] 
> (schedule+0xb0/0xcc)
> [  243.732181] [] (schedule) from [] 
> (schedule_timeout+0x18/0x1f4)
> [  243.739840] [] (schedule_timeout) from [] 
> (wait_for_common+0x100/0x19c)
> [  243.748207] [] (wait_for_common) from [] 
> (dpm_wait_for_superior+0x14/0x5c)
> [  243.756836] [] (dpm_wait_for_superior) from [] 
> (device_resume+0x40/0x1a0)
> [  243.765380] [] (device_resume) from [] 
> (async_resume+0x18/0x44)
> [  243.773055] [] (async_resume) from [] 
> (async_run_entry_fn+0x44/0x114)
> [  243.781245] [] (async_run_entry_fn) from [] 
> (process_one_work+0x1cc/0x31c)
> [  243.789876] [] (process_one_work) from [] 
> (worker_thread+0x2b8/0x3f0)
> [  243.798080] [] (worker_thread) from [] 
> (kthread+0x120/0x140)
> [  243.805500] [] (kthread) from [] 
> (ret_from_fork+0x14/0x2c)
> [...]
> [  249.441198] bashD0  1703   1694 0x
> [  249.446702] [] (__schedule) from [] 
> (schedule+0xb0/0xcc)
> [  249.453764] [] (schedule) from [] 
> (schedule_timeout+0x18/0x1f4)
> [  249.461427] [] (schedule_timeout) from [] 
> (wait_for_common+0x100/0x19c)
> [  249.469797] [] (wait_for_common) from [] 
> (flush_work+0x128/0x158)
> [  249.477650] [] (flush_work) from [] 
> (drain_all_pages+0x198/0x1f0)
> [  249.485503] [] (drain_all_pages) from [] 
> (start_isolate_page_range+0xd8/0x1ac)
> [  249.494484] [] (start_isolate_page_range) from [] 
> (alloc_contig_range+0xc4/0x304)
> [  249.503724] [] (alloc_contig_range) from [] 
> (cma_alloc+0x134/0x1bc)
> [  249.511739] [] (cma_alloc) from [] 
> (__alloc_from_contiguous+0x30/0xa0)
> [  249.520023] [] (__alloc_from_contiguous) from [] 
> (cma_allocator_alloc+0x40/0x48)
> [  249.529173] [] (cma_allocator_alloc) from [] 
> (__dma_alloc+0x1d4/0x2e8)
> [  249.537455] [] (__dma_alloc) from [] 
> (arm_dma_alloc+0x40/0x4c)
> [  249.545047] [] (arm_dma_alloc) from [] 
> (sh_eth_ring_init+0xec/0x1b8)
> [  249.553160] [] (sh_eth_ring_init) from [] 
> (sh_eth_open+0x88/0x1e0)
> [  249.561086] [] (sh_eth_open) from [] 
> (sh_eth_resume+0x7c/0xc0)
> [  249.568678] [] (sh_eth_resume) from [] 
> (dpm_run_callback+0x48/0xc8)
> [  249.576702] [] (dpm_run_callback) from [] 
> (device_resume+0x15c/0x1a0)
> [  249.584898] [] (device_resume) from [] 
> (dpm_resume+0xe4/0x244)
> [  249.592485] [] (dpm_resume) from [] 
> (dpm_resume_end+0xc/0x18)
> [  249.599977] [] (dpm_resume_end) from [] 
> (suspend_devices_and_enter+0x3c8/0x490)
> [  249.609042] [] (suspend_devices_and_enter) from [] 
> (pm_suspend+0x228/0x280)
> [  249.617759] [] (pm_suspend) from [] 
> (state_store+0xac/0xcc)
> [  249.625089] [] (state_store) from [] 
> (kernfs_fop_write+0x164/0x1a0)
> [  249.633116] [] (kernfs_fop_write) from [] 
> (__vfs_write+0x20/0x108)
> [  249.641043] [] (__vfs_write) from [] 
> (vfs_write+0xb8/0x144)
> [  249.648373] [] (vfs_write) from [] 
> (SyS_write+0x40/0x80)
> [  249.655437] [] (SyS_write) from [] 
> (ret_fast_syscall+0x0/0x34)
> [...]
> [  254.753928] Showing busy workqueues and worker pools:
> [...]
> [  254.854225] workqueue mm_percpu_wq: flags=0xc
> [  254.858583]   pwq 2: cpus=1 node=0 flags=0x0 nice=0 active=0/0
> [  254.864428] delayed: drain_local_pages_wq, vmstat_update
> [  254.870111]   pwq 0: cpus=0 node=0 flags=0x0 nice=0 active=0/0
> [  254.875957] delayed: drain_local_pages_wq BAR(1703), vmstat_update
>
> Tetsuo has properly noted that mm_percpu_wq is created as WQ_FREEZABLE
> so it is frozen this early during resume so we are effectively deadlocked.
> Fix this by dropping WQ_FREEZABLE when creating mm_percpu_wq. We really want 
> to
> have it operational all the time.
>
> Fixes: ce612879ddc7 ("mm: move pcp and lru-pcp draining into single wq")
> Reported-by: Geert Uytterhoeven 
> Debugged-by: Tetsuo Handa 
> Signed-off-by: Michal Hocko 

Tested-by: Geert Uytterhoeven 

Thanks a lot to both of you!

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 

Re: Re: Re: "mm: move pcp and lru-pcp draining into single wq" broke resume from s2ram

[Michal Hocko]

On Wed 19-04-17 16:26:10, Tetsuo Handa wrote:
> > On Wed 19-04-17 14:41:30, Tetsuo Handa wrote:
> > [...]
> > > Somebody is waiting forever with cpu_hotplug.lock held?
> > 
> > Why would that matter for drain_all_pages? It doesn't use
> > get_online_cpus since a459eeb7b852 ("mm, page_alloc: do not depend on
> > cpu hotplug locks inside the allocator") while ce612879ddc7 ("mm: move
> > pcp and lru-pcp draining into single wq") was merged later.
> > 
> 
> Looking at ce612879ddc7 ("mm: move pcp and lru-pcp draining into single wq"),
> we merged "lru-add-drain" (!WQ_FREEZABLE && WQ_MEM_RECLAIM) workqueue and
> "vmstat" (WQ_FREEZABLE && WQ_MEM_RECLAIM) workqueue into
> "mm_percpu_wq" (WQ_FREEZABLE && WQ_MEM_RECLAIM) workqueue.
> 
> -   lru_add_drain_wq = alloc_workqueue("lru-add-drain", WQ_MEM_RECLAIM, 
> 0);
> -   vmstat_wq = alloc_workqueue("vmstat", WQ_FREEZABLE|WQ_MEM_RECLAIM, 0);
> +   mm_percpu_wq = alloc_workqueue("mm_percpu_wq",
> +  WQ_FREEZABLE|WQ_MEM_RECLAIM, 0);
> 
> That means "lru-add-drain" became freezable, doesn't it? And this problem
> occurs around resume operation where all freezable threads are frozen?
> Then, lru_add_drain_per_cpu() cannot be performed due to mm_percpu_wq frozen?

Ohh, right you are! Very well spotted. I have completely missed
WQ_FREEZABLE there. The following should work
---
>From f3c6e287042259d6ae9916f1ff66392c46ce2a3c Mon Sep 17 00:00:00 2001
From: Michal Hocko 
Date: Wed, 19 Apr 2017 09:52:46 +0200
Subject: [PATCH] mm: make mm_percpu_wq non freezable

Geert has reported a freeze during PM resume and some additional
debugging has shown that the device_resume worker cannot make a forward
progress because it waits for an event which is stuck waiting in
drain_all_pages:
[  243.691979] INFO: task kworker/u4:0:5 blocked for more than 120 seconds.
[  243.698684]   Not tainted 
4.11.0-rc7-koelsch-00029-g005882e53d62f25d-dirty #3476
[  243.706439] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this 
message.
[  243.714276] kworker/u4:0D0 5  2 0x
[  243.719780] Workqueue: events_unbound async_run_entry_fn
[  243.725118] [] (__schedule) from [] (schedule+0xb0/0xcc)
[  243.732181] [] (schedule) from [] 
(schedule_timeout+0x18/0x1f4)
[  243.739840] [] (schedule_timeout) from [] 
(wait_for_common+0x100/0x19c)
[  243.748207] [] (wait_for_common) from [] 
(dpm_wait_for_superior+0x14/0x5c)
[  243.756836] [] (dpm_wait_for_superior) from [] 
(device_resume+0x40/0x1a0)
[  243.765380] [] (device_resume) from [] 
(async_resume+0x18/0x44)
[  243.773055] [] (async_resume) from [] 
(async_run_entry_fn+0x44/0x114)
[  243.781245] [] (async_run_entry_fn) from [] 
(process_one_work+0x1cc/0x31c)
[  243.789876] [] (process_one_work) from [] 
(worker_thread+0x2b8/0x3f0)
[  243.798080] [] (worker_thread) from [] 
(kthread+0x120/0x140)
[  243.805500] [] (kthread) from [] 
(ret_from_fork+0x14/0x2c)
[...]
[  249.441198] bashD0  1703   1694 0x
[  249.446702] [] (__schedule) from [] (schedule+0xb0/0xcc)
[  249.453764] [] (schedule) from [] 
(schedule_timeout+0x18/0x1f4)
[  249.461427] [] (schedule_timeout) from [] 
(wait_for_common+0x100/0x19c)
[  249.469797] [] (wait_for_common) from [] 
(flush_work+0x128/0x158)
[  249.477650] [] (flush_work) from [] 
(drain_all_pages+0x198/0x1f0)
[  249.485503] [] (drain_all_pages) from [] 
(start_isolate_page_range+0xd8/0x1ac)
[  249.494484] [] (start_isolate_page_range) from [] 
(alloc_contig_range+0xc4/0x304)
[  249.503724] [] (alloc_contig_range) from [] 
(cma_alloc+0x134/0x1bc)
[  249.511739] [] (cma_alloc) from [] 
(__alloc_from_contiguous+0x30/0xa0)
[  249.520023] [] (__alloc_from_contiguous) from [] 
(cma_allocator_alloc+0x40/0x48)
[  249.529173] [] (cma_allocator_alloc) from [] 
(__dma_alloc+0x1d4/0x2e8)
[  249.537455] [] (__dma_alloc) from [] 
(arm_dma_alloc+0x40/0x4c)
[  249.545047] [] (arm_dma_alloc) from [] 
(sh_eth_ring_init+0xec/0x1b8)
[  249.553160] [] (sh_eth_ring_init) from [] 
(sh_eth_open+0x88/0x1e0)
[  249.561086] [] (sh_eth_open) from [] 
(sh_eth_resume+0x7c/0xc0)
[  249.568678] [] (sh_eth_resume) from [] 
(dpm_run_callback+0x48/0xc8)
[  249.576702] [] (dpm_run_callback) from [] 
(device_resume+0x15c/0x1a0)
[  249.584898] [] (device_resume) from [] 
(dpm_resume+0xe4/0x244)
[  249.592485] [] (dpm_resume) from [] 
(dpm_resume_end+0xc/0x18)
[  249.599977] [] (dpm_resume_end) from [] 
(suspend_devices_and_enter+0x3c8/0x490)
[  249.609042] [] (suspend_devices_and_enter) from [] 
(pm_suspend+0x228/0x280)
[  249.617759] [] (pm_suspend) from [] 
(state_store+0xac/0xcc)
[  249.625089] [] (state_store) from [] 
(kernfs_fop_write+0x164/0x1a0)
[  249.633116] [] (kernfs_fop_write) from [] 
(__vfs_write+0x20/0x108)
[  249.641043] [] (__vfs_write) from [] 
(vfs_write+0xb8/0x144)
[  249.648373] [] (vfs_write) from [] (SyS_write+0x40/0x80)
[  249.655437] [] (SyS_write) from [] 
(ret_fast_syscall+0x0/0x34)
[...]
[  254.753928] Showing 

Re: Re: "mm: move pcp and lru-pcp draining into single wq" broke resume from s2ram

[Michal Hocko]

On Wed 19-04-17 09:16:42, Geert Uytterhoeven wrote:
> Hi Tetsuo,
> 
> On Wed, Apr 19, 2017 at 7:41 AM, Tetsuo Handa
>  wrote:
[...]
> > Somebody is waiting forever with cpu_hotplug.lock held?
> > I think that full dmesg with SysRq-t output is appreciated.
> 
> As SysRq doesn't work with my serial console, I added calls to show_state()
> and show_workqueue_state() to check_hung_task().
> 
> Result with current linus/master attached.
[   47.165412] Enabling non-boot CPUs ...
[   47.205615] CPU1 is up
[   47.382002] PM: noirq resume of devices complete after 174.017 msecs
[   47.390181] PM: early resume of devices complete after 1.468 msecs

OK, so this is still the early resume path AFAIU which means that the
userspace is still in the fridge... Is it possible that new workers
cannot be spawned?

[  243.691979] INFO: task kworker/u4:0:5 blocked for more than 120 seconds.
[  243.698684]   Not tainted 
4.11.0-rc7-koelsch-00029-g005882e53d62f25d-dirty #3476
[  243.706439] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this 
message.
[  243.714276] kworker/u4:0D0 5  2 0x
[  243.719780] Workqueue: events_unbound async_run_entry_fn
[  243.725118] [] (__schedule) from [] (schedule+0xb0/0xcc)
[  243.732181] [] (schedule) from [] 
(schedule_timeout+0x18/0x1f4)
[  243.739840] [] (schedule_timeout) from [] 
(wait_for_common+0x100/0x19c)
[  243.748207] [] (wait_for_common) from [] 
(dpm_wait_for_superior+0x14/0x5c)
[  243.756836] [] (dpm_wait_for_superior) from [] 
(device_resume+0x40/0x1a0)
[  243.765380] [] (device_resume) from [] 
(async_resume+0x18/0x44)
[  243.773055] [] (async_resume) from [] 
(async_run_entry_fn+0x44/0x114)
[  243.781245] [] (async_run_entry_fn) from [] 
(process_one_work+0x1cc/0x31c)
[  243.789876] [] (process_one_work) from [] 
(worker_thread+0x2b8/0x3f0)
[  243.798080] [] (worker_thread) from [] 
(kthread+0x120/0x140)
[  243.805500] [] (kthread) from [] 
(ret_from_fork+0x14/0x2c)
[...]
[  249.441198] bashD0  1703   1694 0x
[  249.446702] [] (__schedule) from [] (schedule+0xb0/0xcc)
[  249.453764] [] (schedule) from [] 
(schedule_timeout+0x18/0x1f4)
[  249.461427] [] (schedule_timeout) from [] 
(wait_for_common+0x100/0x19c)
[  249.469797] [] (wait_for_common) from [] 
(flush_work+0x128/0x158)
[  249.477650] [] (flush_work) from [] 
(drain_all_pages+0x198/0x1f0)
[  249.485503] [] (drain_all_pages) from [] 
(start_isolate_page_range+0xd8/0x1ac)
[  249.494484] [] (start_isolate_page_range) from [] 
(alloc_contig_range+0xc4/0x304)
[  249.503724] [] (alloc_contig_range) from [] 
(cma_alloc+0x134/0x1bc)
[  249.511739] [] (cma_alloc) from [] 
(__alloc_from_contiguous+0x30/0xa0)
[  249.520023] [] (__alloc_from_contiguous) from [] 
(cma_allocator_alloc+0x40/0x48)
[  249.529173] [] (cma_allocator_alloc) from [] 
(__dma_alloc+0x1d4/0x2e8)
[  249.537455] [] (__dma_alloc) from [] 
(arm_dma_alloc+0x40/0x4c)
[  249.545047] [] (arm_dma_alloc) from [] 
(sh_eth_ring_init+0xec/0x1b8)
[  249.553160] [] (sh_eth_ring_init) from [] 
(sh_eth_open+0x88/0x1e0)
[  249.561086] [] (sh_eth_open) from [] 
(sh_eth_resume+0x7c/0xc0)
[  249.568678] [] (sh_eth_resume) from [] 
(dpm_run_callback+0x48/0xc8)
[  249.576702] [] (dpm_run_callback) from [] 
(device_resume+0x15c/0x1a0)
[  249.584898] [] (device_resume) from [] 
(dpm_resume+0xe4/0x244)
[  249.592485] [] (dpm_resume) from [] 
(dpm_resume_end+0xc/0x18)
[  249.599977] [] (dpm_resume_end) from [] 
(suspend_devices_and_enter+0x3c8/0x490)
[  249.609042] [] (suspend_devices_and_enter) from [] 
(pm_suspend+0x228/0x280)
[  249.617759] [] (pm_suspend) from [] 
(state_store+0xac/0xcc)
[  249.625089] [] (state_store) from [] 
(kernfs_fop_write+0x164/0x1a0)
[  249.633116] [] (kernfs_fop_write) from [] 
(__vfs_write+0x20/0x108)
[  249.641043] [] (__vfs_write) from [] 
(vfs_write+0xb8/0x144)
[  249.648373] [] (vfs_write) from [] (SyS_write+0x40/0x80)
[  249.655437] [] (SyS_write) from [] 
(ret_fast_syscall+0x0/0x34)
[...]
[  254.753928] Showing busy workqueues and worker pools:
[...]
[  254.854225] workqueue mm_percpu_wq: flags=0xc
[  254.858583]   pwq 2: cpus=1 node=0 flags=0x0 nice=0 active=0/0
[  254.864428] delayed: drain_local_pages_wq, vmstat_update
[  254.870111]   pwq 0: cpus=0 node=0 flags=0x0 nice=0 active=0/0
[  254.875957] delayed: drain_local_pages_wq BAR(1703), vmstat_update

I got lost in the indirection here. But is it possible that the
allocating context will wake up the workqeue context? Anyway the patch
you have bisected to doesn't change a lot in this scenario as I've said
before. If anything the change to using WQ for the draining rather than
smp_function_call would change the behavior. Does the below help by any
chance?
---
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 5fca73c7881a..a9a1ab7ea4c9 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -2417,6 +2417,14 @@ void drain_all_pages(struct zone *zone)
static cpumask_t cpus_with_pcps;
 
 

Re: [PATCH/RFT 1/2] ARM: dts: r8a7793: set maximum frequency for SDHI clocks

[Wolfram Sang]

On Tue, Apr 18, 2017 at 02:55:38PM +0900, Simon Horman wrote:
> Define the upper limit otherwise the driver cannot utilize max speeds.
> 
> Signed-off-by: Simon Horman 

Acked-by: Wolfram Sang 



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Description: PGP signature

Re: [PATCH/RFT 2/2] ARM: dts: gose: Enable UHS-I SDR-50 and SDR-104

[Wolfram Sang]

On Tue, Apr 18, 2017 at 02:55:39PM +0900, Simon Horman wrote:
> Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI{0,1,2}.
> And the sd-uhs-sdr104 property to SDHI0.
> 
> Signed-off-by: Simon Horman 

Acked-by: Wolfram Sang 



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Description: PGP signature

Re: [PATCH] i2c: rcar: fix resume by always initializing registers before transfer

[Kuninori Morimoto]

Hi Wolfram

> > diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
> > index 26f2ff2..db7f4d1 100644
> > --- a/drivers/i2c/busses/i2c-rcar.c
> > +++ b/drivers/i2c/busses/i2c-rcar.c
> > @@ -855,7 +855,6 @@ static int rcar_i2c_probe(struct platform_device *pdev)
> > priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
> >  
> > pm_runtime_enable(dev);
> > -   pm_runtime_get_sync(dev);
> > ret = rcar_i2c_clock_calculate(priv, _t);
> 
> rcar_i2c_clock_calculate() uses clk_get_rate, so clk must be active.

Ahh, OK, I understand.
Then,

Acked-by: Kuninori Morimoto 

Best regards
---
Kuninori Morimoto

Re: [PATCH/RFT v2] ARM: dts: silk: Enable UHS-I SDR-50

[Wolfram Sang]

On Tue, Apr 18, 2017 at 04:34:47PM +0900, Simon Horman wrote:
> Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI1.
> 
> Signed-off-by: Simon Horman 
> ---
> * Compile tested only; no access to silk board
> ---
>  arch/arm/boot/dts/r8a7794-silk.dts | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a7794-silk.dts 
> b/arch/arm/boot/dts/r8a7794-silk.dts
> index 4cb5278d104d..bb0c41c2f3ac 100644
> --- a/arch/arm/boot/dts/r8a7794-silk.dts
> +++ b/arch/arm/boot/dts/r8a7794-silk.dts
> @@ -196,6 +196,13 @@
>   sdhi1_pins: sd1 {
>   groups = "sdhi1_data4", "sdhi1_ctrl";
>   function = "sdhi1";
> + power-source = <3300>;
> + };
> +
> + sdhi1_pins_uhs: sd1_uhs {
> + groups = "sdhi1_data4", "sdhi1_ctrl";
> + function = "sdhi1";
> + power-source = <1800>;
>   };
>  
>   qspi_pins: qspi {
> @@ -343,6 +350,7 @@

No "pinctrl-1" for the uhs state?

>   vmmc-supply = <_sdhi1>;
>   vqmmc-supply = <_sdhi1>;
>   cd-gpios = < 14 GPIO_ACTIVE_LOW>;
> + sd-uhs-sdr50;
>   status = "okay";
>  };
>  
> -- 
> 2.7.0.rc3.207.g0ac5344


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Re: Re: Re: "mm: move pcp and lru-pcp draining into single wq" broke resume from s2ram

[Tetsuo Handa]

> On Wed 19-04-17 14:41:30, Tetsuo Handa wrote:
> [...]
> > Somebody is waiting forever with cpu_hotplug.lock held?
> 
> Why would that matter for drain_all_pages? It doesn't use
> get_online_cpus since a459eeb7b852 ("mm, page_alloc: do not depend on
> cpu hotplug locks inside the allocator") while ce612879ddc7 ("mm: move
> pcp and lru-pcp draining into single wq") was merged later.
> 

Looking at ce612879ddc7 ("mm: move pcp and lru-pcp draining into single wq"),
we merged "lru-add-drain" (!WQ_FREEZABLE && WQ_MEM_RECLAIM) workqueue and
"vmstat" (WQ_FREEZABLE && WQ_MEM_RECLAIM) workqueue into
"mm_percpu_wq" (WQ_FREEZABLE && WQ_MEM_RECLAIM) workqueue.

-   lru_add_drain_wq = alloc_workqueue("lru-add-drain", WQ_MEM_RECLAIM, 0);
-   vmstat_wq = alloc_workqueue("vmstat", WQ_FREEZABLE|WQ_MEM_RECLAIM, 0);
+   mm_percpu_wq = alloc_workqueue("mm_percpu_wq",
+  WQ_FREEZABLE|WQ_MEM_RECLAIM, 0);

That means "lru-add-drain" became freezable, doesn't it? And this problem
occurs around resume operation where all freezable threads are frozen?
Then, lru_add_drain_per_cpu() cannot be performed due to mm_percpu_wq frozen?

Re: [PATCH] PCI: Freeze PME scan before suspending devices

[Wolfram Sang]

On Tue, Apr 18, 2017 at 08:44:30PM +0200, Lukas Wunner wrote:
> Laurent Pinchart reported that the Renesas R-Car H2 Lager board
> (r8a7790) crashes during suspend tests.  Geert Uytterhoeven managed to
> reproduce the issue on an M2-W Koelsch board (r8a7791):
> 
> It occurs when the PME scan runs, once per second.  During PME scan, the
> PCI host bridge (rcar-pci) registers are accessed while its module clock
> has already been disabled, leading to the crash.

Cool! I stumbled over this while testing I2C suspend behaviour the last
days, and I can confirm that the crash is gone with this patch on my
Lager board. Thanks!

Tested-by: Wolfram Sang 



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Re: Re: "mm: move pcp and lru-pcp draining into single wq" broke resume from s2ram

[Geert Uytterhoeven]

Hi Tetsuo,

On Wed, Apr 19, 2017 at 7:41 AM, Tetsuo Handa
 wrote:
> Geert Uytterhoeven wrote:
>> 8 locks held by s2ram/1899:
>>  #0:  (sb_writers#7){.+.+.+}, at: [] vfs_write+0xa8/0x15c
>>  #1:  (>mutex){+.+.+.}, at: [] 
>> kernfs_fop_write+0xf0/0x194
>>  #2:  (s_active#48){.+.+.+}, at: [] 
>> kernfs_fop_write+0xf8/0x194
>>  #3:  (pm_mutex){+.+.+.}, at: [] pm_suspend+0x16c/0xabc
>>  #4:  (>mutex){..}, at: [] 
>> device_resume+0x58/0x190
>>  #5:  (cma_mutex){+.+...}, at: [] cma_alloc+0x150/0x374
>>  #6:  (lock){+.+...}, at: [] lru_add_drain_all+0x4c/0x1b4
>>  #7:  (cpu_hotplug.dep_map){++}, at: [] 
>> get_online_cpus+0x3c/0x9c
>
> I think this situation suggests that

[...]

> Somebody is waiting forever with cpu_hotplug.lock held?
> I think that full dmesg with SysRq-t output is appreciated.

As SysRq doesn't work with my serial console, I added calls to show_state()
and show_workqueue_state() to check_hung_task().

Result with current linus/master attached.

Thanks!

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds


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Re: Re: "mm: move pcp and lru-pcp draining into single wq" broke resume from s2ram

[Michal Hocko]

On Wed 19-04-17 14:41:30, Tetsuo Handa wrote:
[...]
> Somebody is waiting forever with cpu_hotplug.lock held?

Why would that matter for drain_all_pages? It doesn't use
get_online_cpus since a459eeb7b852 ("mm, page_alloc: do not depend on
cpu hotplug locks inside the allocator") while ce612879ddc7 ("mm: move
pcp and lru-pcp draining into single wq") was merged later.

-- 
Michal Hocko
SUSE Labs

Re: [PATCH] i2c: rcar: fix resume by always initializing registers before transfer

[Wolfram Sang]

Morimoto-san,

> I understand about I2C slave / multi-master case of pm_runtime_get/put.
> But in probe case (after rcar_i2c_init() move), we can't do like below ?
> this is more clear code for me.
> 
> -
> diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
> index 26f2ff2..db7f4d1 100644
> --- a/drivers/i2c/busses/i2c-rcar.c
> +++ b/drivers/i2c/busses/i2c-rcar.c
> @@ -855,7 +855,6 @@ static int rcar_i2c_probe(struct platform_device *pdev)
>   priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
>  
>   pm_runtime_enable(dev);
> - pm_runtime_get_sync(dev);
>   ret = rcar_i2c_clock_calculate(priv, _t);

rcar_i2c_clock_calculate() uses clk_get_rate, so clk must be active.

Regards,

   Wolfram



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