Re: [PATCH v6 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi

[Chen-Yu Tsai]

On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
 wrote:
> The R_CPUCFG is a collection of registers needed for SMP bringup
> on clusters and cluster's reset.
> For the moment, documentation about this register is found in
> Allwinner's code only.
>
> Signed-off-by: Mylène Josserand 

Reviewed-by: Chen-Yu Tsai 

Re: [PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file

[Chen-Yu Tsai]

On Tue, Apr 17, 2018 at 5:50 AM, Mylène Josserand
 wrote:
> Move the assembly code for cluster cache enabling and resuming
> into an assembly file instead of having it directly in C code.
>
> Remove the CFLAGS because we are using the ARM directive "arch"
> instead.
>
> Signed-off-by: Mylène Josserand 
> ---
>  arch/arm/mach-sunxi/Makefile  |  4 +--
>  arch/arm/mach-sunxi/headsmp.S | 80 +
>  arch/arm/mach-sunxi/mc_smp.c  | 82 
> +++
>  3 files changed, 85 insertions(+), 81 deletions(-)
>  create mode 100644 arch/arm/mach-sunxi/headsmp.S

I'm still not convinced about this whole "move ASM to separate
file" thing, especially now that you aren't actually adding any
sunxi-specific ASM code beyond a simple function call.

Could you drop this for now?

ChenYu

Re: [PATCH v6 00/11] Sunxi: Add SMP support on A83T

[Ondřej Jirman]

Hello Mylène,

Please also add this:

diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ce53ceaf4cc5..d9c8ecf88ec6 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -51,7 +51,7 @@ config MACH_SUN9I
 config ARCH_SUNXI_MC_SMP
bool
depends on SMP
-   default MACH_SUN9I
+ default MACH_SUN9I || MACH_SUN8I
select ARM_CCI400_PORT_CTRL
select ARM_CPU_SUSPEND

Because otherwise when I'm building kernel just for sun8i and I don't have sun9i
enabled, this new SMP code for A83T (which is sun8i) will not be built.

thank you,
  Ondrej

On Mon, Apr 16, 2018 at 11:50:21PM +0200, Mylène Josserand wrote:
> Hello everyone,
> 
> This is a V6 of my series that adds SMP support for Allwinner sun8i-a83t.
> Based on sunxi's tree, sunxi/for-next branch.
> Depends on a patch from Doug Berger that allows to include the "cpu-type"
> header on assembly files:
> 6c7dd080ba4b ("ARM: Allow this header to be included by assembly files")
> 
> This new series refactors the shmobile code to use the function introduced
> in this series: "secure_cntvoff_init".
> Geert Uytterhoeven and Simon Horman, could you review and test this series
> on Renesas boards? Thank you very much!
> 
> If you have any remarks/questions, let me know.
> Thank you in advance,
> Mylène
> 
> Changes since v5:
> - Remove my patch 01 and use the patch of Doug Berger to be able to
> include the cpu-type header on assembly files.
> - Rename smp_init_cntvoff function into secure_cntvoff_init according
> to Marc Zyngier's review.
> - According to Chen-Yu and Maxime's reviews, remove the patch that was
> moving structures. Instead of using an index to retrieve which
> architecture we are having, use a global variable.
> - Merge the 2 patches that move assembly code from C to assembly file.
> - Use a sun8i field instead of sun9i to know on which architecture we
> are using because many modifications/additions of the code are for
> sun8i-a83t.
> - Rework the patch "add is_sun8i field" to add only this field in this
> patch. The part of the patch that was starting to handle the differences
> between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
> support of sun8i-a83t.
> - Add a new patch that refactor the shmobile code to use the new function
> secure_cntvoff_init introduced in this series.
> 
> Changes since v4:
> - Rebased my series according to new Chen-Yu series:
>"ARM: sunxi: Clean and improvements for multi-cluster SMP"
>https://lkml.org/lkml/2018/3/8/886
> - Updated my series according to Marc Zyngier's reviews to add CNTVOFF
> initialization's function into ARM's common part. Thanks to that, other
> platforms such as Renesa can use this function.
> - For boot CPU, create a new machine to handle the CNTVOFF initialization
> using "init_early" callback.
> Changes since v3:
> - Take into account Maxime's reviews:
>   - split the first patch into 4 new patches: add sun9i device tree
>   parsing, rename some variables, add a83t support and finally,
>   add hotplug support.
>   - Move the code of previous patch 07 (to disable CPU0 disabling)
>   into hotplug support patch (see patch 04)
>   - Remove the patch that added PRCM register because it is already
>   available. Because of that, update the device tree parsing to use
>   "sun8i-a83t-r-ccu".
>   - Use a variable to know which SoC we currently have
> - Take into account Chen-Yu's reviews: create two iounmap functions
> to release the resources of the device tree parsing.
> - Take into account Marc's review: Update the code to initialize CNTVOFF
> register. As there is already assembly code in the driver, I decided
> to create an assembly file not to mix assembly and C code.
> For that, I create 3 new patches: move the current assembly code that
> handles the cluster cache enabling into a file, move the cpu_resume entry
> in this file and finally, add a new assembly entry to initialize the timer
> offset for boot CPU and secondary CPUs.
> 
> Changes since v2:
> - Rebased my modifications according to new Chen Yu's patch series
> that adds SMP support for sun9i-a80 (without MCPM).
> - Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
> and PRCM registers for more visibility.
> - The hotplug of CPU0 is currently not working (even after trying what
> Allwinner's code is doing) so remove the possibility of disabling
> this CPU. Created a new patch for it.
> 
> Changes since v1:
> - Add Chen Yu's patch in my series (see path 01)
> - Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
> Create two functions to separate the DT parsing of sun9i-a80 and
> sun8i-a83t.
> - Thanks to Maxime's review: order device tree's nodes according
> to physical addresses, remove 

Re: [PATCH v13 2/2] rcar-csi2: add Renesas R-Car MIPI CSI-2 receiver driver

[Niklas Söderlund]

Hi Jacopo,

On 2018-04-16 01:16:35 +0200, Niklas Söderlund wrote:

[snip]

> > > +
> > > + /* Set frequency range if we have it */
> > > + if (priv->info->csi0clkfreqrange)
> > > + rcar_csi2_write(priv, CSI0CLKFCPR_REG,
> > > + CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
> > > +
> > > + rcar_csi2_write(priv, PHYCNT_REG, phycnt);
> > > + rcar_csi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
> > > + LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
> > > + rcar_csi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
> > > + rcar_csi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ |
> > > + PHYCNT_RSTZ);
> > 
> > Nit: from tables 25.[17-20] it seems to me you do not have to re-issue
> > PHYCNT_SHUTDOWNZ when writing PHYCNT_RSTZ to PHYCNT_REG.
> 
> You are correct, I miss read ' Here, the ENABLE_0 to ENABLE_3 and
> ENABLECLK values set above should be retained' as all previous PHYCNT 
> bits should be retained not just the ones explicitly listed. I will give 
> this a test and if it still works I will remove it for the next version.

This change breaks capture and LP-11 is never detected. So I will 
continue to retain the PHYCNT_SHUTDOWNZ here.

-- 
Regards,
Niklas Söderlund

[PATCH v6 00/11] Sunxi: Add SMP support on A83T

[Mylène Josserand]

Hello everyone,

This is a V6 of my series that adds SMP support for Allwinner sun8i-a83t.
Based on sunxi's tree, sunxi/for-next branch.
Depends on a patch from Doug Berger that allows to include the "cpu-type"
header on assembly files:
6c7dd080ba4b ("ARM: Allow this header to be included by assembly files")

This new series refactors the shmobile code to use the function introduced
in this series: "secure_cntvoff_init".
Geert Uytterhoeven and Simon Horman, could you review and test this series
on Renesas boards? Thank you very much!

If you have any remarks/questions, let me know.
Thank you in advance,
Mylène

Changes since v5:
- Remove my patch 01 and use the patch of Doug Berger to be able to
include the cpu-type header on assembly files.
- Rename smp_init_cntvoff function into secure_cntvoff_init according
to Marc Zyngier's review.
- According to Chen-Yu and Maxime's reviews, remove the patch that was
moving structures. Instead of using an index to retrieve which
architecture we are having, use a global variable.
- Merge the 2 patches that move assembly code from C to assembly file.
- Use a sun8i field instead of sun9i to know on which architecture we
are using because many modifications/additions of the code are for
sun8i-a83t.
- Rework the patch "add is_sun8i field" to add only this field in this
patch. The part of the patch that was starting to handle the differences
between sun8i-a83t and sun9i-a80 is merged in the patch that adds the
support of sun8i-a83t.
- Add a new patch that refactor the shmobile code to use the new function
secure_cntvoff_init introduced in this series.

Changes since v4:
- Rebased my series according to new Chen-Yu series:
   "ARM: sunxi: Clean and improvements for multi-cluster SMP"
   https://lkml.org/lkml/2018/3/8/886
- Updated my series according to Marc Zyngier's reviews to add CNTVOFF
initialization's function into ARM's common part. Thanks to that, other
platforms such as Renesa can use this function.
- For boot CPU, create a new machine to handle the CNTVOFF initialization
using "init_early" callback.
Changes since v3:
- Take into account Maxime's reviews:
- split the first patch into 4 new patches: add sun9i device tree
parsing, rename some variables, add a83t support and finally,
add hotplug support.
- Move the code of previous patch 07 (to disable CPU0 disabling)
into hotplug support patch (see patch 04)
- Remove the patch that added PRCM register because it is already
available. Because of that, update the device tree parsing to use
"sun8i-a83t-r-ccu".
- Use a variable to know which SoC we currently have
- Take into account Chen-Yu's reviews: create two iounmap functions
to release the resources of the device tree parsing.
- Take into account Marc's review: Update the code to initialize CNTVOFF
register. As there is already assembly code in the driver, I decided
to create an assembly file not to mix assembly and C code.
For that, I create 3 new patches: move the current assembly code that
handles the cluster cache enabling into a file, move the cpu_resume entry
in this file and finally, add a new assembly entry to initialize the timer
offset for boot CPU and secondary CPUs.

Changes since v2:
- Rebased my modifications according to new Chen Yu's patch series
that adds SMP support for sun9i-a80 (without MCPM).
- Split the device-tree patches into 3 patches for CPUCFG, R_CPUCFG
and PRCM registers for more visibility.
- The hotplug of CPU0 is currently not working (even after trying what
Allwinner's code is doing) so remove the possibility of disabling
this CPU. Created a new patch for it.

Changes since v1:
- Add Chen Yu's patch in my series (see path 01)
- Add new compatibles for prcm and cpucfg registers for sun8i-a83t.
Create two functions to separate the DT parsing of sun9i-a80 and
sun8i-a83t.
- Thanks to Maxime's review: order device tree's nodes according
to physical addresses, remove unused label and fix registers' sizes.
Update the commit log and commit title of my last patch (see
patch 05).

Mylène Josserand (11):
  ARM: sunxi: smp: Move assembly code into a file
  ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi
  ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi
  ARM: dts: sun8i: a83t: Add CCI-400 node
  ARM: smp: Add initialization of CNTVOFF
  ARM: sunxi: Add initialization of CNTVOFF
  ARM: sun9i: smp: Rename clusters's power-off
  ARM: sun9i: smp: Add is_sun8i field
  ARM: sun8i: smp: Add support for A83T
  ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
  ARM: shmobile: Convert file to use cntvoff

 arch/arm/boot/dts/sun8i-a83t.dtsi|  59 
 arch/arm/common/Makefile |   1 +
 arch/arm/common/secure_cntvoff.S | 

[PATCH v6 02/11] ARM: dts: sun8i: Add CPUCFG device node for A83T dtsi

[Mylène Josserand]

As we found in sun9i-a80, CPUCFG is a collection of registers that are
mapped to the SoC's signals from each individual processor core and
associated peripherals.

These registers are used for SMP bringup and CPU hotplugging.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 568307639be8..32992afa0b12 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -349,6 +349,11 @@
};
};
 
+   cpucfg@170 {
+   compatible = "allwinner,sun8i-a83t-cpucfg";
+   reg = <0x0170 0x400>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v6 01/11] ARM: sunxi: smp: Move assembly code into a file

[Mylène Josserand]

Move the assembly code for cluster cache enabling and resuming
into an assembly file instead of having it directly in C code.

Remove the CFLAGS because we are using the ARM directive "arch"
instead.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/Makefile  |  4 +--
 arch/arm/mach-sunxi/headsmp.S | 80 +
 arch/arm/mach-sunxi/mc_smp.c  | 82 +++
 3 files changed, 85 insertions(+), 81 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/headsmp.S

diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7de9cc286d53..7f45071ae74a 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -1,5 +1,3 @@
-CFLAGS_mc_smp.o+= -march=armv7-a
-
 obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
-obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o
+obj-$(CONFIG_ARCH_SUNXI_MC_SMP) += mc_smp.o headsmp.o
 obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
new file mode 100644
index ..37dc772701f3
--- /dev/null
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 Chen-Yu Tsai
+ * Copyright (c) 2018 Bootlin
+ *
+ * Chen-Yu Tsai 
+ * Mylène Josserand 
+ *
+ * SMP support for sunxi based systems with Cortex A7/A15
+ *
+ */
+
+#include 
+#include 
+#include 
+
+ENTRY(sunxi_mc_smp_cluster_cache_enable)
+   .arch   armv7-a
+   /*
+* Enable cluster-level coherency, in preparation for turning on the 
MMU.
+*
+* Also enable regional clock gating and L2 data latency settings for
+* Cortex-A15. These settings are from the vendor kernel.
+*/
+   mrc p15, 0, r1, c0, c0, 0
+   movwr2, #(ARM_CPU_PART_MASK & 0x)
+   movtr2, #(ARM_CPU_PART_MASK >> 16)
+   and r1, r1, r2
+   movwr2, #(ARM_CPU_PART_CORTEX_A15 & 0x)
+   movtr2, #(ARM_CPU_PART_CORTEX_A15 >> 16)
+   cmp r1, r2
+   bne not_a15
+
+   /* The following is Cortex-A15 specific */
+
+   /* ACTLR2: Enable CPU regional clock gates */
+   mrc p15, 1, r1, c15, c0, 4
+   orr r1, r1, #(0x1 << 31)
+   mcr p15, 1, r1, c15, c0, 4
+
+   /* L2ACTLR */
+   mrc p15, 1, r1, c15, c0, 0
+   /* Enable L2, GIC, and Timer regional clock gates */
+   orr r1, r1, #(0x1 << 26)
+   /* Disable clean/evict from being pushed to external */
+   orr r1, r1, #(0x1<<3)
+   mcr p15, 1, r1, c15, c0, 0
+
+   /* L2CTRL: L2 data RAM latency */
+   mrc p15, 1, r1, c9, c0, 2
+   bic r1, r1, #(0x7 << 0)
+   orr r1, r1, #(0x3 << 0)
+   mcr p15, 1, r1, c9, c0, 2
+
+   /* End of Cortex-A15 specific setup */
+   not_a15:
+
+   /* Get value of sunxi_mc_smp_first_comer */
+   adr r1, first
+   ldr r0, [r1]
+   ldr r0, [r1, r0]
+
+   /* Skip cci_enable_port_for_self if not first comer */
+   cmp r0, #0
+   bxeqlr
+   b   cci_enable_port_for_self
+
+   .align 2
+   first: .word sunxi_mc_smp_first_comer - .
+ENDPROC(sunxi_mc_smp_cluster_cache_enable)
+
+ENTRY(sunxi_mc_smp_secondary_startup)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   secondary_startup
+ENDPROC(sunxi_mc_smp_secondary_startup)
+
+ENTRY(sunxi_mc_smp_resume)
+   bl  sunxi_mc_smp_cluster_cache_enable
+   b   cpu_resume
+ENDPROC(sunxi_mc_smp_resume)
diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index c0246ec54a0a..727968d6a3e5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -72,6 +72,9 @@ static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
 
+extern void sunxi_mc_smp_secondary_startup(void);
+extern void sunxi_mc_smp_resume(void);
+
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
struct device_node *node;
@@ -300,74 +303,7 @@ static void sunxi_cluster_cache_disable_without_axi(void)
 }
 
 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
-static int sunxi_mc_smp_first_comer;
-
-/*
- * Enable cluster-level coherency, in preparation for turning on the MMU.
- *
- * Also enable regional clock gating and L2 data latency settings for
- * Cortex-A15. These settings are from the vendor kernel.
- */
-static void __naked sunxi_mc_smp_cluster_cache_enable(void)
-{
-   asm volatile (
-   "mrcp15, 0, r1, c0, c0, 0\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_MASK & 0x) "\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_MASK >> 16) "\n"
-   "andr1, r1, r2\n"
-   "movw   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 & 0x) 
"\n"
-   "movt   r2, #" __stringify(ARM_CPU_PART_CORTEX_A15 >> 16) "\n"
-

[PATCH v6 03/11] ARM: dts: sun8i: Add R_CPUCFG device node for the A83T dtsi

[Mylène Josserand]

The R_CPUCFG is a collection of registers needed for SMP bringup
on clusters and cluster's reset.
For the moment, documentation about this register is found in
Allwinner's code only.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 32992afa0b12..7974eaba57a7 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -933,6 +933,11 @@
#reset-cells = <1>;
};
 
+   r_cpucfg@1f01c00 {
+   compatible = "allwinner,sun8i-a83t-r-cpucfg";
+   reg = <0x1f01c00 0x400>;
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

[PATCH v6 05/11] ARM: smp: Add initialization of CNTVOFF

[Mylène Josserand]

The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: Mylène Josserand 
---
 arch/arm/common/Makefile  |  1 +
 arch/arm/common/secure_cntvoff.S  | 31 +++
 arch/arm/include/asm/secure_cntvoff.h |  8 
 3 files changed, 40 insertions(+)
 create mode 100644 arch/arm/common/secure_cntvoff.S
 create mode 100644 arch/arm/include/asm/secure_cntvoff.h

diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 70b4a14ed993..1e9f7af8f70f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE)   += dmabounce.o
 obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
 obj-$(CONFIG_SHARP_PARAM)  += sharpsl_param.o
 obj-$(CONFIG_SHARP_SCOOP)  += scoop.o
+obj-$(CONFIG_SMP)  += secure_cntvoff.o
 obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o
 obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o 
vlock.o
 CFLAGS_REMOVE_mcpm_entry.o = -pg
diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
new file mode 100644
index ..68a4a8344319
--- /dev/null
+++ b/arch/arm/common/secure_cntvoff.S
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * Initialization of CNTVOFF register from secure mode
+ *
+ */
+
+#include 
+#include 
+
+ENTRY(secure_cntvoff_init)
+   .arch   armv7-a
+   /*
+* CNTVOFF has to be initialized either from non-secure Hypervisor
+* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
+* then it should be handled by the secure code
+*/
+   cps #MON_MODE
+   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
+   orr r0, r1, #1
+   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
+   isb
+   mov r0, #0
+   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
+   isb
+   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
+   isb
+   cps #SVC_MODE
+   ret lr
+ENDPROC(secure_cntvoff_init)
diff --git a/arch/arm/include/asm/secure_cntvoff.h 
b/arch/arm/include/asm/secure_cntvoff.h
new file mode 100644
index ..1f93aee1f630
--- /dev/null
+++ b/arch/arm/include/asm/secure_cntvoff.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASMARM_ARCH_CNTVOFF_H
+#define __ASMARM_ARCH_CNTVOFF_H
+
+extern void secure_cntvoff_init(void);
+
+#endif
-- 
2.11.0

[PATCH v6 04/11] ARM: dts: sun8i: a83t: Add CCI-400 node

[Mylène Josserand]

Add CCI-400 node and control-port on CPUs needed by SMP bringup.

Signed-off-by: Mylène Josserand 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7974eaba57a7..42539267e329 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -66,6 +66,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <0>;
};
 
@@ -73,6 +74,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <1>;
};
 
@@ -80,6 +82,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <2>;
};
 
@@ -87,6 +90,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control0>;
reg = <3>;
};
 
@@ -96,6 +100,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x100>;
};
 
@@ -103,6 +108,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x101>;
};
 
@@ -110,6 +116,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x102>;
};
 
@@ -117,6 +124,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
operating-points-v2 = <_opp_table>;
+   cci-control-port = <_control1>;
reg = <0x103>;
};
};
@@ -354,6 +362,39 @@
reg = <0x0170 0x400>;
};
 
+   cci@179 {
+   compatible = "arm,cci-400";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   reg = <0x0179 0x1>;
+   ranges = <0x0 0x0179 0x1>;
+
+   cci_control0: slave-if@4000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x4000 0x1000>;
+   };
+
+   cci_control1: slave-if@5000 {
+   compatible = "arm,cci-400-ctrl-if";
+   interface-type = "ace";
+   reg = <0x5000 0x1000>;
+   };
+
+   pmu@9000 {
+   compatible = "arm,cci-400-pmu,r1";
+   reg = <0x9000 0x5000>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+;
+   };
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
-- 
2.11.0

[PATCH v6 06/11] ARM: sunxi: Add initialization of CNTVOFF

[Mylène Josserand]

Add the initialization of CNTVOFF for sun8i-a83t.

For boot CPU, create a new machine that handles this
function's call in an "init_early" callback. We need to initialize
CNTVOFF before the arch timer's initialization otherwise, it will
not be taken into account and fails to boot correctly.
Because of that, this function can't be called in SMP's early_initcall
function which is called after timer's init.

For secondary CPUs, add this function into secondary_startup
assembly entry.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/headsmp.S |  1 +
 arch/arm/mach-sunxi/sunxi.c   | 20 +++-
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
index 37dc772701f3..32d76be98541 100644
--- a/arch/arm/mach-sunxi/headsmp.S
+++ b/arch/arm/mach-sunxi/headsmp.S
@@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
 
 ENTRY(sunxi_mc_smp_secondary_startup)
bl  sunxi_mc_smp_cluster_cache_enable
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(sunxi_mc_smp_secondary_startup)
 
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 5e9602ce1573..ddc439f6269b 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -16,6 +16,7 @@
 #include 
 
 #include 
+#include 
 
 static const char * const sunxi_board_dt_compat[] = {
"allwinner,sun4i-a10",
@@ -62,7 +63,6 @@ MACHINE_END
 static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
-   "allwinner,sun8i-a83t",
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-r40",
@@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
.dt_compat  = sun8i_board_dt_compat,
 MACHINE_END
 
+void __init sun8i_cntvoff_init(void)
+{
+#ifdef CONFIG_SMP
+   secure_cntvoff_init();
+#endif
+}
+
+static const char * const sun8i_cntvoff_board_dt_compat[] = {
+   "allwinner,sun8i-a83t",
+   NULL,
+};
+
+DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")
+   .init_early = sun8i_cntvoff_init,
+   .init_time  = sun6i_timer_init,
+   .dt_compat  = sun8i_cntvoff_board_dt_compat,
+MACHINE_END
+
 static const char * const sun9i_board_dt_compat[] = {
"allwinner,sun9i-a80",
NULL,
-- 
2.11.0

[PATCH v6 07/11] ARM: sun9i: smp: Rename clusters's power-off

[Mylène Josserand]

To prepare the support for sun8i-a83t, rename the variable name
that handles the power-off of clusters because it is different from
sun9i-a80 to sun8i-a83t.

The power off register for clusters are different from a80 and a83t.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai 
---
 arch/arm/mach-sunxi/mc_smp.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 727968d6a3e5..03f021d0c73e 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -60,7 +60,7 @@
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
-#define PRCM_PWROFF_GATING_REG_CLUSTER BIT(4)
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
@@ -255,7 +255,7 @@ static int sunxi_cluster_powerup(unsigned int cluster)
 
/* clear cluster power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
@@ -452,7 +452,7 @@ static int sunxi_cluster_powerdown(unsigned int cluster)
/* gate cluster power */
pr_debug("%s: gate cluster power\n", __func__);
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
-   reg |= PRCM_PWROFF_GATING_REG_CLUSTER;
+   reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
-- 
2.11.0

[PATCH v6 08/11] ARM: sun9i: smp: Add is_sun8i field

[Mylène Josserand]

To prepare the support of sun8i-a83t, add a field in the smp_data
structure to know if we are on sun9i-a80 or sun8i-a83t.

Add also a global variable to retrieve which architecture we are
having.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/mc_smp.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 03f021d0c73e..9d57ea27dacc 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
+static int is_sun8i;
 
 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
 {
@@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
 struct sunxi_mc_smp_data {
const char *enable_method;
int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
+   int is_sun8i;
 };
 
 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
@@ -664,6 +666,7 @@ static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] 
__initconst = {
{
.enable_method  = "allwinner,sun9i-a80-smp",
.get_smp_nodes  = sun9i_a80_get_smp_nodes,
+   .is_sun8i   = false,
},
 };
 
@@ -697,6 +700,8 @@ static int __init sunxi_mc_smp_init(void)
break;
}
 
+   is_sun8i = sunxi_mc_smp_data[i].is_sun8i;
+
of_node_put(node);
if (ret)
return -ENODEV;
-- 
2.11.0

[PATCH v6 11/11] ARM: shmobile: Convert file to use cntvoff

[Mylène Josserand]

Now that a common function is available for CNTVOFF's
initialization, let's convert shmobile-apmu code to use
this function.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-shmobile/common.h  |  1 -
 arch/arm/mach-shmobile/headsmp-apmu.S| 22 +-
 arch/arm/mach-shmobile/setup-rcar-gen2.c |  3 ++-
 3 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index a8fa4f7e1f60..b77ad5b56895 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -2,7 +2,6 @@
 #ifndef __ARCH_MACH_COMMON_H
 #define __ARCH_MACH_COMMON_H
 
-extern void shmobile_init_cntvoff(void);
 extern void shmobile_init_delay(void);
 extern void shmobile_boot_vector(void);
 extern unsigned long shmobile_boot_fn;
diff --git a/arch/arm/mach-shmobile/headsmp-apmu.S 
b/arch/arm/mach-shmobile/headsmp-apmu.S
index 5672b5849401..d49ab194766a 100644
--- a/arch/arm/mach-shmobile/headsmp-apmu.S
+++ b/arch/arm/mach-shmobile/headsmp-apmu.S
@@ -11,29 +11,9 @@
 #include 
 #include 
 
-ENTRY(shmobile_init_cntvoff)
-   /*
-* CNTVOFF has to be initialized either from non-secure Hypervisor
-* mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
-* then it should be handled by the secure code
-*/
-   cps #MON_MODE
-   mrc p15, 0, r1, c1, c1, 0   /* Get Secure Config */
-   orr r0, r1, #1
-   mcr p15, 0, r0, c1, c1, 0   /* Set Non Secure bit */
-   instr_sync
-   mov r0, #0
-   mcrrp15, 4, r0, r0, c14 /* CNTVOFF = 0 */
-   instr_sync
-   mcr p15, 0, r1, c1, c1, 0   /* Set Secure bit */
-   instr_sync
-   cps #SVC_MODE
-   ret lr
-ENDPROC(shmobile_init_cntvoff)
-
 #ifdef CONFIG_SMP
 ENTRY(shmobile_boot_apmu)
-   bl  shmobile_init_cntvoff
+   bl  secure_cntvoff_init
b   secondary_startup
 ENDPROC(shmobile_boot_apmu)
 #endif
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c 
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 5561dbed7a33..4a881026d740 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "common.h"
 #include "rcar-gen2.h"
 
@@ -70,7 +71,7 @@ void __init rcar_gen2_timer_init(void)
void __iomem *base;
u32 freq;
 
-   shmobile_init_cntvoff();
+   secure_cntvoff_init();
 
if (of_machine_is_compatible("renesas,r8a7745") ||
of_machine_is_compatible("renesas,r8a7792") ||
-- 
2.11.0

[PATCH v6 10/11] ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC

[Mylène Josserand]

Add the use of enable-method property for SMP support which allows
to handle the SMP support for this specific SoC.

This commit adds enable-method properties to all CPU nodes.

Signed-off-by: Mylène Josserand 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 42539267e329..c9b60047b0b8 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -67,6 +67,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
};
 
@@ -75,6 +76,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
};
 
@@ -83,6 +85,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
};
 
@@ -91,6 +94,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control0>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
};
 
@@ -101,6 +105,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
};
 
@@ -109,6 +114,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
};
 
@@ -117,6 +123,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
};
 
@@ -125,6 +132,7 @@
device_type = "cpu";
operating-points-v2 = <_opp_table>;
cci-control-port = <_control1>;
+   enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
};
};
-- 
2.11.0

[PATCH v6 09/11] ARM: sun8i: smp: Add support for A83T

[Mylène Josserand]

Add the support for A83T.

A83T SoC has an additional register than A80 to handle CPU configurations:
R_CPUS_CFG. Information about the register comes from Allwinner's BSP
driver.
An important difference is the Power Off Gating register for clusters
which is BIT(4) in case of SUN9I-A80 and BIT(0) in case of SUN8I-A83T.
There is also a bit swap between sun8i-a83t and sun9i-a80 that must be
handled.

Signed-off-by: Mylène Josserand 
---
 arch/arm/mach-sunxi/mc_smp.c | 151 ++-
 1 file changed, 136 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
index 9d57ea27dacc..1ed2ab3a13b5 100644
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -55,22 +55,31 @@
 #define CPUCFG_CX_RST_CTRL_L2_RST  BIT(8)
 #define CPUCFG_CX_RST_CTRL_CX_RST(n)   BIT(4 + (n))
 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
+#define CPUCFG_CX_RST_CTRL_CORE_RST_ALL(0xf << 0)
 
 #define PRCM_CPU_PO_RST_CTRL(c)(0x4 + 0x4 * (c))
 #define PRCM_CPU_PO_RST_CTRL_CORE(n)   BIT(n)
 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL  0xf
 #define PRCM_PWROFF_GATING_REG(c)  (0x100 + 0x4 * (c))
+/* The power off register for clusters are different from a80 and a83t */
+#define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I   BIT(0)
 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I   BIT(4)
 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
 #define PRCM_PWR_SWITCH_REG(c, cpu)(0x140 + 0x10 * (c) + 0x4 * (cpu))
 #define PRCM_CPU_SOFT_ENTRY_REG0x164
 
+/* R_CPUCFG registers, specific to sun8i-a83t */
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL(c)(0x30 + (c) * 0x4)
+#define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n)   BIT(n)
+#define R_CPUCFG_CPU_SOFT_ENTRY_REG0x01a4
+
 #define CPU0_SUPPORT_HOTPLUG_MAGIC00xFA50392F
 #define CPU0_SUPPORT_HOTPLUG_MAGIC10x790DCA3A
 
 static void __iomem *cpucfg_base;
 static void __iomem *prcm_base;
 static void __iomem *sram_b_smp_base;
+static void __iomem *r_cpucfg_base;
 
 extern void sunxi_mc_smp_secondary_startup(void);
 extern void sunxi_mc_smp_resume(void);
@@ -161,6 +170,16 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_sun8i) {
+   /* assert cpu power-on reset */
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* Cortex-A7: hold L1 reset disable signal low */
if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
@@ -184,17 +203,38 @@ static int sunxi_cpu_powerup(unsigned int cpu, unsigned 
int cluster)
/* open power switch */
sunxi_cpu_power_switch_set(cpu, cluster, true);
 
+   /* Handle A83T bit swap */
+   if (is_sun8i) {
+   if (cpu == 0)
+   cpu = 4;
+   }
+
/* clear processor power gate */
reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
udelay(20);
 
+   /* Handle A83T bit swap */
+   if (is_sun8i) {
+   if (cpu == 4)
+   cpu = 0;
+   }
+
/* de-assert processor power-on reset */
reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
 
+   if (is_sun8i) {
+   reg  = readl(r_cpucfg_base +
+R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
+   writel(reg, r_cpucfg_base +
+  R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* de-assert all processor resets */
reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
@@ -216,6 +256,14 @@ static int sunxi_cluster_powerup(unsigned int cluster)
if (cluster >= SUNXI_NR_CLUSTERS)
return -EINVAL;
 
+   /* For A83T, assert cluster cores resets */
+   if (is_sun8i) {
+   reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+   reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;   /* Core Reset*/
+   writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
+   udelay(10);
+   }
+
/* assert ACINACTM */
reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
reg |= 

Re: [RFC 3/3] arm: shmobile: Add the RZ/N1D SMP enabler driver.

[Florian Fainelli]

Hi Michel,

On 04/16/2018 02:34 AM, Michel Pollet wrote:
> The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
> requires a special enable method to get it started at boot time.
> 
> Signed-off-by: Michel Pollet 

Some few comments below. This patch should probably be re-ordered in
your patch series, I would expect you to have this become patch 2 and
have patch 2 be patch 3 (first you add infrastructure for using
something, then you make use of it).

> +static int rzn1_smp_boot_secondary(unsigned int cpu, struct task_struct 
> *idle)
> +{
> + if (!cpu_bootaddr)
> + return -ENODEV;
> +
> + spin_lock(_lock);
> +
> + writel(virt_to_phys(secondary_startup), cpu_bootaddr);

Consider using __pa_symbol() instead of virt_to_phys() since
secondary_startup is part of the kernel's linear memory map.

> + arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> +
> + spin_unlock(_lock);
> +
> + return 0;
> +}
> +
> +static void __init rzn1_smp_prepare_cpus(unsigned int max_cpus)
> +{
> + struct device_node *dn;
> + int ret;
> + u32 bootaddr;
> +
> + dn = of_get_cpu_node(1, NULL);
> + if (!dn) {
> + pr_err("CPU#1: missing device tree node\n");
> + return;
> + }
> + /*
> +  * Determine the address from which the CPU is polling.
> +  */
> + ret = of_property_read_u32(dn, "cpu-release-addr", );
> + if (ret)
> + pr_err("CPU#1: invalid cpu-release-addr property\n");
> +
> + of_node_put(dn);
> + /* The bootloader *does* change this property */

This comment should probably be moved above the function that fetches
"cpu-release-addr"

> + pr_info("CPU#1: cpu-release-addr %08x\n", (u32)bootaddr);
> +
> + if (!bootaddr)
> + return;

Would not you want to show a message here to help catch such conditions

> +
> + cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr));

Relying on ioremap() to reject values that might be outside of the
allowed range may be a little fragile, but I can't suggest any better
alternative.

> + if (!cpu_bootaddr)
> + pr_err("CPU#1: cpu-release-addr map failed\n");
> +}
> +
> +static const struct smp_operations rzn1_smp_ops __initconst = {
> + .smp_prepare_cpus = rzn1_smp_prepare_cpus,
> + .smp_boot_secondary = rzn1_smp_boot_secondary,
> +};
> +CPU_METHOD_OF_DECLARE(rzn1_smp, "renesas,r9a06g032-smp", _smp_ops);
> 


-- 
Florian

Re: [PATCH] DT: mmc: tmio_mmc: document R8A77980 bindings

[Rob Herring]

On Mon, Apr 16, 2018 at 09:30:02PM +0300, Sergei Shtylyov wrote:
> Document the R-Car V3H (R8A77980) SoC in the Renesas SDHI bindings.
> 
> Signed-off-by: Sergei Shtylyov 
> 
> ---
> This patch is against the 'next' branch of Ulf Hansson's 'mmc.git' repo.
> 
>  Documentation/devicetree/bindings/mmc/tmio_mmc.txt |1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Rob Herring 

Re: [RFC 1/3] dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method.

[Rob Herring]

On Mon, Apr 16, 2018 at 10:34:57AM +0100, Michel Pollet wrote:
> Add a special enable method for second CA8 of the Renesas RZ/N1D
> (R9A06G032).
> 
> Signed-off-by: Michel Pollet 
> ---
>  Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Rob Herring 

Re: [PATCH v3] gpio: dwapb: Add support for 1 interrupt per port A GPIO

[Rob Herring]

On Fri, Apr 13, 2018 at 09:51:12AM +0100, Phil Edworthy wrote:
> The DesignWare GPIO IP can be configured for either 1 interrupt or 1
> per GPIO in port A, but the driver currently only supports 1 interrupt.
> See the DesignWare DW_apb_gpio Databook description of the
> 'GPIO_INTR_IO' parameter.
> 
> This change allows the driver to work with up to 32 interrupts, it will
> get as many interrupts as specified in the DT 'interrupts' property.
> It doesn't do anything clever with the different interrupts, it just calls
> the same handler used for single interrupt hardware.
> 
> Signed-off-by: Phil Edworthy 
> ---
> One point to mention is that I have made it possible for users to have
> unconncted interrupts by specifying holes in the list of interrupts. This is
> done by supporting the interrupts-extended DT prop.
> However, I have no use for this and had to hack some test case for this.
> Perhaps the driver should support 1 interrupt or all GPIOa as interrupts?
> 
> v3:
>  - Rolled mfd: intel_quark_i2c_gpio fix into this patch to avoid bisect 
> problems
> v2:
>  - Replaced interrupt-mask DT prop with support for the interrupts-extended
>prop. This means replacing the call to irq_of_parse_and_map() with calls
>to of_irq_parse_one() and irq_create_of_mapping().
> 
> Note: There are a few *code* lines over 80 chars, but this is just guidance,
>right? Especially as there are already some lines over 80 chars.
> ---
>  .../devicetree/bindings/gpio/snps-dwapb-gpio.txt   |  9 -
>  drivers/gpio/gpio-dwapb.c  | 43 
> +-
>  drivers/mfd/intel_quark_i2c_gpio.c |  3 +-
>  include/linux/platform_data/gpio-dwapb.h   |  3 +-
>  4 files changed, 45 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt 
> b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> index 4a75da7..3c1118b 100644
> --- a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> +++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
> @@ -26,8 +26,13 @@ controller.
>the second encodes the triger flags encoded as described in
>Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
>  - interrupt-parent : The parent interrupt controller.
> -- interrupts : The interrupt to the parent controller raised when GPIOs
> -  generate the interrupts.
> +- interrupts : The interrupts to the parent controller raised when GPIOs
> +  generate the interrupts. If the controller provides one combined interrupt
> +  for all GPIOs, specify a single interrupt. If the controller provides one
> +  interrupt for each GPIO, provide a list of interrupts that correspond to 
> each
> +  of the GPIO pins. When specifying multiple interrupts, if any are 
> unconnected,
> +  use the interrupts-extended property to specify the interrupts and set the
> +  interrupt controller handle for unused interrupts to 0.
>  - snps,nr-gpios : The number of pins in the port, a single cell.
>  - resets : Reset line for the controller.
>  
> diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c
> index 226977f..3273504 100644
> --- a/drivers/gpio/gpio-dwapb.c
> +++ b/drivers/gpio/gpio-dwapb.c
> @@ -441,14 +441,19 @@ static void dwapb_configure_irqs(struct dwapb_gpio 
> *gpio,
>   irq_gc->chip_types[1].handler = handle_edge_irq;
>  
>   if (!pp->irq_shared) {
> - irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
> -  gpio);
> + int i;
> +
> + for (i = 0; i < pp->ngpio; i++) {
> + if (pp->irq[i])
> + irq_set_chained_handler_and_data(pp->irq[i],
> + dwapb_irq_handler, gpio);
> + }
>   } else {
>   /*
>* Request a shared IRQ since where MFD would have devices
>* using the same irq pin
>*/
> - err = devm_request_irq(gpio->dev, pp->irq,
> + err = devm_request_irq(gpio->dev, pp->irq[0],
>  dwapb_irq_handler_mfd,
>  IRQF_SHARED, "gpio-dwapb-mfd", gpio);
>   if (err) {
> @@ -524,7 +529,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
>   if (pp->idx == 0)
>   port->gc.set_config = dwapb_gpio_set_config;
>  
> - if (pp->irq)
> + if (pp->has_irq)
>   dwapb_configure_irqs(gpio, port, pp);
>  
>   err = gpiochip_add_data(>gc, port);
> @@ -535,7 +540,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
>   port->is_registered = true;
>  
>   /* Add GPIO-signaled ACPI event support */
> - if (pp->irq)
> + if (pp->has_irq)
>   acpi_gpiochip_request_interrupts(>gc);
>  
>   return err;
> @@ -601,13 +606,33 @@ 

Re: [PATCH] DT: mmc: tmio_mmc: document R8A77980 bindings

[Wolfram Sang]

On Mon, Apr 16, 2018 at 09:30:02PM +0300, Sergei Shtylyov wrote:
> Document the R-Car V3H (R8A77980) SoC in the Renesas SDHI bindings.
> 
> Signed-off-by: Sergei Shtylyov 

Reviewed-by: Wolfram Sang 



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[PATCH v2] dt-bindings: gpio: Add support for r8a77965

[Jacopo Mondi]

Add compatible string for R-Car M3-N (r8a77965) in gpio-rcar.

Signed-off-by: Jacopo Mondi 
Reviewed-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Reviewed-by: Rob Herring 
---

Renesas R-Car M3-N support has been merged for v4.17.
Document the missing device tree bindings.

v1 -> v2:
- Add Simon and Rob Reviewed-by tags

---
 Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt 
b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index 9474138..f2af897 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -14,6 +14,7 @@ Required Properties:
 - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO 
controller.
 - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO 
controller.
 - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO 
controller.
+- "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO 
controller.
 - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO 
controller.
 - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO 
controller.
 - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
--
2.7.4

Re: [PATCH] dt-bindings: net: ravb: Add support for r8a77965 SoC

[jacopo mondi]

Hi David,

On Mon, Apr 16, 2018 at 10:17:55AM -0400, David Miller wrote:
> From: Jacopo Mondi 
> Date: Mon, 16 Apr 2018 15:55:17 +0200
>
> > Add documentation for r8a77965 compatible string to renesas ravb device
> > tree bindings documentation.
> >
> > Signed-off-by: Jacopo Mondi 
> > Reviewed-by: Geert Uytterhoeven 
> > Reviewed-by: Simon Horman 
> > Acked-by: Sergei Shtylyov 
> > ---
> >
> > Renesas R-Car M3-N support has been merged for v4.17.
> > Document the missing device tree bindings.
>
> Since this is purely a devicetree update, I'm assuming that it doesn't
> go through my networking tree.

Rob has picked this patch up in his tree, so no need for you to do the
same.

Thanks
   j


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Description: PGP signature

[PATCH] DT: mmc: tmio_mmc: document R8A77980 bindings

[Sergei Shtylyov]

Document the R-Car V3H (R8A77980) SoC in the Renesas SDHI bindings.

Signed-off-by: Sergei Shtylyov 

---
This patch is against the 'next' branch of Ulf Hansson's 'mmc.git' repo.

 Documentation/devicetree/bindings/mmc/tmio_mmc.txt |1 +
 1 file changed, 1 insertion(+)

Index: mmc/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
===
--- mmc.orig/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ mmc/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -26,6 +26,7 @@ Required properties:
"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
+   "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
"renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller

Applied "spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCR" to the spi tree

[Mark Brown]

The patch

   spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCR

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 10b4640833e95eeacaef8060bc1b35e636df3218 Mon Sep 17 00:00:00 2001
From: Vladimir Zapolskiy 
Date: Fri, 13 Apr 2018 15:44:16 +0300
Subject: [PATCH] spi: sh-msiof: Fix bit field overflow writes to TSCR/RSCR

The change fixes a bit field overflow which allows to write to higher
bits while calculating SPI transfer clock and setting BRPS and BRDV
bit fields, the problem is reproduced if 'parent_rate' to 'spi_hz'
ratio is greater than 1024, for instance

  p->min_div  = 2,
  MSO rate= ,
  SPI device rate = 1

results in

  k  = 5, i.e. BRDV = 0b100 or 1/32 prescaler output,
  BRPS   = 105,
  TSCR value = 0x6804, thus MSSEL and MSIMM bit fields are non-zero.

Fixes: 65d5665bb260 ("spi: sh-msiof: Update calculation of frequency dividing")
Signed-off-by: Vladimir Zapolskiy 
Signed-off-by: Mark Brown 
---
 drivers/spi/spi-sh-msiof.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index ae086aab57d5..8171eedbfc90 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -283,6 +283,7 @@ static void sh_msiof_spi_set_clk_regs(struct 
sh_msiof_spi_priv *p,
}
 
k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
+   brps = min_t(int, brps, 32);
 
scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
sh_msiof_write(p, TSCR, scr);
-- 
2.17.0

Applied "spi: sh-msiof: Simplify calculation of divisors for transfer rate" to the spi tree

[Mark Brown]

The patch

   spi: sh-msiof: Simplify calculation of divisors for transfer rate

has been applied to the spi tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From d8fb2a06943522b193a649c930020780870f0ee4 Mon Sep 17 00:00:00 2001
From: Vladimir Zapolskiy 
Date: Fri, 13 Apr 2018 15:44:17 +0300
Subject: [PATCH] spi: sh-msiof: Simplify calculation of divisors for transfer
 rate

The change updates sh_msiof_spi_set_clk_regs() function by iterating
over BRDV power values. Note that the change is a functional one, namely
prescaler output x 1/1 set in BRDV bit field (0b111) for MSO division
rate set to 2 is substituted by BRDV = 0b000 and BRPS = 0b0, in terms
of written values to TSCR setting of 0x0107 is substituted by 0x,
and for all input parameter cases this is the only functional change,
which touches the controller.

As a result of the rework the function is supposed to be slightly more
efficient and more readable and maintainable in case of any further
extensions.

Signed-off-by: Vladimir Zapolskiy 
Signed-off-by: Mark Brown 
---
 drivers/spi/spi-sh-msiof.c | 67 --
 1 file changed, 35 insertions(+), 32 deletions(-)

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 8171eedbfc90..5c1ff0097e41 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -39,7 +39,7 @@ struct sh_msiof_chipdata {
u16 tx_fifo_size;
u16 rx_fifo_size;
u16 master_flags;
-   u16 min_div;
+   u16 min_div_pow;
 };
 
 struct sh_msiof_spi_priv {
@@ -51,7 +51,7 @@ struct sh_msiof_spi_priv {
struct completion done;
unsigned int tx_fifo_size;
unsigned int rx_fifo_size;
-   unsigned int min_div;
+   unsigned int min_div_pow;
void *tx_dma_page;
void *rx_dma_page;
dma_addr_t tx_dma_addr;
@@ -249,43 +249,46 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
return IRQ_HANDLED;
 }
 
-static struct {
-   unsigned short div;
-   unsigned short brdv;
-} const sh_msiof_spi_div_table[] = {
-   { 1,SCR_BRDV_DIV_1 },
-   { 2,SCR_BRDV_DIV_2 },
-   { 4,SCR_BRDV_DIV_4 },
-   { 8,SCR_BRDV_DIV_8 },
-   { 16,   SCR_BRDV_DIV_16 },
-   { 32,   SCR_BRDV_DIV_32 },
+static const u32 sh_msiof_spi_div_array[] = {
+   SCR_BRDV_DIV_1, SCR_BRDV_DIV_2,  SCR_BRDV_DIV_4,
+   SCR_BRDV_DIV_8, SCR_BRDV_DIV_16, SCR_BRDV_DIV_32,
 };
 
 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
  unsigned long parent_rate, u32 spi_hz)
 {
-   unsigned long div = 1024;
+   unsigned long div;
u32 brps, scr;
-   size_t k;
+   unsigned int div_pow = p->min_div_pow;
 
-   if (!WARN_ON(!spi_hz || !parent_rate))
-   div = DIV_ROUND_UP(parent_rate, spi_hz);
-
-   div = max_t(unsigned long, div, p->min_div);
+   if (!spi_hz || !parent_rate) {
+   WARN(1, "Invalid clock rate parameters %lu and %u\n",
+parent_rate, spi_hz);
+   return;
+   }
 
-   for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
-   brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
+   div = DIV_ROUND_UP(parent_rate, spi_hz);
+   if (div <= 1024) {
/* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
-   if (sh_msiof_spi_div_table[k].div == 1 && brps > 2)
-   continue;
-   if (brps <= 32) /* max of brdv is 32 */
-   break;
-   }
+   if (!div_pow && div <= 32 && div > 2)
+   div_pow = 1;
+
+   if (div_pow)
+   brps = (div + 1) >> div_pow;
+   else
+   brps = div;
 
-   k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
-   brps = min_t(int, brps, 32);
+   for (; brps > 32; div_pow++)
+   brps = (brps + 1) >> 1;
+   } else {
+   /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */
+   

Re: [PATCH] ARM: dts: renesas: replace toshiba, mmc-wrprotect-disable with disable-wp

[Geert Uytterhoeven]

Hi Yamada-san,

On Mon, Apr 16, 2018 at 5:02 PM, Masahiro Yamada
 wrote:
> Follow up commit 788778b0d21a ("mmc: tmio: deprecate "toshiba,
> mmc-wrprotect-disable" DT property").

Thanks for following up this work.

(I had the exact same changes queued up in my local branch, to be sent out
 after v4.17-rc1, but you beat me to it ;-)

> Signed-off-by: Masahiro Yamada 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] ARM: dts: renesas: replace toshiba,mmc-wrprotect-disable with disable-wp

[Wolfram Sang]

On Tue, Apr 17, 2018 at 12:02:32AM +0900, Masahiro Yamada wrote:
> Follow up commit 788778b0d21a ("mmc: tmio: deprecate "toshiba,
> mmc-wrprotect-disable" DT property").
> 
> Signed-off-by: Masahiro Yamada 

Reviewed-by: Wolfram Sang 



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Re: [PATCH] dt-bindings: dmaengine: rcar-dmac: document R8A77965 support

[Rob Herring]

On Mon, Apr 16, 2018 at 03:56:08PM +0200, Jacopo Mondi wrote:
> Add documentation for r8a77965 compatible string to rcar-dmac device
> tree bindings documentation.
> 
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Geert Uytterhoeven 
> Reviewed-by: Simon Horman 
> ---
> 
> Renesas R-Car M3-N support has been merged for v4.17.
> Document the missing device tree bindings.
> 
> ---
>  Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
>  1 file changed, 1 insertion(+)

Applied.

Rob

Re: [PATCH] dt-bindings: serial: sh-sci: Add support for r8a77965 (H)SCIF

[Rob Herring]

On Mon, Apr 16, 2018 at 03:55:28PM +0200, Jacopo Mondi wrote:
> Add documentation for r8a77965 compatible string to Renesas sci-serial
> device tree bindings documentation.
> 
> Signed-off-by: Jacopo Mondi 
> ---
> 
> Renesas R-Car M3-N support has been merged for v4.17.
> Document the missing device tree bindings.
> 
> ---
>  Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++
>  1 file changed, 2 insertions(+)

Applied.

Rob

Re: [PATCH] dt-bindings: net: ravb: Add support for r8a77965 SoC

[Rob Herring]

On Mon, Apr 16, 2018 at 03:55:17PM +0200, Jacopo Mondi wrote:
> Add documentation for r8a77965 compatible string to renesas ravb device
> tree bindings documentation.
> 
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Geert Uytterhoeven 
> Reviewed-by: Simon Horman 
> Acked-by: Sergei Shtylyov 
> ---
> 
> Renesas R-Car M3-N support has been merged for v4.17.
> Document the missing device tree bindings.
> 
> ---
>  Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
>  1 file changed, 1 insertion(+)

Applied.

Rob

Re: [PATCH] dt-bindings: gpio: Add support for r8a77965

[Rob Herring]

On Mon, Apr 16, 2018 at 03:55:04PM +0200, Jacopo Mondi wrote:
> Add compatible string for R-Car M3-N (r8a77965) in gpio-rcar.
> 
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Geert Uytterhoeven 
> ---

You missed Simon's and my R-by's on v2.

> 
> Renesas R-Car M3-N support has been merged for v4.17.
> Document the missing device tree bindings.
> 
> ---
>  Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt 
> b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
> index 9474138..f2af897 100644
> --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
> +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
> @@ -14,6 +14,7 @@ Required Properties:
>  - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO 
> controller.
>  - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO 
> controller.
>  - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO 
> controller.
> +- "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO 
> controller.
>  - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO 
> controller.
>  - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO 
> controller.
>  - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
> --
> 2.7.4
> 

Re: [PATCH v7] media: platform: Renesas IMR driver

[Sergei Shtylyov]

On 04/16/2018 04:27 PM, Geert Uytterhoeven wrote:

>> The image renderer, or the distortion correction engine, is a drawing
>> processor with a simple instruction system capable of referencing video
>> capture data or data in an external memory as the 2D texture data and
>> performing texture mapping and drawing with respect to any shape that is
>> split into triangular objects.
>>
>> This V4L2 memory-to-memory device driver only supports image renderer light
>> extended 4 (IMR-LX4) found in the R-Car gen3 SoCs; the R-Car gen2 support
>> can be added later...
>>
>> Based on the original patch by Konstantin Kozhevnikov.
>>
>> Signed-off-by: Konstantin Kozhevnikov 
>> 
>> Signed-off-by: Sergei Shtylyov 
>> Acked-by: Rob Herring 
> 
>>  Documentation/devicetree/bindings/media/rcar_imr.txt |   27
>>  Documentation/media/v4l-drivers/index.rst|1
>>  Documentation/media/v4l-drivers/rcar_imr.rst |  372 +++
>>  drivers/media/platform/Kconfig   |   13
>>  drivers/media/platform/Makefile  |1
>>  drivers/media/platform/rcar_imr.c| 1832 
>> +++
>>  include/uapi/linux/rcar_imr.h|  182 +
>>  7 files changed, 2428 insertions(+)
> 
> What's the status of this patch?

   Changes requested, and I'm still having no bandwidth to make them... 

> The compatible value "renesas,r8a7796-imr-lx4" has been in use since v4.14.

   That's because the SoC bindings are unlikely to change...

> Thanks!
> 
> Gr{oetje,eeting}s,
> 
> Geert

MBR, Sergei

Re: [PATCH] pinctrl: sh-pfc: r8a77970: add pin I/O voltage control

[Sergei Shtylyov]

Hello!

On 04/16/2018 04:02 PM, Geert Uytterhoeven wrote:

>> Add the pin I/O voltage level control to the R8A77980 PFC driver.
> 
> Subject says r8a77970?

   Typo, I guess. :-)

>> Loosely based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov 
>> Signed-off-by: Sergei Shtylyov 
>>
>> ---
>>  drivers/pinctrl/sh-pfc/pfc-r8a77980.c |   50 
>> +++---
>>  1 file changed, 47 insertions(+), 3 deletions(-)
>>
>> Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
>> ===
>> --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
>> +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
> 
> Ah, pfc-r8a77980.c it is.
> 
>> @@ -2779,8 +2779,51 @@ static const struct pinmux_cfg_reg pinmu
>> { },
>>  };
>>
>> +enum ioctrl_regs {
>> +   IOCTRL30,
>> +   IOCTRL31,
>> +   IOCTRL32,
>> +};
>> +
>> +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
>> +   [IOCTRL30] = { 0xe6060380, },
>> +   [IOCTRL31] = { 0xe6060384, },
>> +   [IOCTRL32] = { 0xe6060388, },
>> +   { /* sentinel */ },
> 
> However, r8a77980 has 4 IOCTRL3x registers (r8a77970 has three)?

   I thought that since we don't change it, no need to list it for save/restore
either. I was wrong?

> Something is wrong: which SoC source file is this patch for?

   R8A77980.

> Gr{oetje,eeting}s,
> 
> Geert

MBR, Sergei

[PATCH] ARM: dts: renesas: replace toshiba,mmc-wrprotect-disable with disable-wp

[Masahiro Yamada]

Follow up commit 788778b0d21a ("mmc: tmio: deprecate "toshiba,
mmc-wrprotect-disable" DT property").

Signed-off-by: Masahiro Yamada 
---

 arch/arm/boot/dts/r8a73a4-ape6evm.dts | 4 ++--
 arch/arm/boot/dts/sh73a0.dtsi | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts 
b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index ec7c86e..125c39c 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -234,7 +234,7 @@
  {
vmmc-supply = <_sdhi0>;
bus-width = <4>;
-   toshiba,mmc-wrprotect-disable;
+   disable-wp;
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
@@ -244,7 +244,7 @@
vmmc-supply = <_fixed_3v3>;
bus-width = <4>;
broken-cd;
-   toshiba,mmc-wrprotect-disable;
+   disable-wp;
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "okay";
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 914a7c2..39cc586 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -336,7 +336,7 @@
  GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <_clks SH73A0_CLK_SDHI1>;
power-domains = <_a3sp>;
-   toshiba,mmc-wrprotect-disable;
+   disable-wp;
cap-sd-highspeed;
status = "disabled";
};
@@ -348,7 +348,7 @@
  GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <_clks SH73A0_CLK_SDHI2>;
power-domains = <_a3sp>;
-   toshiba,mmc-wrprotect-disable;
+   disable-wp;
cap-sd-highspeed;
status = "disabled";
};
-- 
2.7.4

Re: [PATCH] dt-bindings: serial: sh-sci: Add support for r8a77965 (H)SCIF

[Geert Uytterhoeven]

On Mon, Apr 16, 2018 at 3:55 PM, Jacopo Mondi  wrote:
> Add documentation for r8a77965 compatible string to Renesas sci-serial
> device tree bindings documentation.
>
> Signed-off-by: Jacopo Mondi 

My
Reviewed-by: Geert Uytterhoeven 
on v2 of the full r8a77965 series is still valid.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] dt-bindings: net: ravb: Add support for r8a77965 SoC

[David Miller]

From: Jacopo Mondi 
Date: Mon, 16 Apr 2018 15:55:17 +0200

> Add documentation for r8a77965 compatible string to renesas ravb device
> tree bindings documentation.
> 
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Geert Uytterhoeven 
> Reviewed-by: Simon Horman 
> Acked-by: Sergei Shtylyov 
> ---
> 
> Renesas R-Car M3-N support has been merged for v4.17.
> Document the missing device tree bindings.

Since this is purely a devicetree update, I'm assuming that it doesn't
go through my networking tree.

[PATCH] dt-bindings: dmaengine: rcar-dmac: document R8A77965 support

[Jacopo Mondi]

Add documentation for r8a77965 compatible string to rcar-dmac device
tree bindings documentation.

Signed-off-by: Jacopo Mondi 
Reviewed-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
---

Renesas R-Car M3-N support has been merged for v4.17.
Document the missing device tree bindings.

---
 Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt 
b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
index aadfb23..61315ea 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.txt
@@ -26,6 +26,7 @@ Required Properties:
- "renesas,dmac-r8a7794" (R-Car E2)
- "renesas,dmac-r8a7795" (R-Car H3)
- "renesas,dmac-r8a7796" (R-Car M3-W)
+   - "renesas,dmac-r8a77965" (R-Car M3-N)
- "renesas,dmac-r8a77970" (R-Car V3M)
- "renesas,dmac-r8a77980" (R-Car V3H)

--
2.7.4

[PATCH] dt-bindings: net: ravb: Add support for r8a77965 SoC

[Jacopo Mondi]

Add documentation for r8a77965 compatible string to renesas ravb device
tree bindings documentation.

Signed-off-by: Jacopo Mondi 
Reviewed-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Acked-by: Sergei Shtylyov 
---

Renesas R-Car M3-N support has been merged for v4.17.
Document the missing device tree bindings.

---
 Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt 
b/Documentation/devicetree/bindings/net/renesas,ravb.txt
index c306f55..890526d 100644
--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
+++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
@@ -18,6 +18,7 @@ Required properties:

   - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
   - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
+  - "renesas,etheravb-r8a77965" for the R8A77965 SoC.
   - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
   - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
   - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
--
2.7.4

[PATCH] dt-bindings: serial: sh-sci: Add support for r8a77965 (H)SCIF

[Jacopo Mondi]

Add documentation for r8a77965 compatible string to Renesas sci-serial
device tree bindings documentation.

Signed-off-by: Jacopo Mondi 
---

Renesas R-Car M3-N support has been merged for v4.17.
Document the missing device tree bindings.

---
 Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt 
b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index ad962f4..0cc5417 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -41,6 +41,8 @@ Required properties:
 - "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
 - "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART.
 - "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
+- "renesas,scif-r8a77965" for R8A77965 (R-Car M3-N) SCIF compatible UART.
+- "renesas,hscif-r8a77965" for R8A77965 (R-Car M3-N) HSCIF compatible UART.
 - "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
 - "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
 - "renesas,scif-r8a77980" for R8A77980 (R-Car V3H) SCIF compatible UART.
--
2.7.4

[PATCH] dt-bindings: gpio: Add support for r8a77965

[Jacopo Mondi]

Add compatible string for R-Car M3-N (r8a77965) in gpio-rcar.

Signed-off-by: Jacopo Mondi 
Reviewed-by: Geert Uytterhoeven 
---

Renesas R-Car M3-N support has been merged for v4.17.
Document the missing device tree bindings.

---
 Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt 
b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index 9474138..f2af897 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -14,6 +14,7 @@ Required Properties:
 - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO 
controller.
 - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO 
controller.
 - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO 
controller.
+- "renesas,gpio-r8a77965": for R8A77965 (R-Car M3-N) compatible GPIO 
controller.
 - "renesas,gpio-r8a77970": for R8A77970 (R-Car V3M) compatible GPIO 
controller.
 - "renesas,gpio-r8a77995": for R8A77995 (R-Car D3) compatible GPIO 
controller.
 - "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
--
2.7.4

Re: [PATCH v7] media: platform: Renesas IMR driver

[Geert Uytterhoeven]

Hi Sergei,

On Fri, Aug 4, 2017 at 8:03 PM, Sergei Shtylyov
 wrote:
> The image renderer, or the distortion correction engine, is a drawing
> processor with a simple instruction system capable of referencing video
> capture data or data in an external memory as the 2D texture data and
> performing texture mapping and drawing with respect to any shape that is
> split into triangular objects.
>
> This V4L2 memory-to-memory device driver only supports image renderer light
> extended 4 (IMR-LX4) found in the R-Car gen3 SoCs; the R-Car gen2 support
> can be added later...
>
> Based on the original patch by Konstantin Kozhevnikov.
>
> Signed-off-by: Konstantin Kozhevnikov 
> 
> Signed-off-by: Sergei Shtylyov 
> Acked-by: Rob Herring 

>  Documentation/devicetree/bindings/media/rcar_imr.txt |   27
>  Documentation/media/v4l-drivers/index.rst|1
>  Documentation/media/v4l-drivers/rcar_imr.rst |  372 +++
>  drivers/media/platform/Kconfig   |   13
>  drivers/media/platform/Makefile  |1
>  drivers/media/platform/rcar_imr.c| 1832 
> +++
>  include/uapi/linux/rcar_imr.h|  182 +
>  7 files changed, 2428 insertions(+)

What's the status of this patch?
The compatible value "renesas,r8a7796-imr-lx4" has been in use since v4.14.

Thanks!

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 15/19] dt-bindings: gpio: Add support for r8a77965

[jacopo mondi]

Hi Geert,

On Mon, Apr 16, 2018 at 01:12:06PM +0200, Geert Uytterhoeven wrote:
> Hi Jacopo,
>
> On Tue, Feb 20, 2018 at 4:12 PM, Jacopo Mondi  
> wrote:
> > Add compatible string for R-Car M3-N (r8a77965) in gpio-rcar.
> >
> > Signed-off-by: Jacopo Mondi 
> > Reviewed-by: Geert Uytterhoeven 
>
> Can you please resend to the GPIO maintainer?
> Thanks!

Thank you for the useful reminder.

From my original M3-N support series, the following DT binding patches
have actually to be resent, now that the SoC support is in v4.17-rc1.

dt-bindings: dmaengine: rcar-dmac: document R8A77965 support
dt-bindings: serial: sh-sci: Add support for r8a77965 (H)SCIF
dt-bindings: net: ravb: Add support for r8a77965 SoC
dt-bindings: gpio: Add support for r8a77965

I will resend each one to the appropriate tree maintainer.

Thanks
   j


>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- 
> ge...@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like 
> that.
> -- Linus Torvalds


signature.asc
Description: PGP signature

Re: [PATCH] pinctrl: sh-pfc: r8a77970: add pin I/O voltage control

[Geert Uytterhoeven]

Hi Sergei,

Thanks for your patch!

On Fri, Apr 13, 2018 at 8:29 PM, Sergei Shtylyov
 wrote:
> Add the pin I/O voltage level control to the R8A77980 PFC driver.

Subject says r8a77970?

> Loosely based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov 
> Signed-off-by: Sergei Shtylyov 
>
> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a77980.c |   50 
> +++---
>  1 file changed, 47 insertions(+), 3 deletions(-)
>
> Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
> ===
> --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77980.c
> +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c

Ah, pfc-r8a77980.c it is.

> @@ -2779,8 +2779,51 @@ static const struct pinmux_cfg_reg pinmu
> { },
>  };
>
> +enum ioctrl_regs {
> +   IOCTRL30,
> +   IOCTRL31,
> +   IOCTRL32,
> +};
> +
> +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
> +   [IOCTRL30] = { 0xe6060380, },
> +   [IOCTRL31] = { 0xe6060384, },
> +   [IOCTRL32] = { 0xe6060388, },
> +   { /* sentinel */ },

However, r8a77980 has 4 IOCTRL3x registers (r8a77970 has three)?

Something is wrong: which SoC source file is this patch for?

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v13 2/2] rcar-csi2: add Renesas R-Car MIPI CSI-2 receiver driver

[jacopo mondi]

Hi Niklas,

On Mon, Apr 16, 2018 at 01:16:35AM +0200, Niklas Söderlund wrote:
> Hi Jacopo,
>
> Thanks for your feedback.
>
> Comments I have snipped out from this reply are addressed, thanks for
> bringing them to my attention!
>
> On 2018-04-05 11:10:01 +0200, Jacopo Mondi wrote:
>
> [snip]
>
> > > +static int rcar_csi2_wait_phy_start(struct rcar_csi2 *priv)
> > > +{
> > > + int timeout;
> > > +
> > > + /* Wait for the clock and data lanes to enter LP-11 state. */
> > > + for (timeout = 100; timeout > 0; timeout--) {
> > > + const u32 lane_mask = (1 << priv->lanes) - 1;
> > > +
> > > + if ((rcar_csi2_read(priv, PHCLM_REG) & 1) == 1 &&
> >
> > Nitpicking:
> > if ((rcar_csi2_read(priv, PHCLM_REG) & 0x01) &&
> >
> > Don't you prefer to provide defines also for bit fields instead of
> > using magic values? In this case something like
> > PHCLM_REG_STOPSTATE_CLK would do.
>
> Thanks addressed per your and Kieran's suggestion.
>
> >
> > Also, from tables 25.[17-20] it seems to me that for H3 and V3 you
> > have to set INSTATE to an hardcoded value after having validated PHDLM.
> > Maybe it is not necessary, just pointing it out.
>
> I assume you mean Figures 25.[17-20] and not Tables as the last table in
> chapter 25 is Table 25.15 and the register in question is INTSTATE :-)
> And to clarify this is documented for H3 which this driver supports and
> V3H and M3-N which this driver dose not yet support. And the constant
> you are to set it to is ULPS_START | UPLS_END.

Yes, Figures, not Tables, sorry about this.

>
> This is a good catch as this was introduced in a later version of the
> datasheet and the current code where the ULPS_START | UPLS_END is set
> before confirming LP-11 have kept on working. Check the
> priv->info->clear_ulps usage in rcar_csi2_start(). I do think it's
> better to follow the flow-chart in the new datasheet so I will move this
> to the end of rcar_csi2_start() to reflect that (provided that the end
> result still works :-) Thanks for pointing this out!
>

I see...

Actually, I don't see M3-N in the manual version I'm looking at.
Anyway, I just hope this per-soc specificities are limited.

> [snip]
>
> > > +static int rcar_csi2_start(struct rcar_csi2 *priv)
> > > +{
> > > + const struct rcar_csi2_format *format;
> > > + u32 phycnt, phypll, vcdt = 0, vcdt2 = 0;
> > > + unsigned int i;
> > > + int ret;
> > > +
> > > + dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
> > > + priv->mf.width, priv->mf.height,
> > > + priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
> > > +
> > > + /* Code is validated in set_fmt */
> > > + format = rcar_csi2_code_to_fmt(priv->mf.code);
> > > +
> > > + /*
> > > +  * Enable all Virtual Channels
> > > +  *
> > > +  * NOTE: It's not possible to get individual datatype for each
> > > +  *   source virtual channel. Once this is possible in V4L2
> > > +  *   it should be used here.
> > > +  */
> > > + for (i = 0; i < 4; i++) {
> > > + u32 vcdt_part;
> > > +
> > > + vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON |
> > > + VCDT_SEL_DT(format->datatype);
> > > +
> > > + /* Store in correct reg and offset */
> > > + if (i < 2)
> > > + vcdt |= vcdt_part << ((i % 2) * 16);
> > > + else
> > > + vcdt2 |= vcdt_part << ((i % 2) * 16);
> > > + }
> > > +
> > > + switch (priv->lanes) {
> > > + case 1:
> > > + phycnt = PHYCNT_ENABLECLK | PHYCNT_ENABLE_0;
> > > + break;
> > > + case 2:
> > > + phycnt = PHYCNT_ENABLECLK | PHYCNT_ENABLE_1 | PHYCNT_ENABLE_0;
> > > + break;
> > > + case 4:
> > > + phycnt = PHYCNT_ENABLECLK | PHYCNT_ENABLE_3 | PHYCNT_ENABLE_2 |
> > > + PHYCNT_ENABLE_1 | PHYCNT_ENABLE_0;
> > > + break;
> >
> > Even simpler this could be written as
> >
> > phycnt = PHYCNT_ENABLECLK | (1 << priv->lanes) - 1;
>
> Fixed per your and Geert's suggestion.
>
> >
> > > + default:
> > > + return -EINVAL;
> >
> > Can this happen? You have validated priv->lanes already when parsing
> > DT
>
> This can't happen but I like to have a catch all in any case, but since
> I took yours and Geert's suggestion above this issue goes away :-)
>

Does gcc complains about the missing default case?

> >
> > > + }
> > > +
> > > + ret = rcar_csi2_calc_phypll(priv, format->bpp, );
> > > + if (ret)
> > > + return ret;
> > > +
> > > + /* Clear Ultra Low Power interrupt */
> > > + if (priv->info->clear_ulps)
> > > + rcar_csi2_write(priv, INTSTATE_REG,
> > > + INTSTATE_INT_ULPS_START |
> > > + INTSTATE_INT_ULPS_END);
> > > +
> > > + /* Init */
> > > + rcar_csi2_write(priv, TREF_REG, TREF_TREF);
> > > + rcar_csi2_reset(priv);
> > > + rcar_csi2_write(priv, PHTC_REG, 0);
> > > +
> > > + /* Configure */
> > > + rcar_csi2_write(priv, FLD_REG, FLD_FLD_NUM(2) | FLD_FLD_EN4 |
> > > + FLD_FLD_EN3 | 

Re: [PATCH qemu v3] device_tree: Increase FDT_MAX_SIZE to 1 MiB

[Peter Maydell]

On 12 April 2018 at 14:55, Geert Uytterhoeven  wrote:
> It is not uncommon for a contemporary FDT to be larger than 64 KiB,
> leading to failures loading the device tree from sysfs:
>
> qemu-system-aarch64: qemu_fdt_setprop: Couldn't set ...: FDT_ERR_NOSPACE
>
> Hence increase the limit to 1 MiB, like on PPC.
>
> For reference, the largest arm64 DTB created from the Linux sources is
> ca. 75 KiB large (100 KiB when built with symbols/fixup support).
>
> Signed-off-by: Geert Uytterhoeven 
> ---
> v3:
>   - Update example size figures,
>
> v2:
>   - Enlarge from 128 KiB to 1 MiB, as suggested by Peter Maydell.
> ---
>  device_tree.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Thanks; applied to target-arm.next for 2.13. I'll add cc:qemu-stable too.

-- PMM

Re: [PATCH v2 15/19] dt-bindings: gpio: Add support for r8a77965

[Geert Uytterhoeven]

Hi Jacopo,

On Tue, Feb 20, 2018 at 4:12 PM, Jacopo Mondi  wrote:
> Add compatible string for R-Car M3-N (r8a77965) in gpio-rcar.
>
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Geert Uytterhoeven 

Can you please resend to the GPIO maintainer?
Thanks!

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 10/19] dt-bindings: dmaengine: rcar-dmac: document R8A77965 support

[Geert Uytterhoeven]

Hi Jacopo,

On Tue, Feb 20, 2018 at 4:12 PM, Jacopo Mondi  wrote:
> Add documentation for r8a77965 compatible string to rcar-dmac device
> tree bindings documentation.
>
> Signed-off-by: Jacopo Mondi 
> Reviewed-by: Geert Uytterhoeven 
> Reviewed-by: Simon Horman 

Can you please resend to the DMA engine maintainer?
Thanks!

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v3] dmaengine: rcar-dmac: Document R-Car D3 bindings

[Geert Uytterhoeven]

Hi Uli,

On Tue, Dec 19, 2017 at 10:13 AM, Ulrich Hecht
 wrote:
> R8A77995's SYS-DMAC is R-Car Gen3-compatible.
>
> Signed-off-by: Ulrich Hecht 
> Reviewed-by: Geert Uytterhoeven 
> Reviewed-by: Simon Horman 
> ---
> This revision adds the missing Reviewed-Bys.

Can you please resend to the DMA engine and DT maintainers?
Thanks!

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Please ignore this one [Was: RE: [PATCH 1/1] arm: rzn1: Add support for the second CPU.]

[Michel Pollet]

Please ignore this one... it's rebase junk 

Michel

>
> This enables starting the second CA7 core. Also handles the case the
> bootloader has had to change the second CPU parking address to allow
> booting in NONSEC/HYP.
>
> Signed-off-by: Michel Pollet 
> ---
>  arch/arm/mach-shmobile/Makefile  |  1 +
>  arch/arm/mach-shmobile/r9a06g032.h   |  7 +++
>  arch/arm/mach-shmobile/setup-r9a06g032.c |  2 +
>  arch/arm/mach-shmobile/smp-r9a06g032.c   | 88
> 
>  4 files changed, 98 insertions(+)
>  create mode 100644 arch/arm/mach-shmobile/r9a06g032.h
>  create mode 100644 arch/arm/mach-shmobile/smp-r9a06g032.c
>
> diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-
> shmobile/Makefile index a63e5c2..e0f8c97 100644
> --- a/arch/arm/mach-shmobile/Makefile
> +++ b/arch/arm/mach-shmobile/Makefile
> @@ -36,6 +36,7 @@ smp-$(CONFIG_ARCH_R8A7779)+= smp-r8a7779.o
> headsmp-scu.o platsmp-scu.o
>  smp-$(CONFIG_ARCH_R8A7790)+= smp-r8a7790.o
>  smp-$(CONFIG_ARCH_R8A7791)+= smp-r8a7791.o
>  smp-$(CONFIG_ARCH_EMEV2)+= smp-emev2.o headsmp-scu.o
> platsmp-scu.o
> +smp-$(CONFIG_ARCH_R9A06G032)+= smp-r9a06g032.o
>
>  # PM objects
>  obj-$(CONFIG_SUSPEND)+= suspend.o
> diff --git a/arch/arm/mach-shmobile/r9a06g032.h b/arch/arm/mach-
> shmobile/r9a06g032.h
> new file mode 100644
> index 000..3992e97
> --- /dev/null
> +++ b/arch/arm/mach-shmobile/r9a06g032.h
> @@ -0,0 +1,7 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __R9A06G032_H__
> +#define __R9A06G032_H__
> +
> +extern const struct smp_operations rzn1_smp_ops;
> +
> +#endif /* __R9A06G032_H__ */
> diff --git a/arch/arm/mach-shmobile/setup-r9a06g032.c b/arch/arm/mach-
> shmobile/setup-r9a06g032.c
> index 65288e1..7bc6216 100644
> --- a/arch/arm/mach-shmobile/setup-r9a06g032.c
> +++ b/arch/arm/mach-shmobile/setup-r9a06g032.c
> @@ -11,6 +11,7 @@
>  #include 
>  #include 
>  #include 
> +#include "r9a06g032.h"
>
>  static void __iomem *sysctrl_base_addr;
>
> @@ -50,6 +51,7 @@ static const char *rzn1_boards_compat_dt[] __initconst
> = {  };
>
>  DT_MACHINE_START(RZN1_DT, "Renesas RZ/N1 (Device Tree)")
> +.smp= smp_ops(rzn1_smp_ops),
>  .dt_compat  = rzn1_boards_compat_dt,
>  .restart= rzn1_restart,
>  MACHINE_END
> diff --git a/arch/arm/mach-shmobile/smp-r9a06g032.c b/arch/arm/mach-
> shmobile/smp-r9a06g032.c
> new file mode 100644
> index 000..e441188
> --- /dev/null
> +++ b/arch/arm/mach-shmobile/smp-r9a06g032.c
> @@ -0,0 +1,88 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SMP support for Renesas RZ/N1D
> + *
> + * Copyright (C) 2018 Renesas Electronics Europe Limited
> + *
> + * Michel Pollet , 
> + *
> + * Based on code
> + *  Copyright (C) 2012-2013 Allwinner Ltd.
> + *
> + */
> +
> +#include 
> +#include 
> +#include "r9a06g032.h"
> +
> +#define BOOTADDR2_CANARY0x525a4e31
> +
> +static void __iomem *pen2_base;
> +
> +static DEFINE_SPINLOCK(cpu_lock);
> +
> +/*
> + * The alternate boot address for the second core can be overridden in
> +the DT,
> + * typically this will happen if the bootloader decides to park the
> +second
> + * core somewhere else than the fixed ALT_BOOTADDR address.
> + *
> + * This use case is required for NONSEC, as the SYSCTRL BOOTADDR
> +register isn't
> + * available after switching mode, so the bootloader parks the CPU#2 in
> +a pen
> + * is SRAM to await on an alternate address (followed by a canary) then
> +the
> + * bootloader switches mode, and finaly starts the kernel...
> + * The address of that alternate 'register' is passed in /chosen.
> + */
> +static void __init rzn1_smp_prepare_cpus(unsigned int max_cpus) {
> +u32 bootaddr = 0;
> +struct device_node *np = of_find_node_by_path("/chosen");
> +
> +if (np)
> +of_property_read_u32(np, "rzn1,bootaddr", );
> +
> +if (bootaddr &&
> +bootaddr != RZN1_SYSCTRL_REG_BOOTADDR &&
> +bootaddr !=
> (RZN1_SYSTEM_CTRL_BASE+RZN1_SYSCTRL_REG_BOOTADDR)) {
> +
> +pr_info("RZ/N1 CPU#2 boot address %08x\n", bootaddr);
> +pen2_base = ioremap(bootaddr, 8);
> +
> +if (!pen2_base)
> +pr_warn("Couldn't map RZ/N1 CPU#2 PEN2\n");
> +return;
> +}
> +pr_info("RZ/N1 CPU#2 boot address not specified - using SYSCTRL
> +reg\n"); }
> +
> +static int __init rzn1_smp_boot_secondary(unsigned int cpu,
> +struct task_struct *idle)
> +{
> +u32 t = (u32)virt_to_phys(secondary_startup);
> +
> +/* Inform on what is the second CPU boot address */
> +if (pen2_base && (readl(pen2_base + 4) == BOOTADDR2_CANARY))
> +pr_info("RZ/N1 CPU#%d writing %08x to boot address\n",
> cpu, t);
> +else
> +pr_info("RZ/N1 CPU#%d writing %08x to SYSCTRL reg\n",
> cpu, t);
> +
> +spin_lock(_lock);
> +
> +/* Set CPU boot address */
> +if (pen2_base && (readl(pen2_base + 4) == BOOTADDR2_CANARY))
> +writel(virt_to_phys(secondary_startup), pen2_base);
> +else
> +rzn1_sysctrl_writel(virt_to_phys(secondary_startup),
> +RZN1_SYSCTRL_REG_BOOTADDR);
> +
> +arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> +

[PATCH 1/1] arm: rzn1: Add support for the second CPU.

[Michel Pollet]

This enables starting the second CA7 core. Also handles the case the
bootloader has had to change the second CPU parking address to allow
booting in NONSEC/HYP.

Signed-off-by: Michel Pollet 
---
 arch/arm/mach-shmobile/Makefile  |  1 +
 arch/arm/mach-shmobile/r9a06g032.h   |  7 +++
 arch/arm/mach-shmobile/setup-r9a06g032.c |  2 +
 arch/arm/mach-shmobile/smp-r9a06g032.c   | 88 
 4 files changed, 98 insertions(+)
 create mode 100644 arch/arm/mach-shmobile/r9a06g032.h
 create mode 100644 arch/arm/mach-shmobile/smp-r9a06g032.c

diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index a63e5c2..e0f8c97 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -36,6 +36,7 @@ smp-$(CONFIG_ARCH_R8A7779)+= smp-r8a7779.o headsmp-scu.o 
platsmp-scu.o
 smp-$(CONFIG_ARCH_R8A7790) += smp-r8a7790.o
 smp-$(CONFIG_ARCH_R8A7791) += smp-r8a7791.o
 smp-$(CONFIG_ARCH_EMEV2)   += smp-emev2.o headsmp-scu.o platsmp-scu.o
+smp-$(CONFIG_ARCH_R9A06G032)   += smp-r9a06g032.o
 
 # PM objects
 obj-$(CONFIG_SUSPEND)  += suspend.o
diff --git a/arch/arm/mach-shmobile/r9a06g032.h 
b/arch/arm/mach-shmobile/r9a06g032.h
new file mode 100644
index 000..3992e97
--- /dev/null
+++ b/arch/arm/mach-shmobile/r9a06g032.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __R9A06G032_H__
+#define __R9A06G032_H__
+
+extern const struct smp_operations rzn1_smp_ops;
+
+#endif /* __R9A06G032_H__ */
diff --git a/arch/arm/mach-shmobile/setup-r9a06g032.c 
b/arch/arm/mach-shmobile/setup-r9a06g032.c
index 65288e1..7bc6216 100644
--- a/arch/arm/mach-shmobile/setup-r9a06g032.c
+++ b/arch/arm/mach-shmobile/setup-r9a06g032.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include "r9a06g032.h"
 
 static void __iomem *sysctrl_base_addr;
 
@@ -50,6 +51,7 @@ static const char *rzn1_boards_compat_dt[] __initconst = {
 };
 
 DT_MACHINE_START(RZN1_DT, "Renesas RZ/N1 (Device Tree)")
+   .smp= smp_ops(rzn1_smp_ops),
.dt_compat  = rzn1_boards_compat_dt,
.restart= rzn1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/smp-r9a06g032.c 
b/arch/arm/mach-shmobile/smp-r9a06g032.c
new file mode 100644
index 000..e441188
--- /dev/null
+++ b/arch/arm/mach-shmobile/smp-r9a06g032.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SMP support for Renesas RZ/N1D
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet , 
+ *
+ * Based on code
+ *  Copyright (C) 2012-2013 Allwinner Ltd.
+ *
+ */
+
+#include 
+#include 
+#include "r9a06g032.h"
+
+#define BOOTADDR2_CANARY   0x525a4e31
+
+static void __iomem *pen2_base;
+
+static DEFINE_SPINLOCK(cpu_lock);
+
+/*
+ * The alternate boot address for the second core can be overridden in the DT,
+ * typically this will happen if the bootloader decides to park the second
+ * core somewhere else than the fixed ALT_BOOTADDR address.
+ *
+ * This use case is required for NONSEC, as the SYSCTRL BOOTADDR register isn't
+ * available after switching mode, so the bootloader parks the CPU#2 in a pen
+ * is SRAM to await on an alternate address (followed by a canary) then the
+ * bootloader switches mode, and finaly starts the kernel...
+ * The address of that alternate 'register' is passed in /chosen.
+ */
+static void __init rzn1_smp_prepare_cpus(unsigned int max_cpus)
+{
+   u32 bootaddr = 0;
+   struct device_node *np = of_find_node_by_path("/chosen");
+
+   if (np)
+   of_property_read_u32(np, "rzn1,bootaddr", );
+
+   if (bootaddr &&
+   bootaddr != RZN1_SYSCTRL_REG_BOOTADDR &&
+   bootaddr != (RZN1_SYSTEM_CTRL_BASE+RZN1_SYSCTRL_REG_BOOTADDR)) {
+
+   pr_info("RZ/N1 CPU#2 boot address %08x\n", bootaddr);
+   pen2_base = ioremap(bootaddr, 8);
+
+   if (!pen2_base)
+   pr_warn("Couldn't map RZ/N1 CPU#2 PEN2\n");
+   return;
+   }
+   pr_info("RZ/N1 CPU#2 boot address not specified - using SYSCTRL reg\n");
+}
+
+static int __init rzn1_smp_boot_secondary(unsigned int cpu,
+   struct task_struct *idle)
+{
+   u32 t = (u32)virt_to_phys(secondary_startup);
+
+   /* Inform on what is the second CPU boot address */
+   if (pen2_base && (readl(pen2_base + 4) == BOOTADDR2_CANARY))
+   pr_info("RZ/N1 CPU#%d writing %08x to boot address\n", cpu, t);
+   else
+   pr_info("RZ/N1 CPU#%d writing %08x to SYSCTRL reg\n", cpu, t);
+
+   spin_lock(_lock);
+
+   /* Set CPU boot address */
+   if (pen2_base && (readl(pen2_base + 4) == BOOTADDR2_CANARY))
+   writel(virt_to_phys(secondary_startup), pen2_base);
+   else
+   rzn1_sysctrl_writel(virt_to_phys(secondary_startup),
+   

[RFC 1/3] dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method.

[Michel Pollet]

Add a special enable method for second CA8 of the Renesas RZ/N1D
(R9A06G032).

Signed-off-by: Michel Pollet 
---
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt 
b/Documentation/devicetree/bindings/arm/cpus.txt
index 29e1dc5..b395d107 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -219,6 +219,7 @@ described below.
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"renesas,apmu"
+   "renesas,r9a06g032-smp"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"
-- 
2.7.4

[RFC 2/3] ARM: dts: Renesas RZ/N1D SMP enable method

[Michel Pollet]

Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.

Signed-off-by: Michel Pollet 
---
 arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 7d84b38..50f3043d 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -33,6 +33,8 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <1>;
+   enable-method = "renesas,r9a06g032-smp";
+   cpu-release-addr = <0x4000c204>;
};
};
 
-- 
2.7.4

[RFC 3/3] arm: shmobile: Add the RZ/N1D SMP enabler driver.

[Michel Pollet]

The Renesas RZ/N1D second CA7 is parked in a ROM pen at boot time, it
requires a special enable method to get it started at boot time.

Signed-off-by: Michel Pollet 
---
 arch/arm/mach-shmobile/Makefile|  1 +
 arch/arm/mach-shmobile/smp-r9a06g032.c | 87 ++
 2 files changed, 88 insertions(+)
 create mode 100644 arch/arm/mach-shmobile/smp-r9a06g032.c

diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 1939f52..d7fc98f 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -34,6 +34,7 @@ smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o 
platsmp-scu.o
 smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o
 smp-$(CONFIG_ARCH_R8A7790) += smp-r8a7790.o
 smp-$(CONFIG_ARCH_R8A7791) += smp-r8a7791.o
+smp-$(CONFIG_ARCH_R9A06G032)   += smp-r9a06g032.o
 smp-$(CONFIG_ARCH_EMEV2)   += smp-emev2.o headsmp-scu.o platsmp-scu.o
 
 # PM objects
diff --git a/arch/arm/mach-shmobile/smp-r9a06g032.c 
b/arch/arm/mach-shmobile/smp-r9a06g032.c
new file mode 100644
index 000..59ec287
--- /dev/null
+++ b/arch/arm/mach-shmobile/smp-r9a06g032.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/N1D Second CA7 enabler.
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet , 
+ * Derived from action,s500-smp
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * The second CPU is parked in ROM at boot time. It requires waking it after
+ * writing an address into the BOOTADDR register of sysctrl.
+ *
+ * So the default value of the "cpu-release-addr" corresponds to BOOTADDR...
+ *
+ * *However* the BOOTADDR register is not available when the kernel
+ * starts in NONSEC mode.
+ *
+ * So for NONSEC mode, the bootloader re-parks the second CPU into a pen
+ * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address,
+ * which is not restricted.
+ */
+
+static void __iomem *cpu_bootaddr;
+
+static DEFINE_SPINLOCK(cpu_lock);
+
+static int rzn1_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+   if (!cpu_bootaddr)
+   return -ENODEV;
+
+   spin_lock(_lock);
+
+   writel(virt_to_phys(secondary_startup), cpu_bootaddr);
+   arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+   spin_unlock(_lock);
+
+   return 0;
+}
+
+static void __init rzn1_smp_prepare_cpus(unsigned int max_cpus)
+{
+   struct device_node *dn;
+   int ret;
+   u32 bootaddr;
+
+   dn = of_get_cpu_node(1, NULL);
+   if (!dn) {
+   pr_err("CPU#1: missing device tree node\n");
+   return;
+   }
+   /*
+* Determine the address from which the CPU is polling.
+*/
+   ret = of_property_read_u32(dn, "cpu-release-addr", );
+   if (ret)
+   pr_err("CPU#1: invalid cpu-release-addr property\n");
+
+   of_node_put(dn);
+   /* The bootloader *does* change this property */
+   pr_info("CPU#1: cpu-release-addr %08x\n", (u32)bootaddr);
+
+   if (!bootaddr)
+   return;
+
+   cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr));
+   if (!cpu_bootaddr)
+   pr_err("CPU#1: cpu-release-addr map failed\n");
+}
+
+static const struct smp_operations rzn1_smp_ops __initconst = {
+   .smp_prepare_cpus = rzn1_smp_prepare_cpus,
+   .smp_boot_secondary = rzn1_smp_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(rzn1_smp, "renesas,r9a06g032-smp", _smp_ops);
-- 
2.7.4

[RFC 0/3] Renesas RZ/N1D SMP enabler

[Michel Pollet]

*Warning -- this requires the base RZ/N1 support patches already posted *

This is a tentative patch series for enabling the second CA7 of the RZ/N1D.
It's based on a spin_table method, and it reuses the same binding property
as that driver.

One question is: Do i have to document it separately, or is it sufficiently
clear?

Michel Pollet (3):
  dt-bindings: cpu: Add Renesas RZ/N1D SMP enable method.
  ARM: dts: Renesas RZ/N1D SMP enable method
  arm: shmobile: Add the RZ/N1D SMP enabler driver.

 Documentation/devicetree/bindings/arm/cpus.txt |  1 +
 arch/arm/boot/dts/r9a06g032.dtsi   |  2 +
 arch/arm/mach-shmobile/Makefile|  1 +
 arch/arm/mach-shmobile/smp-r9a06g032.c | 87 ++
 4 files changed, 91 insertions(+)
 create mode 100644 arch/arm/mach-shmobile/smp-r9a06g032.c

-- 
2.7.4

Re: [PATCH v13 2/2] rcar-csi2: add Renesas R-Car MIPI CSI-2 receiver driver

[Sakari Ailus]

Hi Niklas,

On Sun, Apr 15, 2018 at 10:47:37PM +0200, Niklas Söderlund wrote:
> Hi Sakari,
> 
> Thanks for your feedback.
> 
> On 2018-04-04 23:13:57 +0300, Sakari Ailus wrote:
> 
> [snip]
> 
> > > > +   pm_runtime_enable(>dev);
> > > 
> > > Is CONFIG_PM mandatory on Renesas SoCs? If not, you end up with the
> > > device uninitialised at probe, and pm_runtime_get_sync will not
> > > initialise it either if CONFIG_PM is not enabled. I guess you could
> > > call your runtime_resume function unconditionally, and mark the device
> > > as active in runtime_pm using pm_runtime_set_active.
> > 
> > There doesn't seem to be any runtime_resume function. Was there supposed
> > to be one?
> 
> No there is not suppose to be one.

Ok.

> 
> > 
> > Assuming runtime PM would actually do something here, you might add
> > pm_runtime_idle() to power the device off after probing.
> > 
> > I guess pm_runtime_set_active() should precede pm_runtime_enable().
> 
> The CSI-2 is in the always on power domain so the calls to 
> pm_runtime_get_sync() and pm_runtime_put() are there in the s_stream() 
> callback to enable and disable the module clock. I'm no expert on PM but 
> in my testing the pm_ calls in this driver seems to be correct.
> 
> 1. In probe I call pm_runtime_enable(). And rudimentary tests shows the 
>clock is off (but I might miss something) as I wish it to be until 
>stream on time.
> 2. In s_stream() I call pm_runtime_get_sync() before writing any 
>register when starting a stream. And likewise I call pm_runtime_put() 
>when stopping and I no longer need to write to a register.
> 3. In remove() I call pm_runtime_disable().
> 
> Am I missing something obvious here?

Looking at the code again, it seems fine in this respect.

-- 
Sakari Ailus
e-mail: sakari.ai...@iki.fi

Re: [PATCH v2 1/2] pinctrl: sh-pfc: Add r8a77470 PFC support

[Geert Uytterhoeven]

Hi Biju,

On Wed, Apr 4, 2018 at 5:22 PM, Biju Das  wrote:
> Add PFC support for the R8A77470 SoC including pin groups for
> some on-chip devices such as SCIF, AVB and MMC.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 

Thanks for your patch!

> --- /dev/null
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c
> @@ -0,0 +1,2156 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * R8A77470 processor support - PFC hardware block.
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +
> +#include 
> +
> +#include "sh_pfc.h"
> +
> +#define CPU_ALL_PORT(fn, sfx)  \
> +   PORT_GP_23(0, fn, sfx), \
> +   PORT_GP_23(1, fn, sfx), \
> +   PORT_GP_32(2, fn, sfx), \
> +   PORT_GP_17(3, fn, sfx), \
> +   PORT_GP_1(3, 27, fn, sfx),  \
> +   PORT_GP_1(3, 28, fn, sfx),  \
> +   PORT_GP_1(3, 29, fn, sfx),  \

(Oh, they have a hole in the GPIO range...)

> +   PORT_GP_26(4, fn, sfx), \
> +   PORT_GP_32(5, fn, sfx)

> +/* - AVB 
>  */
> +static const unsigned int avb_link_pins[] = {
> +   RCAR_GP_PIN(5, 14),
> +};
> +static const unsigned int avb_link_mux[] = {
> +   AVB_LINK_MARK,
> +};
> +static const unsigned int avb_magic_pins[] = {
> +   RCAR_GP_PIN(5, 15),
> +};
> +static const unsigned int avb_magic_mux[] = {
> +   AVB_MAGIC_MARK,
> +};
> +static const unsigned int avb_phy_int_pins[] = {
> +   RCAR_GP_PIN(5, 16),
> +};
> +static const unsigned int avb_phy_int_mux[] = {
> +   AVB_PHY_INT_MARK,
> +};
> +static const unsigned int avb_mdio_pins[] = {
> +   RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
> +};
> +static const unsigned int avb_mdio_mux[] = {
> +   AVB_MDC_MARK, AVB_MDIO_MARK,
> +};
> +static const unsigned int avb_mii_pins[] = {
> +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
> +   RCAR_GP_PIN(3, 27),
> +
> +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
> +   RCAR_GP_PIN(3, 5),
> +
> +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
> +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23),
> +   RCAR_GP_PIN(3, 12),
> +};
> +static const unsigned int avb_mii_mux[] = {
> +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
> +   AVB_TXD3_MARK,
> +
> +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
> +   AVB_RXD3_MARK,
> +
> +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
> +   AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
> +   AVB_TX_CLK_MARK,

You forgot AVB_COL, which is GP5_18?

> +};
> +static const unsigned int avb_gmii_pins[] = {
> +   RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
> +   RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
> +   RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22),
> +
> +   RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
> +   RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
> +   RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
> +
> +   RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
> +   RCAR_GP_PIN(5, 17), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11),
> +   RCAR_GP_PIN(3, 13), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(3, 12),
> +};
> +static const unsigned int avb_gmii_mux[] = {
> +   AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
> +   AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
> +   AVB_TXD6_MARK, AVB_TXD7_MARK,
> +
> +   AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
> +   AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
> +   AVB_RXD6_MARK, AVB_RXD7_MARK,
> +
> +   AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
> +   AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
> +   AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,

You forgot AVB_COL, which is GP5_18?

> +};

Any specific reason you haven't added the avb_avtp_capture and
avb_avtp_match pins?

> +/* - SCIF1 
> -- */
> +static const unsigned int scif1_data_b_pins[] = {
> +   /* RX, TX */
> +   RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
> +};
> +static const unsigned int scif1_data_b_mux[] = {
> +   RX1_B_MARK, TX1_B_MARK,
> +};
> +/* - SCIF2 
> -- */
> +static const unsigned int scif2_data_b_pins[] = {
> +   /* RX, TX */
> +   RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
> +};
> +static const unsigned int scif2_data_b_mux[] = {
> +   RX2_B_MARK, TX2_B_MARK,
> +};
> +/* - SCIF4 
> 

Re: [PATCH RESEND] backlight: pwm_bl: don't use GPIOF_* with gpiod_get_direction

[Lee Jones]

On Wed, 11 Apr 2018, Simon Horman wrote:

> On Tue, Apr 10, 2018 at 02:32:40PM +0200, Wolfram Sang wrote:
> > The documentation was wrong, gpiod_get_direction() returns 0/1 instead
> > of the GPIOF_* flags. The docs were fixed with commit 94fc73094abe47
> > ("gpio: correct docs about return value of gpiod_get_direction"). Now,
> > fix this user (until a better, system-wide solution is in place).
> > 
> > Signed-off-by: Wolfram Sang 
> > Acked-by: Daniel Thompson 
> 
> Reviewed-by: Simon Horman 

Thanks for the Reviewed-by Simon.  I have applied it to the original mail.

Do you know why you mail wasn't sent attached to the original thread?
For some reason I received this mail on it's own i.e. not in reply
to the original.

> > ---
> > 
> > Changes since V1:
> > * rebased to top-of-linus-tree
> > * added tag from Daniel, thanks!
> > 
> > Through which tree does this need to go?
> > 
> >  drivers/video/backlight/pwm_bl.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/video/backlight/pwm_bl.c 
> > b/drivers/video/backlight/pwm_bl.c
> > index 1c2289ddd555..0fa7d2bd0e48 100644
> > --- a/drivers/video/backlight/pwm_bl.c
> > +++ b/drivers/video/backlight/pwm_bl.c
> > @@ -301,14 +301,14 @@ static int pwm_backlight_probe(struct platform_device 
> > *pdev)
> >  
> > /*
> >  * If the GPIO is not known to be already configured as output, that
> > -* is, if gpiod_get_direction returns either GPIOF_DIR_IN or -EINVAL,
> > -* change the direction to output and set the GPIO as active.
> > +* is, if gpiod_get_direction returns either 1 or -EINVAL, change the
> > +* direction to output and set the GPIO as active.
> >  * Do not force the GPIO to active when it was already output as it
> >  * could cause backlight flickering or we would enable the backlight too
> >  * early. Leave the decision of the initial backlight state for later.
> >  */
> > if (pb->enable_gpio &&
> > -   gpiod_get_direction(pb->enable_gpio) != GPIOF_DIR_OUT)
> > +   gpiod_get_direction(pb->enable_gpio) != 0)
> > gpiod_direction_output(pb->enable_gpio, 1);
> >  
> > pb->power_supply = devm_regulator_get(>dev, "power");

-- 
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH 3/3] backlight: pwm_bl: don't use GPIOF_* with gpiod_get_direction

[Lee Jones]

On Sun, 14 Jan 2018, Wolfram Sang wrote:

> The documentation was wrong, gpiod_get_direction() returns 0/1 instead
> of the GPIOF_* flags. The docs were fixed with commit 94fc73094abe47
> ("gpio: correct docs about return value of gpiod_get_direction"). Now,
> fix this user (until a better, system-wide solution is in place).
> 
> Signed-off-by: Wolfram Sang 
> ---
> Only build tested!
> 
>  drivers/video/backlight/pwm_bl.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Applied with Daniel and Simon's Acks.

-- 
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v2 2/2] dt-bindings: pinctrl: sh-pfc: Document r8a77470 PFC support

[Geert Uytterhoeven]

On Wed, Apr 4, 2018 at 5:22 PM, Biju Das  wrote:
> Document PFC support for the R8A77470 SoC.
>
> Signed-off-by: Biju Das 
> Reviewed-by: Fabrizio Castro 
> ---
> V1->V2:
> * Incorporated sergie's review comment.

Reviewed-by: Geert Uytterhoeven 
I.e. will queue in sh-pfc-for-v4.18.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] spi: sh-msiof: Add spi_master_suspend/spi_master_resume

[Geert Uytterhoeven]

On Fri, Apr 13, 2018 at 7:28 PM, Wolfram Sang  wrote:
>> + struct platform_device *pdev = to_platform_device(dev);
>> + struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
>
> struct sh_msiof_spi_priv *p = dev_get_drvdata(dev);

With Wolfram's comment taken into account:
Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds