On Tue, Sep 18, 2018 at 10:05 PM Souptick Joarder wrote:
>
> convert drm_atomic_helper_suspend/resume() to use
> drm_mode_config_helper_suspend/resume().
>
> remove suspend_state field from the rcar_du_device
> structure as it is no more required.
>
> With this conversion, also drm_fbdev_cma_set_s
From: Andrew Lunn
Date: Mon, 24 Sep 2018 17:50:23 +0200
> I submitted it to netdev in the usual way. I hope DaveM will accept
> and merge it.
Andrew did I miss your patch somehow?
If so, sorry, please resend.
On 25 September 2018 at 19:27, Biju Das wrote:
> Add support for r8a7744 SoC. Renesas RZ/G1N (R8A7744) MMCIF is identical
> to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/binding
On 25 September 2018 at 19:23, Biju Das wrote:
> Add support for r8a7744 SoC. Renesas RZ/G1N (R8A7744) SDHI is identical
> to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings
When adding support for parallel subdev for Gen3 it was missed that the
symbol 'i' in rvin_group_link_notify() was already declare, remove the
dupe as it's only used as a loop variable this have no functional
change. This fixes warning:
rcar-core.c:117:52: originally declared here
rcar-cor
Hello Geert,
> Subject: Re: [PATCH 1/4] dt-bindings: mmc: renesas_sdhi: Add r8a77470 support
>
> Hi Fabrizio,
>
> On Mon, Sep 24, 2018 at 8:34 PM Fabrizio Castro
> wrote:
> > > Subject: Re: [PATCH 1/4] dt-bindings: mmc: renesas_sdhi: Add r8a77470
> > > support
> > > On Fri, Sep 21, 2018 at 1:55
> On September 14, 2018 at 11:10 AM Laurent Pinchart
> wrote:
>
>
> The official way to stop the display is to clear the display enable
> (DEN) bit in the DSYSR register, but that operates at a group level and
> affects the two channels in the group. To disable channels selectively,
> the dri
> On September 14, 2018 at 11:10 AM Laurent Pinchart
> wrote:
>
>
> All Gen3 SoCs supported so far have a fixed association between DPAD0
> and DU channels, which led to hardcoding that association when writing
> the corresponding hardware register. The D3 and E3 will break that
> mechanism a
> On September 14, 2018 at 11:10 AM Laurent Pinchart
> wrote:
>
>
> Add the LVDS decoder, HDMI encoder, VGA encoder and HDMI and VGA
> connectors, and wire up the display-related nodes with clocks, pinmux
> and regulators.
>
> The LVDS0 and LVDS1 encoders can use the DU_DOTCLKIN0, DU_DOTCLKI
> On September 14, 2018 at 11:10 AM Laurent Pinchart
> wrote:
>
>
> DSYSR is a DU channel register that also contains group fields. It is
> thus written to by both the group and CRTC code, using read-update-write
> sequences. As the register isn't initialized explicitly at startup time,
> thi
> On September 14, 2018 at 11:10 AM Laurent Pinchart
> wrote:
>
>
> On selected SoCs, the DU can use the clock output by the LVDS encoder
> PLL as its input dot clock. This feature is optional, but on the D3 and
> E3 SoC it is often the only way to obtain a precise dot clock frequency,
> as t
Thank you for your patch.
> On September 14, 2018 at 11:10 AM Laurent Pinchart
> wrote:
>
>
> The rcar_du_crtc_get() function is always immediately followed by a call
> to rcar_du_crtc_setup(). Call the later from the former to simplify the
> code, and add a comment to explain how the get and
From: Masaharu Hayakawa
The initial value of the interrupt mask register may be different from
the H/W manual at the startup of the kernel by setting from the
bootloader. Since the error interrupts may be unmasked, the driver sets
initial value.
The initial value is only known for R-Car Gen2 and
Hi Rob,
CC devicetree
On Wed, Sep 26, 2018 at 4:20 PM Rob Herring wrote:
>
> DT bindings should be sent to DT list.
>
> On Wed, Sep 19, 2018 at 9:24 AM Phil Edworthy
> wrote:
> >
> > The Renesas RZ/N1 device family PINCTRL node description.
> >
> > Based on a patch originally written by Michel
Hi Kieran,
Thanks for your comment.
On 2018-09-24 15:39:15 +0100, Kieran Bingham wrote:
> Hi Niklas,
>
> On 23/08/18 14:25, Niklas Söderlund wrote:
> > The driver can now access frame descriptor information, use it when
> > configuring the CSI-2 bus. Only enable the virtual channels which are
>
DT bindings should be sent to DT list.
On Wed, Sep 19, 2018 at 9:24 AM Phil Edworthy wrote:
>
> The Renesas RZ/N1 device family PINCTRL node description.
>
> Based on a patch originally written by Michel Pollet at Renesas.
>
> Signed-off-by: Phil Edworthy
> ---
> v4:
> - Add alternative way to
Hi Kieran,
On 2018-09-26 14:49:22 +0100, Kieran Bingham wrote:
> Hi Niklas,
>
> On 18/09/18 02:45, Niklas Söderlund wrote:
> > Fix copy-and-past error in comment for TXB CSI-2 transmitter power down
> > sequence.
> >
>
> I have collected this patch into my adv748x/for-next branch (and fixed
> t
Hi Niklas,
On 18/09/18 02:45, Niklas Söderlund wrote:
> Fix copy-and-past error in comment for TXB CSI-2 transmitter power down
> sequence.
>
I have collected this patch into my adv748x/for-next branch (and fixed
the typo in "copy-and-past" and submitted as a pull request for Hans and
Mauro.
--
On Wed, Sep 26, 2018 at 3:40 PM Chris Brandt wrote:
> Add RSPI clocks for RZ/A2.
>
> Signed-off-by: Chris Brandt
Reviewed-by: Geert Uytterhoeven
i.e. will queue in clk-renesas-for-v4.20.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond i
Hi Jacopo,
On 17/09/18 12:30, Jacopo Mondi wrote:
> Hello Laurent, Kieran, Niklas,
>to address the Ebisu board use case, this series allows the adv748x driver
> to probe with a single output connection defined.
>
> Compared to v2, I have dropped the last patch, as without any dynamic routing
Hi Hans, Mauro,
Please consider including these updates for linux-media
--
Regards
Kieran
The following changes since commit 4158757395b300b6eb308fc20b96d1d231484413:
media: davinci: Fix implicit enum conversion warning (2018-09-24 09:43:13
-0400)
are available in the Git repository at:
Renesas RZ/G SoCs are pin compatible with R-Car SoCs, but lack several
automotive-specific peripherals.
Currently pin groups and functions for automotive-specific peripherals
are grouped in arrays named after the automative SoC part numbers.
Rename them to "automotive" for clarity and consistency.
Add RSPI clocks for RZ/A2.
Signed-off-by: Chris Brandt
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c
b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index d8ff4cb0defc..5135f13ec628 100644
--- a/drivers/clk/rene
Hi Thomas,
On Wednesday, 26 September 2018 15:26:38 EEST Thomas Zimmermann wrote:
> Hi,
>
> thanks for reviewing the patch and the one for rcar-du. Please also add
> them to your tree.
I took both patches in my tree. Thank you.
> Am 26.09.18 um 14:14 schrieb Kieran Bingham:
> > On 26/09/18 12:5
Hi Geert,
On Wednesday, September 26, 2018, Geert Uytterhoeven wrote:
> > +/* The clock dividers in the table vary based on DT and register
> settings */
> > +static void r7s9210_update_clk_table(struct clk *extal_clk, void
> __iomem *base)
>
> Can be __init.
>
> Reviewed-by: Geert Uytterhoeven
Hi Geert
On Wednesday, September 26, 2018, Geert Uytterhoeven wrote:
> Thanks for the update!
> Works fine on R-Car Gen2 and Gen3.
Thank you for checking!
> > struct clk **clks;
>
> In v1, you initialized clks to NULL, which was needed ...
~~~
> > + priv->base = of_iomap(np, 0);
Hi,
thanks for reviewing the patch and the one for rcar-du. Please also add
them to your tree.
Best regards
Thomas
Am 26.09.18 um 14:14 schrieb Kieran Bingham:
> Hi Thomas,
>
> Thank you for the patch,
>
> On 26/09/18 12:55, Thomas Zimmermann wrote:
>> This patch unifies the naming of DRM func
Hi Thomas,
Thank you for the patch,
On 26/09/18 12:55, Thomas Zimmermann wrote:
> This patch unifies the naming of DRM functions for reference counting
> of struct drm_device. The resulting code is more aligned with the rest
> of the Linux kernel interfaces.
>
> Signed-off-by: Thomas Zimmermann
Hi Thomas,
Thank you for the patch,
On 26/09/18 12:53, Thomas Zimmermann wrote:
> This patch unifies the naming of DRM functions for reference counting
> of struct drm_device. The resulting code is more aligned with the rest
> of the Linux kernel interfaces.> Signed-off-by: Thomas Zimmermann
>
This patch unifies the naming of DRM functions for reference counting
of struct drm_device. The resulting code is more aligned with the rest
of the Linux kernel interfaces.
Signed-off-by: Thomas Zimmermann
Reviewed-by: Simon Horman
---
drivers/gpu/drm/shmobile/shmob_drm_drv.c | 4 ++--
1 file c
Hello Geert,
> From: devicetree-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Geert Uytterhoeven
> Sent: 26 September 2018 12:41
>
> Hi Chris,
>
> On Wed, Sep 26, 2018 at 12:01 PM Chris Paterson
> wrote:
> > Update the model string for this platform configuration and fix the
> > gr
This patch unifies the naming of DRM functions for reference counting
of struct drm_device. The resulting code is more aligned with the rest
of the Linux kernel interfaces.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/rcar-du/rcar_du_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deleti
Hi Phil,
On Wed, Sep 26, 2018 at 11:11 AM Phil Edworthy
wrote:
> This implements the pinctrl driver for the RZ/N1 family of devices, including
> the R9A06G032 (RZ/N1D) device.
>
> This series was originally written by Michel Pollet whilst at Renesas, and I
> have taken over this work.
>
> Main ch
On Wed, Sep 26, 2018 at 11:11 AM Phil Edworthy
wrote:
> This provides a pinctrl driver for the Renesas R9A06G032 SoC
>
> Based on a patch originally written by Michel Pollet at Renesas.
>
> Signed-off-by: Phil Edworthy
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Hi Chris,
On Wed, Sep 26, 2018 at 12:01 PM Chris Paterson
wrote:
> Update the model string for this platform configuration and fix the
> grammar at the same time.
>
> This brings the syntax in line with the RZ/G1E iWave board.
>
> Signed-off-by: Chris Paterson
> ---
> Perhaps this patch isn't re
On Wed, Sep 26, 2018 at 10:28 AM Biju Das wrote:
> Document the iW-RainboW-G20M-RZ/G1N Qseven device tree bindings,
> listing it as a supported system on module.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
> ---
> iWave uses the same "iW-RainboW-G
On Tue, Sep 25, 2018 at 7:34 PM Biju Das wrote:
> Add support for r8a7744 SoC. Renesas RZ/G1N (R8A7744) MMCIF is identical
> to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
-
On Tue, Sep 25, 2018 at 7:30 PM Biju Das wrote:
> Add support for r8a7744 SoC. Renesas RZ/G1N (R8A7744) SDHI is identical
> to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
On Tue, Sep 25, 2018 at 7:25 PM Biju Das wrote:
> Document SoC specific compatible strings for r8a7744. No driver change
> is needed as the fallback strings will activate the right code.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}
On Tue, Sep 25, 2018 at 7:14 PM Biju Das wrote:
> RZ/G1N (R8A7744) watchdog implementation is compatible with R-Car
> Gen2, therefore add relevant documentation.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
On Tue, Sep 25, 2018 at 7:08 PM Biju Das wrote:
> Add thermal sensor support for r8a7744 SoC. The Renesas RZ/G1N
> (r8a7744) thermal sensor module is identical to the R-Car Gen2 family.
>
> No driver change is needed due to the fallback compatible value
> "renesas,rcar-gen2-thermal".
>
> Signed-of
On Tue, Sep 25, 2018 at 7:03 PM Biju Das wrote:
> Document RZ/G1N (R8A7744) SoC bindings.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
Document the iW-RainboW-G20D-Qseven-RZG1N device tree bindings,
listing it as a supported board.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
*) This patch is tested against linux-next and depend upon the below patch
https://patchwork.kernel.org/patch/10615399/
*) Details of this b
Hi,
I would like to stop accepting non-bug-fix patches for v4.20 and get
the last pull requests posted by the end of this week. This is in order
for them to be sent before the release of v4.19-rc6, the deadline set by the
ARM SoC maintainers. As patches should ideally progress from the renesas
tr
On Mon, Sep 24, 2018 at 02:26:25PM +0200, Simon Horman wrote:
> On Thu, Jul 26, 2018 at 05:39:50AM +0900, Yoshihiro Kaneko wrote:
> > From: Takeshi Kihara
> >
> > Based on a similar patch of the R8A7796 device tree
> > by Kuninori Morimoto .
> >
> > Signed-off-by: Takeshi Kihara
> > Signed-off-
On Wed, Sep 26, 2018 at 12:46:12PM +0300, Sergei Shtylyov wrote:
> On 9/26/2018 12:13 PM, Simon Horman wrote:
>
> > > > From: Kieran Bingham
> > > >
> > > > The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
> > > >
> > > > Signed-off-by: Kieran Bingham
> > > > [uli: moved lvds*
> Subject: [PATCH] ARM: dts: iwg20d-q7-dbcm-ca: Improve model string
>
> Update the model string for this platform configuration and fix the
> grammar at the same time.
>
> This brings the syntax in line with the RZ/G1E iWave board.
>
> Signed-off-by: Chris Paterson
Reviewed-by: Fabrizio Castro
Update the model string for this platform configuration and fix the
grammar at the same time.
This brings the syntax in line with the RZ/G1E iWave board.
Signed-off-by: Chris Paterson
---
Perhaps this patch isn't really needed, but the current string annoys me.
Patch applies cleanly to renesas-
On 9/26/2018 12:13 PM, Simon Horman wrote:
From: Kieran Bingham
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham
[uli: moved lvds* into the soc node, added PM domains, resets]
Signed-off-by: Ulrich Hecht
Reviewed-by: Laurent Pinchart
Tested-by
Hi Morimoto-san,
Thank you for the patch.
> Subject: [PATCH resend] can: rcar_can: convert to SPDX identifiers
>
>
> From: Kuninori Morimoto
>
> This patch updates license to use SPDX-License-Identifier
> instead of verbose license text.
>
> Signed-off-by: Kuninori Morimoto
> Reviewed-by: S
On Mon, Sep 24, 2018 at 6:50 PM Chris Brandt wrote:
> Same functionality, just easier to read.
>
> Signed-off-by: Chris Brandt
> ---
> drivers/clk/renesas/r7s9210-cpg-mssr.c | 94
> ++
> 1 file changed, 49 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/c
On Mon, Sep 24, 2018 at 6:50 PM Chris Brandt wrote:
> The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the
> ostm module clocks to be registers early in boot.
>
> Signed-off-by: Chris Brandt
> ---
> v2:
> * List early clocks first
> * Remove unnecessary comments
> * Removed
Hi Chris,
On Mon, Sep 24, 2018 at 6:50 PM Chris Brandt wrote:
> Add support for SoCs that need to register core and module clocks early in
> order to use OF drivers that exclusively use macros such as
> TIMER_OF_DECLARE.
>
> Signed-off-by: Chris Brandt
> ---
> v2:
> * List early clocks first
>
On Tue, Sep 25, 2018 at 07:33:33PM +0300, Laurent Pinchart wrote:
> Hello,
>
> The patches in this series enable display support for the D3 and E3 SoCs, on
> the Draak and Ebisu boards respectively. They were previously part of the
> "[PATCH v2 00/16] R-Car D3/E3 display support (with LVDS PLL)" s
On Wed, Sep 26, 2018 at 11:27:53AM +0300, Sergei Shtylyov wrote:
> On 9/25/2018 7:33 PM, Laurent Pinchart wrote:
>
> > From: Kieran Bingham
> >
> > The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
> >
> > Signed-off-by: Kieran Bingham
> > [uli: moved lvds* into the soc node, a
This provides a pinctrl driver for the Renesas RZ/N1 device family.
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy
Reviewed-by: Jacopo Mondi
---
v5:
- Address Jacopo's comments
- Address Geert's comments
v4:
- Address Jacopo's comments
- Imple
This provides a pinctrl driver for the Renesas R9A06G032 SoC
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy
---
v5:
- No changes.
v4:
- No changes.
v3:
- No changes.
v2:
- Add "renesas,rzn1-pinctrl" compatible fallback string
- Register size
The Renesas RZ/N1 device family PINCTRL node description.
Based on a patch originally written by Michel Pollet at Renesas.
Signed-off-by: Phil Edworthy
Reviewed-by: Jacopo Mondi
---
v5:
- 'Optional generic properties' => 'Optional generic pinconf properties'
v4:
- Add alternative way to use
This implements the pinctrl driver for the RZ/N1 family of devices, including
the R9A06G032 (RZ/N1D) device.
This series was originally written by Michel Pollet whilst at Renesas, and I
have taken over this work.
Main changes:
v5:
- Address Jacopo's further comments
- Address Geert's comments
On Tue, Sep 25, 2018 at 06:01:04PM +0100, Biju Das wrote:
> Add thermal sensor support for r8a7744 SoC. The Renesas RZ/G1N
> (r8a7744) thermal sensor module is identical to the R-Car Gen2 family.
>
> No driver change is needed due to the fallback compatible value
> "renesas,rcar-gen2-thermal".
>
On Tue, Sep 25, 2018 at 06:27:24PM +0100, Biju Das wrote:
> Add support for r8a7744 SoC. Renesas RZ/G1N (R8A7744) MMCIF is identical
> to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Simon Horman
On Tue, Sep 25, 2018 at 06:23:07PM +0100, Biju Das wrote:
> Add support for r8a7744 SoC. Renesas RZ/G1N (R8A7744) SDHI is identical
> to the R-Car Gen2 family.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Simon Horman
On Tue, Sep 25, 2018 at 06:18:16PM +0100, Biju Das wrote:
> Document SoC specific compatible strings for r8a7744. No driver change
> is needed as the fallback strings will activate the right code.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Simon Horman
On Tue, Sep 25, 2018 at 06:07:21PM +0100, Biju Das wrote:
> RZ/G1N (R8A7744) watchdog implementation is compatible with R-Car
> Gen2, therefore add relevant documentation.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Simon Horman
On Tue, Sep 25, 2018 at 05:56:34PM +0100, Biju Das wrote:
> Document RZ/G1N (R8A7744) SoC bindings.
>
> Signed-off-by: Biju Das
> Reviewed-by: Chris Paterson
Reviewed-by: Simon Horman
Document the iW-RainboW-G20M-RZ/G1N Qseven device tree bindings,
listing it as a supported system on module.
Signed-off-by: Biju Das
Reviewed-by: Chris Paterson
---
iWave uses the same "iW-RainboW-G20M-Qseven" name for both
iWave-RZ/G1N and iWave-RZ/G1M Q7 SOM. Details can be found
in the below
On 9/25/2018 7:33 PM, Laurent Pinchart wrote:
From: Kieran Bingham
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham
[uli: moved lvds* into the soc node, added PM domains, resets]
Signed-off-by: Ulrich Hecht
Reviewed-by: Laurent Pinchart
Tested
Hi Joerg
> > Joerg
> >
> > 2 weeks past. resend patch
>
> I applied that patch just yesterday, didn't you get the notice about
> that?
Thanks, nice to know
On Wed, Sep 26, 2018 at 01:33:27AM +, Kuninori Morimoto wrote:
> Joerg
>
> 2 weeks past. resend patch
I applied that patch just yesterday, didn't you get the notice about
that?
Regards,
Joerg
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