IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either external crystal or from
external reference clock.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Alexey Firago <alexey_fir...@mentor.com>
Cc: Ro
Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901.
This chip has two clock inputs (external XTAL or external CLKIN), four
fractional dividers (FODs) and five clock outputs (four universal clock
outputs and one reference clock output at OUT0_SELB_I2C).
Signed-off-by: Marek Vasut
is not necessarily the case.
In case the output buffer input mux is disabled, default to input
from FOD to have some parent and don't print the warning.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
Cc: Alexey Firago <alexey_fir...@mentor.c
of doing
so. We disable the entire output buffer in the .unprepare() callback
already.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
Cc: Alexey Firago <alexey_fir...@mentor.com>
Cc: Michael Turquette <mturque...@baylibre.com&
Fix trivial typo in vc5_clk_out_unprepare() , s/Enable/Disable/ .
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
Cc: Alexey Firago <alexey_fir...@mentor.com>
Cc: Michael Turquette <mturque...@baylibre.com>
Cc: Laurent
On 06/30/2017 09:26 PM, Stephen Boyd wrote:
> On 06/29, Marek Vasut wrote:
>> @@ -549,6 +552,7 @@ static unsigned char vc5_clk_out_get_parent(struct
>> clk_hw *hw)
>>
>> dev_warn(>client->dev,
>> "Invalid clock output configur
output, while the clock input mux
output first passes through the predivider before it is fed into
the PLL.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
Cc: Alexey Firago <alexey_fir...@mentor.com>
Cc: Michael Turquette <mt
On 06/29/2017 01:38 PM, Geert Uytterhoeven wrote:
> Hi Marek,
>
> On Thu, Jun 29, 2017 at 12:18 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>> From: Marek Vasut <marek.vasut+rene...@gmail.com>
>>
>> IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fra
On 06/29/2017 01:41 PM, Geert Uytterhoeven wrote:
> Hi Marek,
>
> On Thu, Jun 29, 2017 at 12:18 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>> From: Marek Vasut <marek.vasut+rene...@gmail.com>
>>
>> Update IDT VersaClock 6 driver to support 5P49V
From: Marek Vasut <marek.vasut+rene...@gmail.com>
IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fractional dividers.
Input clock source can be taken from either external crystal or from
external reference clock.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: A
From: Marek Vasut <marek.vasut+rene...@gmail.com>
Split the VC5 clock input mux and the predivider to more accurately
model the hardware and fix the previously incorrect assumption that
both the OUT_SEL_I2CB and the PLL are fed from the predivider.
It is in fact the clock input mux output
From: Marek Vasut <marek.vasut+rene...@gmail.com>
The VersaClock 6 has an input frequency doubler between the input
clock mux and the predivider. Add new capability flag and support
for this frequency doubler block into the driver.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmai
From: Marek Vasut <marek.vasut+rene...@gmail.com>
The output buffer input mux can be configured in either of three
states -- disabled, input from FOD, input from previous output.
Once the .prepare() callback of the output buffer is called, the
output buffer input mux must be set to either
From: Marek Vasut <marek.vasut+rene...@gmail.com>
Update IDT VersaClock 6 driver to support 5P49V6901. This chip has
two clock inputs (external XTAL or external CLKIN), four fractional
dividers (FODs) and five clock outputs (four universal clock outputs
and one reference clock
From: Marek Vasut <marek.vasut+rene...@gmail.com>
The output buffer input mux can be configured in either of three
states -- disabled, input from FOD, input from previous output.
If the output buffer input mux is set to disabled, the code in
vc5_clk_out_get_parent() would consider this an i
From: Marek Vasut <marek.vasut+rene...@gmail.com>
Fix trivial typo in vc5_clk_out_unprepare() , s/Enable/Disable/ .
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
Cc: Alexey Firago <alexey_fir...@mentor.com>
Cc: Mi
From: Marek Vasut <marek.vasut+rene...@gmail.com>
In case the initial values of the FOD registers are not configured in
the OTP or by the bootloader, it is possible that the FOD registers
will contain zeroes. The code in vc5_fod_recalc_rate() immediately
feeds the FOD divider value obtaine
On 05/02/2017 02:18 PM, Marek Vasut wrote:
> Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
> entry. The MFD part only specifies the regmap bits for the PMIC and
> binds the subdevs together.
>
> Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.co
Add DT bindings for the ROHM BD9571MWV-M PMIC. This PMIC has
the following features:
- multiple voltage monitors for 1V8, 2V5, 3V3 voltage rail
- one voltage regulator for DVFS
- two GPIOs
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: devicet...@vger.kernel.org
Cc: Rob Herr
Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
entry. The MFD part only specifies the regmap bits for the PMIC and
binds the subdevs together.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-ker...@vger.kernel.org
Cc: Geert Uytterhoeven <g
On 04/25/2017 11:32 AM, Linus Walleij wrote:
> On Mon, Apr 24, 2017 at 5:21 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>
>> Add driver for the GPIO block in the ROHM BD9571MWV-W MFD PMIC.
>> This block is pretty trivial and supports setting GPIO direction
>&g
On 04/26/2017 12:31 AM, Mark Brown wrote:
> On Tue, Apr 25, 2017 at 08:32:10PM +0200, Marek Vasut wrote:
>> Add driver for the regulator block in the ROHM BD9571MWV-W MFD PMIC.
>> This block supports three voltage monitors, VD18, VD25, VD33 for the
>> 1V8, 2V5, 3V3 volta
On 04/25/2017 04:01 PM, Lee Jones wrote:
> On Tue, 25 Apr 2017, Marek Vasut wrote:
>
>> On 04/25/2017 02:21 PM, Lee Jones wrote:
>>> On Tue, 25 Apr 2017, Marek Vasut wrote:
>>>
>>>> On 04/25/2017 11:32 AM, Linus Walleij wrote:
>>>>&g
Add driver for the regulator block in the ROHM BD9571MWV-W MFD PMIC.
This block supports three voltage monitors, VD18, VD25, VD33 for the
1V8, 2V5, 3V3 voltage rails and a single voltage regulator for the
DVFS rail.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: lin
Add driver for the GPIO block in the ROHM BD9571MWV-W MFD PMIC.
This block is pretty trivial and supports setting GPIO direction
as Input/Output and in case of Output, supports setting value.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-g...@vger.kernel.org
Cc:
Add DT bindings for the ROHM BD9571MWV-M PMIC. This PMIC has
the following features:
- multiple voltage monitors for 1V8, 2V5, 3V3 voltage rail
- one voltage regulator for DVFS
- two GPIOs
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: devicet...@vger.kernel.org
Cc: Rob Herr
Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
entry. The MFD part only specifies the regmap bits for the PMIC and
binds the subdevs together.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-ker...@vger.kernel.org
Cc: Geert Uytterhoeven <g
On 04/25/2017 02:21 PM, Lee Jones wrote:
> On Tue, 25 Apr 2017, Marek Vasut wrote:
>
>> On 04/25/2017 11:32 AM, Linus Walleij wrote:
>>> On Mon, Apr 24, 2017 at 5:21 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>>>
>>>> Add driver for
Add node for the GyroADC block and it's associated clock.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman <horms+rene...@verge.net.au>
To: linux-renesas-soc@vger.kernel.org
---
V2: - Drop the whole ad-h
Add driver for the regulator block in the ROHM BD9571MWV-W MFD PMIC.
This block supports three voltage monitors, VD18, VD25, VD33 for the
1V8, 2V5, 3V3 voltage rails and a single voltage regulator for the
DVFS rail.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: lin
Add driver for the GPIO block in the ROHM BD9571MWV-W MFD PMIC.
This block is pretty trivial and supports setting GPIO direction
as Input/Output and in case of Output, supports setting value.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-g...@vger.kernel.org
Cc:
Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
entry. The MFD part only specifies the regmap bits for the PMIC and
binds the subdevs together.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-ker...@vger.kernel.org
Cc: Geert Uytterhoeven <g
Add DT bindings for the ROHM BD9571MWV-M PMIC. This PMIC has
the following features:
- multiple voltage monitors for 1V8, 2V5, 3V3 voltage rail
- one voltage regulator for DVFS
- two GPIOs
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: devicet...@vger.kernel.org
Cc: Rob Herr
On 04/20/2017 07:26 PM, Geert Uytterhoeven wrote:
> Hi Marek,
Hi!
> On Thu, Apr 20, 2017 at 5:44 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>> Add node for the GyroADC block and it's associated clock.
>>
>> Signed-off-by: Marek Vasut <marek.vasut+rene...@gma
On 04/24/2017 03:55 PM, Linus Walleij wrote:
> On Sun, Apr 16, 2017 at 8:08 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>
>> Add driver for the GPIO block in the ROHM BD9571MWV-W MFD PMIC.
>> This block is pretty trivial and supports setting GPIO direction
>&g
On 04/24/2017 01:38 PM, Lee Jones wrote:
> On Sun, 16 Apr 2017, Marek Vasut wrote:
[...]
>> +static int bd9571mwv_identify(struct bd9571mwv *bd)
>> +{
>> +struct device *dev = bd->dev;
>> +unsigned int value;
>> +int ret;
>&
On 04/21/2017 02:41 AM, Kuninori Morimoto wrote:
>
> From: Marek Vasut <marek.vasut+rene...@gmail.com>
>
> 25165f79adc76b812bfb4d8f2ab120aafb28d0e6
> ("ASoC: rsnd: enable clock-frequency for both 44.1kHz/48kHz")
> supports both 44.1kHz/48kHz clock-frequency set
h / sizeof(u32); will
>> trigger a NULL pointer dereference.
>>
>> This patch adds check for the NULL return value and propagates
>> the error into the caller of the function.
>>
>> Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
>> Cc: Geert Uy
On 04/20/2017 11:00 AM, Simon Horman wrote:
> On Tue, Apr 18, 2017 at 03:42:25PM +0200, Geert Uytterhoeven wrote:
>> On Sun, Apr 16, 2017 at 6:57 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>>> Add the GyroADC clock to the R8A7791 device tree.
>>>
>>&g
Add node for the GyroADC block and it's associated clock.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman <horms+rene...@verge.net.au>
To: linux-renesas-soc@vger.kernel.org
---
V2: - Drop the _clk su
The "if" interface clock speed is actually derived from the "fck"
block clock, as in the hardware they are the same clock. Drop the
incorrect second "if" clock and get the clock speed from "fck".
Signed-off-by: Marek Vasut <marek.vasut+rene...@gm
The "if" interface clock speed is actually derived from the "fck"
block clock, as in the hardware they are the same clock. Drop the
incorrect second "if" clock and retain only the "fck" clock.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gm
nd propagates
the error into the caller of the function.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama...@renesas.com>
Cc: Kuninori Morimoto <kuninori.morimoto...@renesas
On 04/20/2017 02:35 PM, Geert Uytterhoeven wrote:
> Hi Marek,
Hi!
> On Sun, Apr 16, 2017 at 8:07 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>> Add DT bindings for the ROHM BD9571MWV-M PMIC. This PMIC has
>> the following features:
>> - multiple voltage monitors
On 04/18/2017 07:57 PM, Mark Brown wrote:
> On Sun, Apr 16, 2017 at 08:08:01PM +0200, Marek Vasut wrote:
>
> This looks good, a couple of minor things though:
>
>> +static int bd9571mwv_regulator_is_enabled(struct regulator_dev *reg)
>> +{
>> +/* Alway
On 04/17/2017 11:19 AM, Sergei Shtylyov wrote:
> Hello!
Hi!
> On 4/16/2017 7:57 PM, Marek Vasut wrote:
>
>> Add bindings for the GyroADC block and it's associated clock.
>
>Well, I already spoke to you about the bindings on IRC...
That's fixed.
>> Signed-off-b
On 04/18/2017 03:59 PM, Geert Uytterhoeven wrote:
> Hi Marek,
Hi Geert,
> On Sun, Apr 16, 2017 at 6:57 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>> Add bindings for the GyroADC block and it's associated clock.
>
> bindings??
That's fixed...
>> --- a/
Add driver for the regulator block in the ROHM BD9571MWV-W MFD PMIC.
This block supports three voltage monitors, VD18, VD25, VD33 for the
1V8, 2V5, 3V3 voltage rails and a single voltage regulator for the
DVFS rail.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: lin
Add driver for the GPIO block in the ROHM BD9571MWV-W MFD PMIC.
This block is pretty trivial and supports setting GPIO direction
as Input/Output and in case of Output, supports setting value.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-g...@vger.kernel.org
Cc:
Add the MFD part of the ROHM BD9571MWV-M PMIC driver and MAINTAINERS
entry. The MFD part only specifies the regmap bits for the PMIC and
binds the subdevs together.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: linux-ker...@vger.kernel.org
Cc: Geert Uytterhoeven <g
Add DT bindings for the ROHM BD9571MWV-M PMIC. This PMIC has
the following features:
- multiple voltage monitors for 1V8, 2V5, 3V3 voltage rail
- one voltage regulator for DVFS
- two GPIOs
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: devicet...@vger.kernel.org
Cc: Rob Herr
Add bindings for the GyroADC block and it's associated clock.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman <horms+rene...@verge.net.au>
Cc: linux-renesas-soc@vger.kernel.org
---
arch/arm/boot/dts
Add the GyroADC clock to the R8A7791 device tree.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman <horms+rene...@verge.net.au>
Cc: linux-renesas-soc@vger.kernel.org
---
include/dt-bindings/clock/r8a779
From: Marek Vasut <marek.vasut+rene...@gmail.com>
Add DT bindings for the Renesas RCar GyroADC block. This block is
a simple 4/8-channel ADC which samples 12/15/24 bits of data every
cycle from all channels.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Geert Uytterh
From: Marek Vasut <marek.vasut+rene...@gmail.com>
Add IIO driver for the Renesas RCar GyroADC block. This block is a
simple 4/8-channel ADC which samples 12/15/24 bits of data every
cycle from all channels.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Geert Uytterh
On 01/27/2017 11:26 PM, Rob Herring wrote:
> On Tue, Jan 24, 2017 at 07:26:41PM +0100, Marek Vasut wrote:
>> Add DT bindings for the Renesas RCar GyroADC block. This block is
>> a simple 4/8-channel ADC which samples 12/15/24 bits of data every
>> cycle from all chann
Add DT bindings for the Renesas RCar GyroADC block. This block is
a simple 4/8-channel ADC which samples 12/15/24 bits of data every
cycle from all channels.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman
Add IIO driver for the Renesas RCar GyroADC block. This block is a
simple 4/8-channel ADC which samples 12/15/24 bits of data every
cycle from all channels.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman
On 01/24/2017 08:30 AM, Geert Uytterhoeven wrote:
> Hi Marek,
>
> On Tue, Jan 24, 2017 at 12:15 AM, Marek Vasut <marek.va...@gmail.com> wrote:
>> On 01/23/2017 09:41 PM, Geert Uytterhoeven wrote:
>>> On Mon, Jan 23, 2017 at 8:56 PM, Marek Vasut <marek.va...@gmail.
On 01/23/2017 09:41 PM, Geert Uytterhoeven wrote:
> Hi Marek,
>
> On Mon, Jan 23, 2017 at 8:56 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>> On 01/23/2017 06:08 PM, Rob Herring wrote:
>>> On Sat, Jan 21, 2017 at 03:42:11PM +0100, Marek Vasut wrote:
>&g
On 01/23/2017 06:08 PM, Rob Herring wrote:
> On Sat, Jan 21, 2017 at 03:42:11PM +0100, Marek Vasut wrote:
>> Add DT bindings for the Renesas RCar GyroADC block. This block is
>> a simple 4/8-channel ADC which samples 12/15/24 bits of data every
>> cycle from all channel
On 01/21/2017 02:04 PM, Jonathan Cameron wrote:
> On 15/01/17 17:05, Marek Vasut wrote:
>> Add IIO driver for the Renesas RCar GyroADC block. This block is a
>> simple 4/8-channel ADC which samples 12/15/24 bits of data every
>> cycle from all channels.
>>
>> Sig
Add IIO driver for the Renesas RCar GyroADC block. This block is a
simple 4/8-channel ADC which samples 12/15/24 bits of data every
cycle from all channels.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman
Add DT bindings for the Renesas RCar GyroADC block. This block is
a simple 4/8-channel ADC which samples 12/15/24 bits of data every
cycle from all channels.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman
On 01/21/2017 01:12 AM, Stephen Boyd wrote:
> On 01/12, Marek Vasut wrote:
>> Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These
>> chips have two clock inputs, XTAL or CLK, which are muxed into single
>> PLL/VCO input. In case of 5P49V5923, the XTAL i
On 01/15/2017 09:21 PM, Marek Vasut wrote:
> On 01/15/2017 08:53 PM, Jonathan Cameron wrote:
>> On 15/01/17 17:06, Marek Vasut wrote:
>>> On 01/15/2017 05:28 PM, Jonathan Cameron wrote:
>>>>
>>>>
>>>> On 15 January 2017 15:47:31 GMT+
On 01/15/2017 08:53 PM, Jonathan Cameron wrote:
> On 15/01/17 17:06, Marek Vasut wrote:
>> On 01/15/2017 05:28 PM, Jonathan Cameron wrote:
>>>
>>>
>>> On 15 January 2017 15:47:31 GMT+00:00, Marek Vasut <marek.va...@gmail.com>
>>> wrote:
On 01/15/2017 05:28 PM, Jonathan Cameron wrote:
>
>
> On 15 January 2017 15:47:31 GMT+00:00, Marek Vasut <marek.va...@gmail.com>
> wrote:
>> On 01/15/2017 03:05 PM, Jonathan Cameron wrote:
>>> On 15/01/17 00:14, Marek Vasut wrote:
>>>> Add
Add IIO driver for the Renesas RCar GyroADC block. This block is a
simple 4/8-channel ADC which samples 12/15/24 bits of data every
cycle from all channels.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman
On 01/15/2017 03:05 PM, Jonathan Cameron wrote:
> On 15/01/17 00:14, Marek Vasut wrote:
>> Add IIO driver for the Renesas RCar GyroADC block. This block is a
>> simple 4/8-channel ADC which samples 12/15/24 bits of data every
>> cycle from all channels.
>>
>> Sig
ses where the channel does not
>> correspond to externally available input one of the named
>> versions may be used. The number must always be specified and
>> unique to allow association with event codes. Units after
>> application of scale and offset are millivolts.
>
> So millivolts. This comes from a, perhaps ill judged, decision to match
> hwmon units were we could.
Fun, regulator framework returns values in uV to add to the chaos :)
--
Best regards,
Marek Vasut
Add IIO driver for the Renesas RCar GyroADC block. This block is a
simple 4/8-channel ADC which samples 12/15/24 bits of data every
cycle from all channels.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Geert Uytterhoeven <geert+rene...@glider.be>
Cc: Simon Horman
On 01/12/2017 09:25 AM, Geert Uytterhoeven wrote:
> Hi Marek,
Hi!
> On Thu, Jan 12, 2017 at 2:03 AM, Marek Vasut <marek.va...@gmail.com> wrote:
>> Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips.
>> These are I2C clock generators with optional clock so
On 01/12/2017 02:51 AM, Laurent Pinchart wrote:
> The clocks are generated by an I2C-controlled programmable clock
> generator.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
Reviewed-by: Marek Vasut <marek.va...@gmail.com>
> ---
>
};
>
> + {
> + status = "okay";
> +
> + clock-frequency = <10>;
> +
> + versaclock5: clock-generator@6a {
> + compatible = "idt,5p49v5923";
> + reg = <0x6a>;
> + #clock-cells = <1>;
> + clocks = <_clk>;
> + clock-names = "xin";
> + };
> +};
> +
> _sound {
> pinctrl-0 = <_pins _clk_pins>;
> pinctrl-names = "default";
>
--
Best regards,
Marek Vasut
and 5P49V5933, while
it should be easily extensible to the whole 5P49V59xx family of chips
as they are all pretty similar.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Michael Turquette <mturque...@baylibre.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
Cc: Laurent Pinchart
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips.
These are I2C clock generators with optional clock source from
either XTal or dedicated clock generator and, depending on the
model, two or more clock outputs.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Michael Tur
On 01/11/2017 05:42 PM, Laurent Pinchart wrote:
> Hi Marek,
Hi!
> On Wednesday 11 Jan 2017 16:53:53 Marek Vasut wrote:
>> On 01/11/2017 04:41 PM, Laurent Pinchart wrote:
>>> On Wednesday 11 Jan 2017 15:37:11 Marek Vasut wrote:
>>>> On 01/10/2017 07:50 PM, Ma
On 01/11/2017 04:41 PM, Laurent Pinchart wrote:
> Hi Marek,
Hi!
> Thank you for the patch.
>
> On Wednesday 11 Jan 2017 15:37:11 Marek Vasut wrote:
>> On 01/10/2017 07:50 PM, Marek Vasut wrote:
>>> Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. The
and 5P49V5933, while
it should be easily extensible to the whole 5P49V59xx family of chips
as they are all pretty similar.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Michael Turquette <mturque...@baylibre.com>
Cc: Stephen Boyd <sb...@codeaurora.org>
Cc: Laurent Pinchart
Add bindings for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips.
These are I2C clock generators with optional clock source from
either XTal or dedicated clock generator and, depending on the
model, two or more clock outputs.
Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Michael Tur
On 01/11/2017 03:41 PM, Geert Uytterhoeven wrote:
> Hi Marek,
>
> On Wed, Jan 11, 2017 at 3:32 PM, Marek Vasut <marek.va...@gmail.com> wrote:
>> On 01/11/2017 02:11 PM, Geert Uytterhoeven wrote:
>>> On Wed, Jan 11, 2017 at 1:35 PM, Marek Vasut <marek.va...@g
On 01/10/2017 07:50 PM, Marek Vasut wrote:
> Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These
> chips have two clock inputs, XTAL or CLK, which are muxed into single
> PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip
> while the 5P49V5923 requi
On 01/11/2017 09:38 AM, Geert Uytterhoeven wrote:
> Hi Marek,
Hi,
> Please CC linux-renesas-soc for drivers for (parts of) Renesas ARM SoCs.
I just registered and will CC from now on.
> On Tue, Jan 10, 2017 at 10:33 PM, Marek Vasut <marek.va...@gmail.com> wrote:
&g
On 01/10/2017 01:44 AM, Stephen Boyd wrote:
> On 01/10, Marek Vasut wrote:
>> On 01/10/2017 01:23 AM, Stephen Boyd wrote:
>>> On 01/05, Marek Vasut wrote:
>>>> On 01/05/2017 03:13 PM, Laurent Pinchart wrote:
>>>>> Hi Marek,
>>>>
>
On 01/10/2017 01:23 AM, Stephen Boyd wrote:
> On 01/05, Marek Vasut wrote:
>> On 01/05/2017 03:13 PM, Laurent Pinchart wrote:
>>> Hi Marek,
>>
>> Hi!
>>
>> [...]
>>
>>>>>>> +static unsigned long vc5_mux_recalc_rate(struct clk_h
On 01/03/2017 01:18 PM, Laurent Pinchart wrote:
> Hi Marek,
Hi,
> Thank you for the patch.
>
> On Monday 02 Jan 2017 14:46:29 Geert Uytterhoeven wrote:
>> On Wed, Dec 28, 2016 at 1:00 AM, Marek Vasut <marek.va...@gmail.com> wrote:
>>> Add driver for IDT VersaC
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