Re: [RFC 0/5] Renesas RZ series pinctrl driver

On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote: >after having discussed in great detail the RZ series per-pin PFC hardware > peculiarities, this is a proposal for a possible pin-based pin controller > driver for SoC devices of Renesas RZ family. > > This RFC

Re: [git pull] pinctrl: sh-pfc: Updates for v4.11 (take two)

On Fri, Jan 27, 2017 at 10:21 AM, Geert Uytterhoeven wrote: > The following changes since commit 0e4e4999aac16641f47699e8929693b83a7a4d64: > > pinctrl: sh-pfc: r8a7796: Add HSCIF pins, groups, and functions (2016-12-27 > 10:57:39 +0100) > > are available in the git

Re: [PATCH/RFC] iommu/dma: Per-domain flag to control size-alignment

On 30/01/17 07:20, Yoshihiro Shimoda wrote: > Hi Robin, Magnus, > >> -Original Message- >> From: Robin Murphy >> Sent: Saturday, January 28, 2017 2:38 AM >> >> Hi Magnus, >> >> On 27/01/17 06:24, Magnus Damm wrote: >>> From: Magnus Damm >>> >>> Introduce the

Re: [PATCH v7 0/2] clocksource: Add renesas-ostm timer driver

On Fri, Jan 27, 2017 at 03:02:13PM -0500, Chris Brandt wrote: > This patch set adds a new clocksource driver that uses the OS Timer > (OSTM) that exists in the R7S72100 (RZ/A1) SoC. > > The operation of the driver was tested with a simple user application > that does multiple calls to nanosleep()

Re: [RFC 0/5] Renesas RZ series pinctrl driver

Hi Tony, On 30/01/2017 16:53, Tony Lindgren wrote: * Linus Walleij [170130 05:53]: On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote: after having discussed in great detail the RZ series per-pin PFC hardware peculiarities, this is a

Re: [RFC fixes 0/2] FIX: Renesas RZ series pinctrl driver

Hi Chris, thanks for testing the series On 27/01/2017 22:09, Chris Brandt wrote: Hi Jacopo, On Friday, January 27, 2017, Jacopo Mondi wrote: Hello, sorry if I'm sending 2 patches on top of an RFC series with comments still pending, but these patches enabled me to properly test pin

RE: [RFC fixes 0/2] FIX: Renesas RZ series pinctrl driver

Hi Jacopo, On Monday, January 30, 2017, Jacopo Mondi wrote: > > Note that the I2C pin need to be configured at "bi-directional" but > > there is no way to specify that from DT, so that has to be added as a > parameter. > > That's something I would like to discuss quite soon. > One general thing

Re: [RFC 0/5] Renesas RZ series pinctrl driver

* Linus Walleij [170130 05:53]: > On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi > wrote: > > >after having discussed in great detail the RZ series per-pin PFC hardware > > peculiarities, this is a proposal for a possible pin-based pin

Re: [PATCH v2 0/3] sh_eth: E-DMAC interrupt mask cleanups

From: Sergei Shtylyov Date: Sun, 29 Jan 2017 15:06:39 +0300 >Here's a set of 3 patches against DaveM's 'net-next.git' repo. The main > goal > of this set is to stop using the bare numbers for the E-DMAC interrupt masks. > > [1/3] sh_eth: rename EESIPR

Re: [RFC 5/5] arm: dts: genmai: Add SCIF2 pin group

Hello, On Thursday 26 Jan 2017 12:51:03 Sergei Shtylyov wrote: > On 1/25/2017 9:09 PM, Jacopo Mondi wrote: > > Add TxD and RxD pin configuration for SCIF2 serial communication > > interface on r7s72100 Genmai board. > > > > Signed-off-by: Jacopo Mondi > > --- > > >

Re: [RFC 3/5] arm: dts: dt-bindings: Add Renesas RZ pinctrl header

On Thursday 26 Jan 2017 20:52:33 Geert Uytterhoeven wrote: > On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote: > > Add dt-bindings header for Renesas RZ pincontroller. > > The header defines macros for pin description and alternate function > > numbers. > > > > Signed-off-by: Jacopo Mondi

Re: [RFC fixes 1/2] arm: dts: genmai: Configure RIIC2 pins

Hi Jacopo, Thank you for the patch. On Friday 27 Jan 2017 17:47:07 Jacopo Mondi wrote: > Add pin configuration for RIIC2 pins interface. > The i2c2 is connected to internal eeprom. > > Signed-off-by: Jacopo Mondi > --- > arch/arm/boot/dts/r7s72100-genmai.dts | 8

Re: [RFC 4/5] arm: dts: r7s1000: Add pincontroller node

Hi Jacopo, Thank you for the patch. On Wednesday 25 Jan 2017 19:09:46 Jacopo Mondi wrote: > Add pincontroller node compatible with the new Renesas RZ/A1 > pincontroller driver. > > Signed-off-by: Jacopo Mondi > --- > arch/arm/boot/dts/r7s72100.dtsi | 12

Re: [RFC 0/5] Renesas RZ series pinctrl driver

Hi Geert, On Monday 30 Jan 2017 17:08:11 Geert Uytterhoeven wrote: > On Mon, Jan 30, 2017 at 2:51 PM, Linus Walleij wrote: > > On Wed, Jan 25, 2017 at 7:09 PM, Jacopo Mondi wrote: > >> after having discussed in great detail the RZ series per-pin PFC > >> hardware peculiarities, this is a proposal

RE: [RFC 4/5] arm: dts: r7s1000: Add pincontroller node

Hi Jacopo, On Monday, January 30, 2017, Laurent Pinchart wrote: > > + pinctrl: pinctrl@fcfe3000 { > > + compatible = "renesas,rza1-pinctrl"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + #pinctrl-cells = <2>; > > + > > + reg =

Re: [PATCH v2 1/4] dt-bindings: clock: renesas: cpg-mssr: Document reset control support

On Wed, Jan 25, 2017 at 10:15:00AM +0100, Geert Uytterhoeven wrote: > Document properties needed to use the Reset Control feature of the > Renesas Clock Pulse Generator / Module Standby and Software Reset > module. > > Signed-off-by: Geert Uytterhoeven > --- > v2: > -

Re: [PATCH v2 2/3] iommu/ipmmu-vmsa: Increase maximum micro-TLBS to 48

Hi Joerg, On Fri, Jan 27, 2017 at 8:47 PM, Joerg Roedel wrote: > On Mon, Jan 23, 2017 at 08:40:29PM +0900, Magnus Damm wrote: >> From: Magnus Damm >> >> Bump up the maximum numbers of micro-TLBS to 48. >> >> Each IPMMU device instance get micro-TLB

Re: [PATCH v6 2/3] mmc: sh_mobile_sdhi: explain clock bindings

On Wed, Jan 25, 2017 at 03:28:09PM -0500, Chris Brandt wrote: > In the case of a single clock source, you don't need names. However, > if the controller has 2 clock sources, you need to name them correctly > so the driver can find the 2nd one. The 2nd clock is for the internal > card detect logic.

RE: [RFC 2/5] pinctrl: rz-pfc: Add Renesas RZ/A1 pinctrl driver

Hi Jacopo, On Wednesday, January 25, 2017, Jacopo Mondi wrote: > + /* Port 5 */ > + RZ_PIN_NAME(5, 0), RZ_PIN_NAME(5, 1), RZ_PIN_NAME(5, 2), > + RZ_PIN_NAME(5, 3), RZ_PIN_NAME(5, 4), RZ_PIN_NAME(5, 5), > + RZ_PIN_NAME(5, 6), RZ_PIN_NAME(5, 7), RZ_PIN_NAME(5, 8), > +

RE: [RFC 1/5] pinctrl: rz-pfc: Add Renesas RZ pinctrl core module

Hi Jacopo, On Wednesday, January 25, 2017, Jacopo Mondi wrote: > + > + return 0; > + > +free_map: > + devm_kfree(rz_pinctrl->dev, *map); > +free_fngrps: > + devm_kfree(rz_pinctrl->dev, fngrps); > +free_pins: > + devm_kfree(rz_pinctrl->dev, mux_modes); > +

Re: [RFC 5/5] arm: dts: genmai: Add SCIF2 pin group

Hi Laurent, On Mon, Jan 30, 2017 at 7:17 PM, Laurent Pinchart wrote: > On Thursday 26 Jan 2017 12:51:03 Sergei Shtylyov wrote: >> On 1/25/2017 9:09 PM, Jacopo Mondi wrote: >> > + { >> > + pinctrl-names = "default"; >> > + pinctrl-0 = <_pins>; >> > + >> > +

RE: [RFC 0/5] Renesas RZ series pinctrl driver

On Monday, January 30, 2017, Laurent Pinchart wrote: > > It depends on the actual hardware: while per-pin settings are suitable > > for SoCs that have per-pin hardware configuration (e.g. RZ/A1), it's > > not suitable for SoCs where that's not the case, and where the > > hardware has group-wise