Hi Tomohito-san,
On Thu, May 09, 2019 at 02:45:18PM +0900, Tomohito Esaki wrote:
> Add support for the linear modifier. Since the rcar-du device supports
> only linear modifier, this driver doesn't support other modifiers.
What's the purpose of this, as it adds no new functionality to the
driver
Hi Wolfram,
On Mon, Apr 15, 2019 at 12:52 PM Wolfram Sang
wrote:
> Support an already running watchdog by checking its enable bit and set
> up the status accordingly before registering the device.
>
> Signed-off-by: Wolfram Sang
> ---
>
> This patch was tested using a Renesas Salvator XS board (
Hi Tudor,
On Thu, May 9, 2019 at 8:56 AM wrote:
> When the configuration register QUAD bit CR[1] is 1, only the WRR command
> format
> with 16 data bits may be used, WRR with 8 bits is not recognized and hence the
> FFs. You probably set quad bit in u-boot, while others don't. We can verify
> t
On Wed, May 8, 2019 at 8:27 PM Jacopo Mondi wrote:
> Add clock defintions for CMM units on Renesas R-Car Gen3 M3-W.
>
> Signed-off-by: Jacopo Mondi
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
Hi Laurent-san
> What's the purpose of this, as it adds no new functionality to the
> driver ? Why is this change needed ?
Weston compositor (v5.0.0 or later) uses the DRM API to get the
supported modifiers and determines if the sprite plane can be used by
comparing the modifiers with the client
On Wed, May 08, 2019 at 03:20:03PM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> Thanks for your patch!
>
> On Wed, May 8, 2019 at 1:56 PM Simon Horman
> wrote:
...
>
> > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > @@ -155,6 +155,7
Hi Simon,
On Thu, May 9, 2019 at 11:57 AM Simon Horman wrote:
> On Wed, May 08, 2019 at 03:20:03PM +0200, Geert Uytterhoeven wrote:
> > On Wed, May 8, 2019 at 1:56 PM Simon Horman
> > wrote:
> > > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dts
Hi, Geert,
On 05/09/2019 12:11 PM, Geert Uytterhoeven wrote:
> External E-Mail
>
>
> Hi Tudor,
>
> On Thu, May 9, 2019 at 8:56 AM wrote:
>> When the configuration register QUAD bit CR[1] is 1, only the WRR command
>> format
>> with 16 data bits may be used, WRR with 8 bits is not recognized a
Hi Tudor,
On Thu, May 9, 2019 at 12:31 PM wrote:
> On 05/09/2019 12:11 PM, Geert Uytterhoeven wrote:
> > On Thu, May 9, 2019 at 8:56 AM wrote:
> >> When the configuration register QUAD bit CR[1] is 1, only the WRR command
> >> format
> >> with 16 data bits may be used, WRR with 8 bits is not re
On Wed, May 08, 2019 at 03:40:08PM +0200, Geert Uytterhoeven wrote:
> Hi Linus,
>
> This patch series adds pins, groups and functions for the 16-Bit Timer
> Pulse Unit (TPU) outputs on the R-Car H3/M3-W/M3-N and RZ/G2M SoCs.
>
> This has been tested on the Salvator-XS development board with
Describe the dynamic power coefficient of A57 and A53 CPUs.
Based on work by Gaku Inami and others.
Signed-off-by: Simon Horman
---
v3 [Simon Horman]
* Broken out of a larger patch
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/bo
From: Dien Pham
Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.
In R-Car Gen3, IPA is supported for only one channel
(on H3/M3/M3N board, it is channel THS3). Reason:
Currently, IPA contro
1) Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.
2) Describe dynamic power coefficient of CPUs
Changes since v2:
* Break power coefficient changes into separate patch.
Dien Pham (1):
SUDMAC driver was introduced in v3.10 but was never integrated for use
by any platform. As it unused remove it.
Signed-off-by: Simon Horman
---
drivers/dma/sh/Kconfig | 6 -
drivers/dma/sh/Makefile | 1 -
drivers/dma/sh/sudmac.c | 414
includ
On Fri, Apr 26, 2019 at 05:23:43PM +0530, Vinod Koul wrote:
> On 25-04-19, 03:52, Yoshihiro Shimoda wrote:
> > Hi Geert-san,
> >
> > > From: Geert Uytterhoeven, Sent: Wednesday, April 24, 2019 9:22 PM
> > >
> > > Hi Niklas, Shimoda-san,
> > >
> > > On Thu, Apr 11, 2019 at 5:18 PM Niklas Söderlun
On Mon, Apr 29, 2019 at 05:22:09PM +0200, Geert Uytterhoeven wrote:
> ata_host_alloc() can only fail due to memory allocation failures.
> Hence there is no need to print a message, as the memory allocation core
> code already takes care of that.
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by:
Hi Tudor,
On 09/05/19 4:01 PM, tudor.amba...@microchip.com wrote:
[...]
>>
>>> --- a/drivers/mtd/spi-nor/spi-nor.c
>>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>>
>>> +static int spi_nor_clear_block_protection(struct spi_nor *nor)
>>> +{
>>> + int ret;
>>> + u8 sr, cr, sr_cr[2] = {0};
>>> +
On 05/09/2019 03:52 PM, Simon Horman wrote:
> SUDMAC driver was introduced in v3.10 but was never integrated for use
> by any platform. As it unused remove it.
"It's unused" perhaps? :-)
> Signed-off-by: Simon Horman
[...]
MBR, Sergei
On 4/29/19 9:22 AM, Geert Uytterhoeven wrote:
> ata_host_alloc() can only fail due to memory allocation failures.
> Hence there is no need to print a message, as the memory allocation core
> code already takes care of that.
Applied, thanks.
--
Jens Axboe
On Thu, May 09, 2019 at 08:57:44AM +0200, Ulrich Hecht wrote:
>
> > On May 8, 2019 at 6:52 PM Niklas Söderlund
> > wrote:
> >
> >
> > Hi Sergei,
> >
> > On 2019-05-08 18:59:01 +0300, Sergei Shtylyov wrote:
> > > Hello!
> > >
> > > On 05/08/2019 06:21 PM, Ulrich Hecht wrote:
> > >
> > > > Us
> On May 9, 2019 at 12:10 PM Simon Horman wrote:
>
>
> On Thu, May 09, 2019 at 08:57:44AM +0200, Ulrich Hecht wrote:
> >
> > > On May 8, 2019 at 6:52 PM Niklas Söderlund
> > > wrote:
> > >
> > >
> > > Hi Sergei,
> > >
> > > On 2019-05-08 18:59:01 +0300, Sergei Shtylyov wrote:
> > > > Hel
According to the latest information, the clock options for CAN on RZ/G2
are the same as the ones available on R-Car Gen3
Fixes: 868b7c0f43e6 ("dt-bindings: can: rcar_can: Add r8a774a1 support")
Signed-off-by: Fabrizio Castro
Reviewed-by: Chris Paterson
Reviewed-by: Simon Horman
Reviewed-by: Rob
From: Marek Vasut
Document the support for rcar_canfd on R8A77990 SoC devices.
Signed-off-by: Marek Vasut
Cc: Eugeniu Rosca
Cc: Geert Uytterhoeven
Cc: Marc Kleine-Budde
Cc: Rob Herring
Cc: Simon Horman
Cc: Wolfram Sang
Cc: linux-renesas-soc@vger.kernel.org
To: devicet...@vger.kernel.org
R
Document the support for rcar_canfd on R8A774C0 SoC devices.
Signed-off-by: Fabrizio Castro
Reviewed-by: Chris Paterson
Reviewed-by: Simon Horman
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 16 +---
1 file changed, 9 insertions(+), 7 del
Dear All,
I am reposting some CAN and CANFD related dt-bindings changes for
Renesas' R-Car and RZ/G devices that have been originally sent
end of last year and beginning of this year.
Thanks,
Fab
Fabrizio Castro (3):
dt-bindings: can: rcar_can: Fix RZ/G2 CAN clocks
dt-bindings: can: rcar_can
Document RZ/G2E (r8a774c0) SoC specific bindings.
Signed-off-by: Fabrizio Castro
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/net/can/rcar_can.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devi
From: Marek Vasut
Document the support for rcar_canfd on R8A77965 SoC devices.
Signed-off-by: Marek Vasut
Cc: Eugeniu Rosca
Cc: Geert Uytterhoeven
Cc: Marc Kleine-Budde
Cc: Rob Herring
Cc: Simon Horman
Cc: Wolfram Sang
Cc: linux-renesas-soc@vger.kernel.org
Reviewed-by: Simon Horman
---
Hi Chrisさん
Thank you for the patch!
> From: Chris Brandt, Sent: Tuesday, May 7, 2019 8:46 AM
>
> The RZ/A2 is similar to the R-Car Gen3 with some small differences.
>
> Signed-off-by: Chris Brandt
> ---
> drivers/usb/renesas_usbhs/Makefile | 2 +-
> drivers/usb/renesas_usbhs/common.c | 27 ++
Hi Chrisさん
Thank you for the patch!
> From: Chris Brandt, Sent: Tuesday, May 7, 2019 8:46 AM
>
> When not using OTG, the PHY will need to know if it should function as
> host or peripheral by checking dr_mode in the PHY node (not the parent
> controller node).
>
> Signed-off-by: Chris Brandt
>
On Wed, May 01, 2019 at 02:54:07PM +0530, Nishad Kamdar wrote:
> This patch corrects the SPDX License Identifier style
> in header files related to Clock Drivers for Renesas Socs.
> For C header files Documentation/process/license-rules.rst
> mandates C-like comments (opposed to C source files wher
From: Cao Van Dong
Document SoC specific bindings for R-Car H3/M3-N/E3 SoCs.
Signed-off-by: Cao Van Dong
Reviewed-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Signed-off-by: Simon Horman
---
Documentation/devicetree/bindings/timer/renesas,cmt.txt | 6 ++
1 file changed, 6 insertions(
Hi Shimodaさん、
> From: Yoshihiro Shimoda
> Sent: Thursday, May 09, 2019 3:04 AM
> > -/* status */
> > -#define usbhsc_flags_init(p) do {(p)->flags = 0; } while (0)
> > -#define usbhsc_flags_set(p, b) ((p)->flags |= (b))
> > -#define usbhsc_flags_clr(p, b) ((p)->flags &= ~(b))
> > -#define usbhs
Hello!
On 05/09/2019 05:06 AM, masonccy...@mxic.com.tw wrote:
[...]
>> > >> > On 4/24/19 11:23 PM, Rob Herring wrote:
>> > >> > > On Wed, Apr 24, 2019 at 03:55:36PM +0800, Mason Yang wrote:
>> > >> > >> Document the bindings used by the Renesas R-Car Gen3 RPC-IF MFD.
>> > >> > >>
>> > >> > >> Sig
Document the optional dr_mode property
Signed-off-by: Chris Brandt
---
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
b/Documentation/devicetree/bindings/phy/rcar-ge
The RZ/A2 has an optional dedicated 48MHz clock input for the PLL.
If a clock node named 'usb_x1' exists and set to non-zero, then we can
assume we want it use it.
Signed-off-by: Chris Brandt
---
v2:
* use 'usb_x1' clock node instead of 'renesas,uses_usb_x1' property
---
drivers/phy/renesas/phy
When not using OTG, the PHY will need to know if it should function as
host or peripheral by checking dr_mode in the PHY node (not the parent
controller node).
Signed-off-by: Chris Brandt
---
v2:
* added braces to else statement
* check if dr_mode is "host"
---
drivers/phy/renesas/phy-rcar-gen
Add USB Device support for RZ/A2.
Signed-off-by: Chris Brandt
---
v2:
* changed to generic name usb@xxx
* Add space between compatible strings
---
arch/arm/boot/dts/r7s9210.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/
The RZ/A2M EVB has a 48MHz clock attached to USB_X1.
Signed-off-by: Chris Brandt
---
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts
b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
index 7795066d82cb..7da409170db5 1
Document RZ/A2 (R7S9210) SoC bindings.
Signed-off-by: Chris Brandt
---
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
b/Documentation/devicet
Enable USB Host support for both the Type-C connector on the CPU board
and the Type-A plug on the sub board.
Both boards are also capable of USB Device operation as well after the
appropriate Device Tree modifications.
Signed-off-by: Chris Brandt
---
v2:
* added blank line between nodes
* remo
Document the optional renesas,uses_usb_x1 property.
Signed-off-by: Chris Brandt
---
v2:
* removed 'use_usb_x1' option
* document that 'usb_x1' clock node will be detected to determine if
48MHz clock exists
---
Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 4 +++-
1 file cha
The RZ/A2 is similar to the R-Car Gen3 with some small differences.
Signed-off-by: Chris Brandt
---
v2:
* combined RZA1 and RZA2 for fifo setting
* added braces to make code easier to read
* fixed and clean up usbhs_rza2_power_ctrl()
---
drivers/usb/renesas_usbhs/Makefile | 2 +-
drivers/usb
Some SoC have a CFIFO register that is byte addressable. This means
when the CFIFO access is set to 32-bit, you can write 8-bit values to
addresses CFIFO+0, CFIFO+1, CFIFO+2, CFIFO+3.
Signed-off-by: Chris Brandt
---
drivers/usb/renesas_usbhs/common.h | 1 +
drivers/usb/renesas_usbhs/fifo.c | 9
For some SoC, CNEN must be set for USB Device mode operation.
Signed-off-by: Chris Brandt
---
drivers/usb/renesas_usbhs/common.c | 6 ++
drivers/usb/renesas_usbhs/common.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/usb/renesas_usbhs/common.c
b/drivers/usb/renesas_usbhs/c
Add support for r7s9210 (RZ/A2M) SoC
Signed-off-by: Chris Brandt
---
Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
in
Add USB clock node. If present, this clock input must be 48MHz.
Signed-off-by: Chris Brandt
---
arch/arm/boot/dts/r7s9210.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
index 2eaa5eeba509..73041f04fef5 100644
--- a/
Move flags macros to header file so they can be used by other files.
Signed-off-by: Chris Brandt
---
drivers/usb/renesas_usbhs/common.c | 7 ---
drivers/usb/renesas_usbhs/common.h | 10 ++
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/renesas_usbhs/comm
Add EHCI and OHCI host support for RZ/A2.
Signed-off-by: Chris Brandt
---
v2:
* changed to generic name usb@xxx
* Add space between compatible strings
---
arch/arm/boot/dts/r7s9210.dtsi | 64 ++
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boo
For the most part, the RZ/A2 has the same USB 2.0 host and device
HW as the R-Car Gen3, so we can reuse a lot of the code.
However, there are a couple extra register bits, and the CFIFO
register 8-bit access works a little different..
There is a dedicated DMAC for the RZ/A2 USB Device HW, but we
On Thu, 2019-05-09 at 15:11 -0500, Chris Brandt wrote:
> The RZ/A2 has an optional dedicated 48MHz clock input for the PLL.
> If a clock node named 'usb_x1' exists and set to non-zero, then we can
> assume we want it use it.
>
> Signed-off-by: Chris Brandt
> ---
> v2:
> * use 'usb_x1' clock node
On Thu, 2019-05-09 at 15:11 -0500, Chris Brandt wrote:
> The RZ/A2 is similar to the R-Car Gen3 with some small differences.
>
> Signed-off-by: Chris Brandt
> ---
> v2:
> * combined RZA1 and RZA2 for fifo setting
> * added braces to make code easier to read
> * fixed and clean up usbhs_rza2_po
On Thu, 2019-05-09 at 15:11 -0500, Chris Brandt wrote:
> Move flags macros to header file so they can be used by other files.
>
> Signed-off-by: Chris Brandt
> ---
> drivers/usb/renesas_usbhs/common.c | 7 ---
> drivers/usb/renesas_usbhs/common.h | 10 ++
> 2 files changed, 10 inser
Hi Chrisさん
Thank you for the patch!
> From: Chris Brandt, Sent: Friday, May 10, 2019 5:12 AM
>
> The RZ/A2 has an optional dedicated 48MHz clock input for the PLL.
> If a clock node named 'usb_x1' exists and set to non-zero, then we can
> assume we want it use it.
>
> Signed-off-by: Chris Brand
Hi Chris-san,
Thank you for the patch!
> From: Chris Brandt, Sent: Friday, May 10, 2019 5:12 AM
>
> Document the optional renesas,uses_usb_x1 property.
>
> Signed-off-by: Chris Brandt
> ---
> v2:
> * removed 'use_usb_x1' option
> * document that 'usb_x1' clock node will be detected to determ
Hi Shimoda-san, Chris,
On Fri, May 10, 2019 at 6:38 AM Yoshihiro Shimoda
wrote:
> > From: Chris Brandt, Sent: Friday, May 10, 2019 5:12 AM
> >
> > Document the optional renesas,uses_usb_x1 property.
> >
> > Signed-off-by: Chris Brandt
> > ---
> > v2:
> > * removed 'use_usb_x1' option
> > * doc
Hi Simoda-san, Chris,
On Fri, May 10, 2019 at 6:17 AM Yoshihiro Shimoda
wrote:
> > From: Chris Brandt, Sent: Friday, May 10, 2019 5:12 AM
> >
> > The RZ/A2 has an optional dedicated 48MHz clock input for the PLL.
> > If a clock node named 'usb_x1' exists and set to non-zero, then we can
> > assum
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