> The issue with the CS being held low so long makes me think there is a
> little bit more to it.
If you look at function rspi_setup, you'll see that bit SPCMD_SSLKP is set so
the CS will stay low after every transfer until SW comes back in and manually
puts it back high.
I would guess the
> The DMA controller in the RZ/A1 can apparently read a long from the source in
> one
> transaction and feed it too the destination as 4 byte writes so I'm thinking
> maybe
> I can setup the DMA controller to read 2 longs and write that as 8 bytes in
> one go
> so that each DMA transaction
Well, it's a 16 byte FIFO, so if you can just fill it up and leave that's the
easiest from a SW/HW standpoint.
However, if you just used DMA every time, it would still finish just as fast
without any CPU involvement so that's the same.
So, maybe using the FIFO instead of DMA was a fun idea,
> The gr peach board only has the internal 10MB SRAM so everything should be
> coming from there.
Damn. There goes that easy excuse of why it's slow.
> The kernel is running from the memory mapped SPI flash however. I'm not sure
> if that would make a difference.
No, that should not be the
RZ/A1.
Chris
-Original Message-
From: Daniel Palmer [mailto:danier...@gmail.com]
Sent: Thursday, August 04, 2016 2:59 PM
To: Geert Uytterhoeven <ge...@linux-m68k.org>
Cc: Chris Brandt <chris.bra...@renesas.com>; linux-renesas-soc@vger.kernel.org
Subject: Re: spi-rspi mixes
is to specify a secure write function which will then cause
the cache-l2x0 driver to not enable this feature.
If you do not override a l2c_write_sec function which causes the line of
zeros mode to be enabled, then the system will crash pretty quickly after
the L2C is enabled.
Signed-off-by: Chris Brandt
On Friday, January 27, 2017, Chris Brandt wrote:
> When there is no status bit, it is possible for the clock enable/disable
> operation to have not completed by the time the driver code resumes
> execution. This is due to the fact that write operations are sometimes
> queued and delaye
On Friday, January 27, 2017, Chris Brandt wrote:
> Due to the lack of clock status bits, we need to disable runtime pm
> for all RZ/A1 peripherals. Otherwise, it is possible that a driver
> will start using a peripheral before it is fully ready.
>
> By using pm_clk_resume immediate
Hi Laurent,
On Tuesday, January 31, 2017, Laurent Pinchart wrote:
> On Monday 30 Jan 2017 19:19:18 Chris Brandt wrote:
> > On Wednesday, January 25, 2017, Jacopo Mondi wrote:
> > > + /* Port 5 */
> > > + RZ_PIN_NAME(5, 0), RZ_PIN_NAME(5, 1), RZ_PIN_NAME(5, 2
-
> From: jacopo mondi [mailto:jac...@jmondi.org]
> Sent: Tuesday, January 31, 2017 4:01 AM
> To: Chris Brandt <chris.bra...@renesas.com>; Jacopo Mondi
> <jacopo+rene...@jmondi.org>; laurent.pinch...@ideasonboard.com;
> geert+rene...@glider.be; linus.wall...@linaro.org
On Tuesday, January 31, 2017, Geert Uytterhoeven wrote:
> > This may become something like:
> >
> > #define ALT_FUNC_1 0
> > #define ALT_FUNC_2 1
> > #define ALT_FUNC_3 2
> > #define ALT_FUNC_4 3
> > #define ALT_FUNC_5 4
> > #define ALT_FUNC_6 5
> > #define
Hi Laurent (and Jacopo)
On Tuesday, January 31, 2017, Laurent Pinchart wrote:
> On Monday 30 Jan 2017 19:39:33 Chris Brandt wrote:
> > On Monday, January 30, 2017, Laurent Pinchart wrote:
> > >> +pinctrl: pinctrl@fcfe3000 {
> > >> +c
support to the RZ/A1 DT.
v2:
* Added "arm,pl310-no-sideband" to cache-l2x0.c instead of hacking in a
dummy l2c_write_sec function to keep FLZ from being enabled.
Chris Brandt (3):
ARM: l2c: add pl310-no-sideband option
ARM: shmobile: r7s72100: Enable L2 cache
ARM: dts: r7s72100: ad
Even though L2C is specified in the DT, you still need to add the aux
settings in the machine_desc.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v2:
* removed dummy l2c_write_sec function
---
arch/arm/mach-sh
gets the commands.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
Documentation/devicetree/bindings/arm/l2c2x0.txt | 2 ++
arch/arm/mm/cache-l2x0.c | 9 +++--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bi
Note that arm,pl301-no-sideband is required because the sideband signals
between the CPU and L2C were not connected in this SoC.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v2:
* added "arm,pl310-no-sideba
for an XIP kernel and you cannot build.
Given that it is already clear in the Kconfig that ARM_PATCH_PHYS_VIRT and
XIP_KERNEL do not go well together (read the help for ARM_PATCH_PHYS_VIRT),
adding this condition to ARCH_MULTIPLATFORM is logical and will fix this
build issue.
Signed-off-by: Chris Brandt
On Wednesday, February 08, 2017, Russell King wrote:
> On Wed, Feb 08, 2017 at 12:22:09PM -0500, Chris Brandt wrote:
> > Since ARCH_MULTIPLATFORM explicitly selects ARM_PATCH_PHYS_VIRT, even
> > though ARCH_MULTIPLATFORM has 'depends on !XIP_KERNEL',
> > ARM_PATCH_PHYS_V
Hello Russell,
On Wednesday, February 08, 2017, Russell King wrote:
> We have the big "ARM system type" choice, one of the options there is to
> build for multi-platform. Historically, it's been to select the SoC
> family - where "SoC family" means a group of SoCs that could be built
> together
depends on !ARM_LPAE && !ARCH_MULTIPLATFORM && XIP_CAPABLE
Chris Brandt (2):
ARM: add ARM_SINGLE_ARMV7 as config option
ARM: shmobile: add renesas soc as a top level selection
arch/arm/Kconfig | 22 ++
arch/arm/Kconfig.debug | 6 --
arch/
,
ARM_SINGLE_ARMV7 was added along side it in order to produce similar
results.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
arch/arm/Kconfig | 18 ++
arch/arm/Kconfig.debug| 6 --
arch/arm/Makefile | 5 +
arch/arm/kernel/devtree.
Allows users to select "Renesas ARM SoCs" as opposed to multiplatform.
ARM_SINGLE_ARMV7 is then selected to help with the behind the scenes work
in the build scripts.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
arch/arm/Kconfig | 4
arch/a
Hello Florian,
On Wednesday, February 08, 2017, Florian Fainelli wrote:
> On 02/08/2017 07:30 PM, Chris Brandt wrote:
> > Creates a new ARM_SINGLE_ARMV7 option as an alternative
> ARCH_MULTIPLATFORM.
> >
> > ARM_SINGLE_ARMV7 is very similar to ARCH_MULTIPLATFORM, exc
As of commit
8ef418c7178f "ARM: l2c: trial at enabling some Cortex-A9 optimisations"
from linux-3.16, my Renesas RZ/A1 (R7s72100) has never been able to use
its PL310 r3p2. It enables it fine, but then crashes later on in boot
because of corrupted memory.
It basically boils down to these
Hi Geert,
On Monday, February 06, 2017, Geert Uytterhoeven wrote:
> CC linux-arm-kernel
>
> On Thu, Feb 2, 2017 at 10:20 PM, Chris Brandt <chris.bra...@renesas.com>
> wrote:
> > This enables the 128KB L2 cache in the RZ/A1 (R7S72100).
> >
> > The 'Write full l
Hi Geert,
On Monday, February 06, 2017, Geert Uytterhoeven wrote:
> > I agree that faking out a secure write function just so the fill-zeros
> > sideband feature is not enabled is a bit of a hack, but I'm not sure
> > if modifying the cache-l2x0.c was an option.
>
> Given I've added
Hi Simon,
On Monday, February 06, 2017, Simon Horman wrote:
> is it possible to apply the .dtsi and .c portions of this change
> separately and still get sane behaviour at each step?
>
> If so I would like to request that this patch be split into two patches,
> one for .c and one for .dtsi. This
, runtime PM no longer seems to be an issue.
Fixes: 310c18a41450 ("i2c: riic: add driver")
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
drivers/i2c/busses/i2c-riic.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/dr
Hello Russell,
Thank you for your reply. This at least fills in some missing info
for me.
On Wednesday, February 01, 2017, Russell King wrote:
> > (1) I see that the PL310 is enabled on multiple platforms, so how as
> > this not broken any systems since it was introduced in 2014? What am I
>
This patch adds a OSTM driver for the Renesas architecture.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v2:
* changed implementation to be independent channel nodes
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clocksource/Kconfig| 12 ++
drivers/clock
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v3:
* changed ostm@fcfec000 to timer@fcfec000 in example
* added power-domains in example
v2:
* remove sw implementation specific portions
---
.../devicetree/bindings/t
source, and any additional channels probed
will become a clock event.
Chris Brandt (2):
dt-bindings: document renesas-ostm timer
clocksource: Add renesas-ostm timer driver
.../devicetree/bindings/timer/renesas,ostm.txt | 30 ++
arch/arm/mach-shmobile/Kconfig | 1
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v2:
* remove part that was supposed to go in dsti
* now there is a node for each channel
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v3:
* changed ostm@xxx to timer@xxx
* added power-domains to nodes
v2:
* wrap clock lines to avoid 80 char max
* split into 2 separate channel nodes
---
arch/arm/boot/dts/r7s72100.dtsi | 18 ++
1 file chang
Hi Geert,
On Monday, January 23, 2017, Geert Uytterhoeven:
> > @@ -190,6 +191,12 @@ static int sh_mobile_sdhi_clk_enable(struct
> tmio_mmc_host *host)
> > if (ret < 0)
> > return ret;
> >
> > + ret = clk_prepare_enable(priv->clk_cd);
> > + if (ret < 0) {
> > +
Hi Geert,
On Tuesday, January 24, 2017, Geert Uytterhoeven wrote:
> > From what I can tell, that makes the register space readable...but the
> > IP block is not fully functional unless you delay a little.
>
> If you know the minimum delay needed, and it's not too long, it can be
> added to the
On Tuesday, January 24, 2017, Simon Horman wrote:
> On Mon, Jan 23, 2017 at 04:12:16PM +0100, Geert Uytterhoeven wrote:
> > On Mon, Jan 23, 2017 at 3:13 PM, Chris Brandt <chris.bra...@renesas.com>
> wrote:
> > > Signed-off-by: Chris Brandt <chris.bra...@renesas.c
Hello Renesas SoC people,
One difference between R-Car/RZG vs RZA is that there is no status bits for the
MSTP clocks.
This means even though you enable a clock by clearing the module-stop bit,
you're not really guaranteed that the peripheral block is ready to be used.
For the most part, the
Hi Daniel,
On Tuesday, January 24, 2017, Daniel Lezcano wrote:
> > > > +early_platform_init("earlytimer", _timer);
> > > > +subsys_initcall(ostm_init); module_exit(ostm_exit);
> > > > +
> > > > +MODULE_AUTHOR("Chris B
stem_clock = (void *)-1; /* prevent future attempts */
> > + ret = 0;/* still works as clocksource */
> > + }
>
> This error code check is unnecessary complex. ostm_init_sched_clock always
> return zero.
Good point.
And since sched_clock_register() always retur
Hi Jacopo,
On Thursday, January 26, 2017, jacopo mondi wrote:
> > I think we should try to avoid the rz naming as much as possible since
> > this driver will hopefully be useful for other future Renesas devices
> > if they move to a similar pin-control type method. Maybe future "R-car"
> SoCs?
>
On Thursday, January 26, 2017, Rob Herring wrote:
> >> > +
> >> > +Example showing 2 clocks:
> >> > + sdhi0: sd@e804e000 {
> >>
> >> mmc@...
> >
> > I'm confused. I see that for all SDHI controllers, it either "sd@" or
> "sdhci@".
> >
> > $ grep sdhi $(find arch/arm/boot/dts -name "*.dtsi")
> >
On Thursday, January 26, 2017, Wolfram Sang wrote:
> Subject: Re: [PATCH v6 0/3] mmc: sh_mobile_sdhi: fix missing r7s72100
> clocks
>
>
> > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > guess!? (And I can add Rob's ack afterwards).
>
> Can you add my tags as well. They
Hi Simon,
On Thursday, January 26, 2017, Simon Horman wrote:
> > Thanks, applied patch1 and patch2 for next. Patch3 is for Simon, I
> > guess!? (And I can add Rob's ack afterwards).
>
> Thanks, I will take care of the 3rd patch.
>
> Chris, is it safe to apply the 3rd patch without the first 2
Hi Daniel,
On Thursday, January 26, 2017, Daniel Lezcano wrote:
> > ---
> > v3:
> > * Added more details to commit log
> > * Kconfig: SYS_SUPPORTS_RENESAS_OSTM to just RENESAS_OSTM
> > * removed all MODULE code (this driver is builtin only)
> > * removed items from 'struct ostm_device'
> > *
This patch adds a OSTM driver for the Renesas architecture.
The OS Timer (OSTM) has independent channels that can be
used as a freerun or interval times.
This driver uses the first probed device as a clocksource
and then any additional devices as clock events.
Signed-off-by: Chris Brandt
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v3:
* changed ostm@fcfec000 to timer@fcfec000 in example
* added power-domains in example
v2:
* remove sw implementation specific portions
---
.../devicetree/bindings/t
be set up as a clock source, and any additional channels probed
will become a clock event.
Chris Brandt (2):
dt-bindings: document renesas-ostm timer
clocksource: Add renesas-ostm timer driver
.../devicetree/bindings/timer/renesas,ostm.txt | 30 +++
arch/arm/mach-shmobile/Kconfig
This patch adds a OSTM driver for the Renesas architecture.
The OS Timer (OSTM) has independent channels that can be
used as a freerun or interval times.
This driver uses the first probed device as a clocksource
and then any additional devices as clock events.
Signed-off-by: Chris Brandt
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v3:
* changed ostm@fcfec000 to timer@fcfec000 in example
* added power-domains in example
v2:
* remove sw implementation specific portions
---
.../devicetree/bindings/t
DT. The first probed will
be set up as a clock source, and any additional channels probed
will become a clock event.
Chris Brandt (2):
dt-bindings: document renesas-ostm timer
clocksource: Add renesas-ostm timer driver
.../devicetree/bindings/timer/renesas,ostm.txt | 30 +++
arch/arm/m
Hi Geert,
On Wednesday, January 25, 2017, Geert Uytterhoeven wrote:
> >> I think you can handle that in drivers/clk/renesas/clk-mstp.c:
> >> - in cpg_mstp_attach_dev(), add a call to pm_clk_resume(dev) after
> the
> >> call to pm_clk_add_clk(),
> >> - in cpg_mstp_detach_dev(), add a call
down to 0, and hence will always keep
the clock enabled.
In order for dis_runtime_pm to be accessible for all relevant functions
in this file, it needed to be a global.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
drivers/clk/renesas/clk-mstp.c | 20 ++--
.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
drivers/clk/renesas/clk-mstp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index 3ce819c..69cfdb9 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drive
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v3:
* changed ostm@fcfec000 to timer@fcfec000 in example
* added power-domains in example
v2:
* remove sw implementation specific portions
---
.../devicetree/bindings/t
ns to nodes
v2:
* The biggest change was now the channels are independent of each
other and have separate nodes in the DT. The first probed will
be set up as a clock source, and any additional channels probed
will become a clock event.
Chris Brandt (2):
dt-bindings: document renesas-ostm ti
Hi Jacopo,
On Monday, January 30, 2017, Jacopo Mondi wrote:
> > Note that the I2C pin need to be configured at "bi-directional" but
> > there is no way to specify that from DT, so that has to be added as a
> parameter.
>
> That's something I would like to discuss quite soon.
> One general thing
Hi Jacopo,
On Monday, January 30, 2017, Laurent Pinchart wrote:
> > + pinctrl: pinctrl@fcfe3000 {
> > + compatible = "renesas,rza1-pinctrl";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + #pinctrl-cells = <2>;
> > +
> > + reg =
Hi Jacopo,
On Wednesday, January 25, 2017, Jacopo Mondi wrote:
> + /* Port 5 */
> + RZ_PIN_NAME(5, 0), RZ_PIN_NAME(5, 1), RZ_PIN_NAME(5, 2),
> + RZ_PIN_NAME(5, 3), RZ_PIN_NAME(5, 4), RZ_PIN_NAME(5, 5),
> + RZ_PIN_NAME(5, 6), RZ_PIN_NAME(5, 7), RZ_PIN_NAME(5, 8),
> +
Hi Jacopo,
On Wednesday, January 25, 2017, Jacopo Mondi wrote:
> +
> + return 0;
> +
> +free_map:
> + devm_kfree(rz_pinctrl->dev, *map);
> +free_fngrps:
> + devm_kfree(rz_pinctrl->dev, fngrps);
> +free_pins:
> + devm_kfree(rz_pinctrl->dev, mux_modes);
> +
On Monday, January 30, 2017, Laurent Pinchart wrote:
> > It depends on the actual hardware: while per-pin settings are suitable
> > for SoCs that have per-pin hardware configuration (e.g. RZ/A1), it's
> > not suitable for SoCs where that's not the case, and where the
> > hardware has group-wise
Hi Jacopo,
On Friday, January 27, 2017, Jacopo Mondi wrote:
> Hello,
>sorry if I'm sending 2 patches on top of an RFC series with comments
> still pending, but these patches enabled me to properly test pin
> configuration sequence in order to access the internal EEPROM through
> RIIC2
Hi Geert,
On Wednesday, January 25, 2017, Geert Uytterhoeven wrote:
> > I can play around and see. I know udealy(100) works OK, but then I
> > have to have a delay that's as long as the slowest peripheral.
> > If it was just to turn a clock on once, or once in a while, that's OK.
> > But it seems
Hi Daniel,
On Wednesday, January 25, 2017, Daniel Lezcano wrote:
> > Then things work, but I'm back to managing the rollback code manually.
> >
> >
> > Any other ideas on how to get the corresponding platform_device for a
> > DT node?
>
> No :/
>
> So up to you.
> - CLOCKSOURCE_OF_DECLARE
Hi Geert,
On Wednesday, January 25, 2017, Geert Uytterhoeven wrote:
> > So I realized that in order to use builtin_platform, I can't have any
> > of the functions in __init because the build system has no idea that I
> > never plan on removing or probing again after boot. But, even if I
> > take
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v3:
* changed ostm@fcfec000 to timer@fcfec000 in example
* added power-domains in example
v2:
* remove sw implementation specific portions
---
.../devicetree/bindings/t
This patch adds a OSTM driver for the Renesas architecture.
The OS Timer (OSTM) has independent channels that can be
used as a freerun or interval times.
This driver uses the first probed device as a clocksource
and then any additional devices as clock events.
Signed-off-by: Chris Brandt
Hi Jacopo,
Thanks for the patches.
On Wednesday, January 25, 2017, Jacopo Mondi wrote:
> Right now, the only "SoC" module support implemented is for RZ/A1H (Genmai
> and GR-Peach boards).
I'm going to give it a try on the RZ/A1 RSK board.
> I have tested the correctness of mux settings
Hi Jacopo,
On Wednesday, January 25, 2017, Jacopo Mondi wrote:
> drivers/pinctrl/Kconfig | 1 +
> drivers/pinctrl/Makefile| 1 +
> drivers/pinctrl/rz-pfc/Kconfig | 18 ++
> drivers/pinctrl/rz-pfc/Makefile | 1 +
> drivers/pinctrl/rz-pfc/pinctrl-rz.c | 447
Hi Geert,
On Friday, January 20, 2017, Geert Uytterhoeven wrote:
> It takes longer to boot, though. I guess due to more kernel output?
You can see there is a jump in the time when the system clocksource changes
from mtu2 to ostm.
[0.079591] clocksource: Switched to clocksource ostm
[
-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v2:
* add missing clock sources instead of just fixing typo
* changed clock name from "carddetect" to "cd"
---
arch/arm/boot/dts/r7s72100.dtsi| 17 ++
Some controllers have 2 clock sources instead of 1. The 2nd clock
is for the internal card detect logic and must be enabled/disabled
along with the main core clock for proper operation.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v3:
* add more clarification to the commit
-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v3:
* add more clarification about why there are sometimes 2 clocks
and what you should do with them.
* remove 'status = "disabled"' from example
v2:
* fix spelling and change wording
* changed clock name from &qu
on an RZ/A1 RSK board. Card detect works
fine as well as bind/unbind.
v4:
* No code changes, only text udpates to explain why there are 2 clocks
and why we need to treat them as 1 clock.
Chris Brandt (3):
mmc: sh_mobile_sdhi: add support for 2 clocks
mmc: sh_mobile_sdhi: explain clock bindings
on an RZ/A1 RSK board. Card detect works
fine as well as bind/unbind.
v5:
* Take implementation details out of DT documentation and put into
the driver code.
v4:
* No code changes, only text udpates to explain why there are 2 clocks
and why we need to treat them as 1 clock.
Chris Brandt (3):
mmc
In the case of a single clock source, you don't need names. However,
if the controller has 2 clock sources, you need to name them correctly
so the driver can find the 2nd one. The 2nd clock is for the internal
card detect logic.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v2:
* add missing clock sources instead of just fixing typo
* changed clock name from "carddetect" to "cd"
---
arch/arm/boot/dts/r7s72100.dtsi| 17 ++
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v2:
* remove sw implementation specific portions
---
.../devicetree/bindings/timer/renesas,ostm.txt | 29 ++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/r
.
Chris Brandt (2):
dt-bindings: document renesas-ostm timer
clocksource: Add renesas-ostm timer driver
.../devicetree/bindings/timer/renesas,ostm.txt | 29 ++
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clocksource/Kconfig| 12 +
drivers
This patch adds a OSTM driver for the Renesas architecture.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v2:
* changed implementation to be independent channel nodes
---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clocksource/Kconfig| 12 ++
drivers/clock
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v2:
* remove part that was supposed to go in dsti
* now there is a node for each channel
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
arch/arm/boot/dts/r7s72100.dtsi| 9 +
include/dt-bindings/clock/r7s72100-clock.h | 4
2 files changed, 13 insertions(+)
diff --git a/arch/
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v2:
* wrap clock lines to avoid 80 char max
* split into 2 separate channel nodes
---
arch/arm/boot/dts/r7s72100.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/ar
will become a clock event.
Chris Brandt (3):
ARM: dts: r7s72100: add ostm clock to device tree
ARM: dts: r7s72100: add ostm to device tree
ARM: dts: rskrza1: add ostm DT support
arch/arm/boot/dts/r7s72100-rskrza1.dts | 8
arch/arm/boot/dts/r7s72100.dtsi| 25
Hello Sergei,
On Saturday, January 21, 2017, Sergei Shtylyov wrote:
> > diff --git a/arch/arm/boot/dts/r7s72100.dtsi
> > b/arch/arm/boot/dts/r7s72100.dtsi index d5946df..47b2165 100644
> > --- a/arch/arm/boot/dts/r7s72100.dtsi
> > +++ b/arch/arm/boot/dts/r7s72100.dtsi
> > @@ -505,4 +505,20 @@
> >
Hello Geert,
On Sunday, January 22, 2017, Geert Uytterhoeven wrote:
> > diff --git a/arch/arm/boot/dts/r7s72100.dtsi
> > b/arch/arm/boot/dts/r7s72100.dtsi index d5946df..47b2165 100644
> > --- a/arch/arm/boot/dts/r7s72100.dtsi
> > +++ b/arch/arm/boot/dts/r7s72100.dtsi
> > @@ -505,4 +505,20 @@
> >
-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v2:
* add missing clock sources instead of just fixing typo
* changed clock name from "carddetect" to "cd"
---
arch/arm/boot/dts/r7s72100.dtsi| 17 ++
to treat them as 1 clock.
Chris Brandt (3):
mmc: sh_mobile_sdhi: add support for 2 clocks
mmc: sh_mobile_sdhi: explain clock bindings
ARM: dts: r7s72100: update sdhi clock bindings
Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 13
arch/arm/boot/dts/r7s72100.dtsi
In the case of a single clock source, you don't need names. However,
if the controller has 2 clock sources, you need to name them correctly
so the driver can find the 2nd one. The 2nd clock is for the internal
card detect logic.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Re
Some controllers have 2 clock sources instead of 1. The 2nd clock
is for the internal card detect logic and must be enabled/disabled
along with the main core clock for proper operation.
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
---
v5:
* call clk_disable_unprepare even if
Hi Günter and Geert,
Catching up on the subject (because I was sleeping here in the US...)
On Friday, February 17, 2017, Geert Uytterhoeven wrote:
> > FWIW, the watchdog subsystem should support that easily, even with 125
> > ms hardware timeout. We added that capability for that very purpose.
On Thursday, February 16, 2017, Guenter Roeck wrote:
> Hmm, ok. Guess I don't have to understand that you can not use the
> watchdog driver because of the above, but implementing exactly the same
> functionality in a separate driver is ok.
>
> [ I am sure I am missing something here, so just
Hello Guenter,
On Wednesday, February 22, 2017, Guenter Roeck wrote:
> > Looking through the drivers in the watchdog directly, I see default
> > timeouts of 20, 30, 60, and 120 seconds.
> >
> 30 and 60 are pretty common for default timeouts, though I personally
> think they are a bit long. If you
On Thursday, February 09, 2017, Florian Fainelli worte:
> > I think the closest I might have come was to purposely break the build
> > if more then 1 was select, but that still didn't stop you from making
> > the selection.
> >
> > If someone smarter than me has a way to do (not just an idea...I
>
.
Fixes: b6face404f38 ("ARM: shmobile: r7s72100: add essential clock nodes to
dtsi")
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v3:
* changed clk_readl to cpg_mstp_read to take into account 8-bit regi
Hi Geert,
On Monday, February 13, 2017, Geert Uytterhoeven wrote:
> On Fri, Feb 10, 2017 at 8:46 PM, Chris Brandt <chris.bra...@renesas.com>
> wrote:
> > On Friday, February 10, 2017, Geert Uytterhoeven wrote:
> >> Alternatively, you can write a restart driver (cf
Reported-by: Geert Uytterhoeven <geert+rene...@glider.be>
Signed-off-by: Chris Brandt <chris.bra...@renesas.com>
Fixes: 66474697923c ("ARM: dts: r7s72100: add sdhi to device tree")
---
arch/arm/boot/dts/r7s72100.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch
Hi Simon and Geert,
On Thursday, February 09, 2017, Simon Horman wrote:
> On Thu, Feb 09, 2017 at 11:18:47AM +0100, Geert Uytterhoeven wrote:
> > Hi Simon, Magnus,
> >
> > This patch series completes the migration from ARCH_SHMOBILE_MULTI to
> > ARCH_RENESAS, which was started by commit
On Friday, February 10, 2017, Arnd Bergmann wrote:
> I also couldn't come up with something working when I looked at this, and
> it wouldn't solve the related problem of platforms that we want to be able
> to use with or without MMU: You can't make the decision of whether allow
> an MMU based on
Hi Geert,
On Friday, February 10, 2017, Geert Uytterhoeven wrote:
> > static const char *const r7s72100_boards_compat_dt[] __initconst = {
> > "renesas,r7s72100",
> > NULL,
> > @@ -29,4 +58,5 @@ DT_MACHINE_START(R7S72100_DT, "Generic R7S72100
> (Flattened Device Tree)")
> >
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