On Thu, 01 Dec 2016 12:41:20 +0200
Laurent Pinchart wrote:
> > > If a DVI connector instead of a HDMI connector is soldered, how
> > > should such a device tree be written?
> >
> > Use a dvi-connector instead :)
>
> The HDMI encoder DT node doesn't (and
On Wed, 30 Nov 2016 20:14:11 +0100
Jernej Škrabec wrote:
> Dne četrtek, 01. december 2016 ob 03:03:14 CET je Icenowy Zheng napisal(a):
> > 2016年12月1日 02:49于 Jernej Skrabec 写道:
> >
> > > Hi Jean-François,
> > >
> > > Dne sreda, 30. november
On Wed, 30 Nov 2016 11:52:25 +0200
Laurent Pinchart <laurent.pinch...@ideasonboard.com> wrote:
> Hi Jean-François,
>
> On Wednesday 30 Nov 2016 10:27:57 Jean-Francois Moine wrote:
> > On Wed, 30 Nov 2016 10:20:21 +0200 Laurent Pinchart wrote:
> > >> Well, I
On Tue, 29 Nov 2016 22:59:32 +0100
Maxime Ripard wrote:
> > > I'm still not sure which pipeline should I use.
> > >
> > > And, it seems that HDMI Slow Clock is not needed?
> > >
> > > (seems that it's only for EDID, but simplefb won't use EDID)
> >
> > So, I
On Wed, 30 Nov 2016 10:20:21 +0200
Laurent Pinchart wrote:
> > Well, I don't see what this connector can be.
> > May you give me a DT example?
>
> Sure.
>
> arch/arm/boot/dts/r8a7791-koelsch.dts
>
> /* HDMI encoder */
>
> hdmi@39 {
>
On Tue, 29 Nov 2016 22:36:50 +0100
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Tue, Nov 29, 2016 at 11:18:35AM +0100, Jean-Francois Moine wrote:
> > This patchset series adds HDMI video support to the Allwinner
> > sun8i SoCs which include the
On Tue, 29 Nov 2016 22:10:01 +0200
Laurent Pinchart <laurent.pinch...@ideasonboard.com> wrote:
> Hi Jean-François,
>
> On Tuesday 29 Nov 2016 21:04:55 Jean-Francois Moine wrote:
> > On Tue, 29 Nov 2016 21:33 +0200 Laurent Pinchart wrote:
> > >>> You need a th
On Tue, 29 Nov 2016 21:33 +0200
Laurent Pinchart wrote:
> > > You need a third port for the HDMI encoder output, connected to an HDMI
> > > connector DT node.
> >
> > I don't see what you mean. The HDMI device is both the encoder
> > and connector (as the
On Tue, 29 Nov 2016 20:46:22 +0200
Laurent Pinchart wrote:
[snip]
> > +Example:
> > +
> > + hdmi: hdmi@01ee {
> > + compatible = "allwinner,sun8i-a83t-hdmi";
> > + reg = <0x01ee 0x2>;
> > + clocks = <
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
drivers/gpu/drm/sun8i/Kconfig | 7 +
drivers/gpu/drm/sun8i/Makefile | 2 +
drivers/gpu/drm/sun8i/de2_hdmi.c| 440 +++
drivers/gpu/drm/sun8i/de2_hdmi.h| 51 +++
drivers/gpu/drm/sun8i/de2_hdm
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
.../bindings/display/sunxi/sun8i-de2.txt | 121 +
1 file changed, 121 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
diff --git a/Documentation/devi
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
.../devicetree/bindings/display/sunxi/hdmi.txt | 56 ++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/sunxi/hdmi.txt
diff --git a/Documentation/devicetree/bi
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
Note 1:
The DE clock is not set in the driver. Instead, it is set at system
startup time by 'assigned-clocks', but there is a problem in sunxi-ng
which uses readl_relaxed_poll_timeout(), and, as noticed by
Ondřej Jirman, this fu
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index c0c49dd..9
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 047e9e1..7712972 100644
--- a/ar
zywara)
v2:
- remove the HDMI driver
- remarks from Chen-Yu Tsai and Russell King
- DT documentation added
Jean-Francois Moine (8):
drm: sun8i: Add a basic DRM driver for Allwinner DE2
drm/sun8i: Add DT bindings documentation of Allwinner DE2
drm: sun8i: add HDMI vid
Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
engine, DE2.
This patch adds a DRM video driver for this device.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/g
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
include/dt-bindings/clock/sun8i-h3-ccu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h
b/include/dt-bindings/clock/sun8i-h3-ccu.h
index efb7ba2..7af57b7 100644
--- a/include/dt-bindings
On Mon, 28 Nov 2016 17:59:00 +0800
Icenowy Zheng wrote:
> As there's currently a fork of U-Boot which provides simplefb support
> for H3, a simplefb node can be added to the device tree.
>
> Signed-off-by: Icenowy Zheng
> ---
>
> I'm still not sure which
(I reduced the Cc to linux-sunxi)
On Fri, 25 Nov 2016 18:32:07 +0800
Icenowy Zheng <icen...@aosc.xyz> wrote:
>
> 25.11.2016, 18:22, "Jean-Francois Moine" <moin...@free.fr>:
> >
> > The 'pll-de' and 'de' must have a fixed rate. Otherwise, if you do not
On Fri, 25 Nov 2016 17:41:51 +0800
Icenowy Zheng wrote:
> After removing CLK_PLL_DE's assigned-clock, the kernel passes compilation.
The 'pll-de' and 'de' must have a fixed rate. Otherwise, if you do not
use the legacy u-boot, I don't know which can be the rate of the DE.
>
On Mon, 21 Nov 2016 01:54:53 +0100
Ondřej Jirman <meg...@megous.com> wrote:
> Dne 20.11.2016 v 12:32 Jean-Francois Moine napsal(a):
> > This patchset series adds HDMI video support to the Allwinner
> > sun8i SoCs which include the display engine 2 (DE2).
> > T
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 047e9e1..9ecc6f1 100644
--- a/ar
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 51 +
1 file changed, 51 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 416b825..7c6b1d5 100644
--- a/ar
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index c0c49dd..4
This patch adds a HDMI video driver to the Allwinner's SoCs A83T and H3.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
.../devicetree/bindings/display/sunxi/hdmi.txt | 53 ++
drivers/gpu/drm/sun8i/Kconfig | 7 +
drivers/gpu/drm/sun8i/Ma
e hardware cursor
- simplify and fix the DE2 init sequences
- generation for all SUNXI SoCs (Andre Przywara)
v2:
- remove the HDMI driver
- remarks from Chen-Yu Tsai and Russell King
- DT documentation added
Jean-Francois Moine (5):
drm: sun8i: Add a basic
On Wed, 16 Nov 2016 22:33:06 +0100
Maxime Ripard wrote:
> > > > The Device Engine just handles the planes of the LCDs, but, indeed,
> > > > the LCDs must know about the DE and the DE must know about the LCDs.
> > > > There are 2 ways to realize this knowledge in
On Mon, 7 Nov 2016 23:37:41 +0100
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Fri, Oct 28, 2016 at 07:34:20PM +0200, Jean-Francois Moine wrote:
> > On Fri, 28 Oct 2016 00:03:16 +0200
> > Maxime Ripard <maxime.rip...@free-elect
On Mon, 7 Nov 2016 21:05:05 +0100
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Sun, Nov 06, 2016 at 07:02:48PM +0100, Jean-Francois Moine wrote:
> > On Sun, 23 Oct 2016 09:33:16 +0800
> > Chen-Yu Tsai <w...@csie.org> wrote:
> >
>
On Sun, 23 Oct 2016 09:33:16 +0800
Chen-Yu Tsai <w...@csie.org> wrote:
> On Fri, Oct 21, 2016 at 4:36 PM, Jean-Francois Moine <moin...@free.fr> wrote:
> > This patch adds I2S support to sun8i SoCs as the A83T and H3.
> >
> > Signed-off-by: Jean-Francois Moine &
On Sun, 30 Oct 2016 10:06:20 +0800
Chen-Yu Tsai wrote:
> >> Yes, I know that the burst size is always a power of 2.
> >> The best way to check it would be to change the {src,dts}_maxburst to a
> >> bitmap of the possible bursts as 0x0d for 1,4 and 8 bytes. But this
> >> asks for a
On Fri, 28 Oct 2016 00:03:16 +0200
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Tue, Oct 25, 2016 at 04:14:41PM +0200, Jean-Francois Moine wrote:
> > > > +Display controller
> > > > +==
> > > > +
> > > > +Re
On Fri, 28 Oct 2016 00:54:34 +0800
Chen-Yu Tsai wrote:
> There's already a driver for basically the same thing:
>
> sound/soc/codec/hdmi-codec.c
>
> You use it by registering a sub-device from your hdmi driver, with the
> proper platform_data and callbacks. Grep for
On Mon, 24 Oct 2016 14:34:49 +0200
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Sun, Oct 23, 2016 at 09:45:03AM +0200, Jean-Francois Moine wrote:
> > On Sun, 23 Oct 2016 09:33:16 +0800
> > Chen-Yu Tsai <w...@csie.org> wrote:
> &g
On Tue, 25 Oct 2016 08:44:22 +0200
Daniel Vetter wrote:
> > + /* start the subdevices */
> > + ret = component_bind_all(dev, drm);
> > + if (ret < 0)
> > + goto out2;
> > +
> > + ret = drm_dev_register(drm, 0);
>
> This needs to be the very last step in your
On Mon, 24 Oct 2016 16:04:19 +0200
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> Hi,
Hi Maxime,
> On Fri, Oct 21, 2016 at 09:26:18AM +0200, Jean-Francois Moine wrote:
> > Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
> > engine, DE2.
&
On Tue, 4 Oct 2016 18:55:54 +0200
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Tue, Oct 04, 2016 at 12:40:11PM +0200, Jean-Francois Moine wrote:
> > On Tue, 4 Oct 2016 11:46:14 +0200
> > Mylène Josserand <mylene.josser...@free-electrons.com> wro
On Sun, 23 Oct 2016 09:33:16 +0800
Chen-Yu Tsai wrote:
> > Note: This driver is closed to the sun4i-i2s except that:
> > - it handles the H3
>
> If it's close to sun4i-i2s, you should probably rework that one to support
> the newer SoCs.
>
> > - it creates the sound card (with
On Sun, 23 Oct 2016 09:38:04 +0800
Chen-Yu Tsai wrote:
> > Recently, an announce about Tina OS for the R series
> > https://www.youtube.com/watch?v=h7KD-6HblAU
> > was followed by the upload of a new linux-3.4 source tree
> > https://github.com/tinalinux/linux-3.4
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
The patch for the Banana Pi M3 (A83T) is the same as this one.
---
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
The patch for the A83T DT is not included in this patchset because
the clock driver sunxi-ng does not support the A83T clocks.
---
arch/arm/boot/dts/sun8i-h3.dtsi | 67 +
1 file changed, 67 inse
This patch adds I2S support to sun8i SoCs as the A83T and H3.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
Note: This driver is closed to the sun4i-i2s except that:
- it handles the H3
- it creates the sound card (with sun4i-i2s, the sound card is created
by the
Allwinner's SoCs include support for both audio and video on HDMI.
This patch defines a simple audio CODEC which may be used in sunxi
HDMI video drivers.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
include/sound/sunxi_hdmi.h| 23 +
sound/soc/codecs/Kconfig
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
The same patch may be applied to other H3 based boards (Orange PI xx).
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
This patch adds a HDMI driver to the DE2 based Allwinner's SoCs
as A83T and H3.
Audio and video are supported.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
.../devicetree/bindings/display/sunxi/hdmi.txt | 52 ++
drivers/gpu/drm/sunxi/Kconfig | 8 +
d
:
- add the hardware cursor
- simplify and fix the DE2 init sequences
- generation for all SUNXI SoCs (Andre Przywara)
v2:
- remove the HDMI driver
- remarks from Chen-Yu Tsai and Russell King
- DT documentation added
Jean-Francois Moine (7):
drm
Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
engine, DE2.
This patch adds a DRM video driver for this device.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
.../bindings/display/sunxi/sunxi-de2.txt | 83 +++
drivers/gpu/drm/K
On Tue, 18 Oct 2016 13:42:09 +0800
Chen-Yu Tsai wrote:
> On the A31, the DMA engine only works if AHB1 is clocked from PLL6.
> In addition, the hstimer is clocked from AHB1, and if AHB1 is clocked
> from the CPU clock, and cpufreq is working, we get an unstable timer.
>
> Force
On Wed, 5 Oct 2016 08:04:26 +0200
Code Kipper wrote:
> > +static int sun8i_probe(struct platform_device *pdev)
> > +{
> > + struct snd_soc_dai_link *link = _dai_link;
> > + struct device_node *np = pdev->dev.of_node;
> > + int ret;
> > +
> > + /*
On Tue, 4 Oct 2016 14:12:21 +0200
Thomas Petazzoni wrote:
> > > Add the case of a burst of 4 which is handled by the SoC.
> > >
> > > Signed-off-by: Mylène Josserand
> > > ---
> > > drivers/dma/sun6i-dma.c | 2 ++
> > >
On Tue, 4 Oct 2016 11:46:18 +0200
Mylène Josserand wrote:
> The sun8i audio codec is using PRCM registers to configure all the
> analog part of the audio codec. It is added as a subnode of the PRCM
> with his resource (offset of 0x1c0).
>
> Signed-off-by:
On Tue, 4 Oct 2016 11:46:14 +0200
Mylène Josserand wrote:
> Add the case of a burst of 4 which is handled by the SoC.
>
> Signed-off-by: Mylène Josserand
> ---
> drivers/dma/sun6i-dma.c | 2 ++
> 1 file changed, 2
On Sat, 24 Sep 2016 16:35:05 +0800
Chen-Yu Tsai <w...@csie.org> wrote:
> On Fri, Sep 23, 2016 at 4:58 PM, Jean-Francois Moine <moin...@free.fr> wrote:
> > This patch series adds support for the X-Powers AXP803 and AXP813 PMICs.
> > It is based on the previous patch s
On Sat, 24 Sep 2016 16:29:11 +0800
Chen-Yu Tsai wrote:
[snip]
> > static int axp20x_regulator_probe(struct platform_device *pdev)
> > {
> > + struct device *dev = pdev->dev.parent;
>
> There are 2 struct device's in play in this function, 1 from the parent,
> and
The X-Powers AXP803 PMIC is close to the AXP809 with more outputs.
It is used in some Allwinner boards as the Sinovoip BananaPi M64
and the Pine A64.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
not tested
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 32 +++-
drive
The axp20x driver contains device specific and device independant parts.
This patch moves the independant parts to new .c/.h files.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
drivers/regulator/Makefile | 2 +-
drivers/regulator/axp-regulator.c
The axp20x rsb driver handles many different devices.
Duplicating its code in a generic regulator driver permits
to probe/remove individual devices.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
drivers/regulator/axp-regulator.c | 39 +++
d
The X-Powers AXP813 PMIC is close to the AXP803.
It is used in some Allwinner boards as the Sinovoip BananaPi M3+.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 9 +-
drivers/mfd/axp20x.c | 2 +
d
and interrupts
v2:
- fix lack of support of dcdc frequency
- notice that the AXP803 is also handled
- send the patch to the DT maintainers
Jean-Francois Moine (4):
regulator: axp20x: move device independant parts to new files
regulator: axp20x: duplicate the MFD axp20x-rsb code
regulator: axp20x: add
Building a list (bitmap) of the slaves included in poly-phase groups
at probe startup time simplifies the treatment in the regulator
creation loop.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
drivers/regulator/axp20x-regulator.c | 45 +---
This patch series just simplifies a bit the code of the AXP20x driver.
It does not contain any fonctional changes.
It will be used as a base for adding new AXP devices (patches to come).
It applies on linux-next.
Jean-Francois Moine (3):
regulator: axp20x: simplify poly-phase handling
Using ancillary variables for handling the linked regulators simplifies
the loop of regulator creation and makes easier the addition of new
regulator types.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
drivers/regulator/axp20x-regulator.c | 24
1 file c
Use the pointer to the main regulator device instead of the pointer
to the child platform device.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
drivers/regulator/axp20x-regulator.c | 45 ++--
1 file changed, 23 insertions(+), 22 deletions(-)
diff
The A83T SoC has the same dma engine as the A31 (sun6i), with a reduced
amount of endpoints and physical channels.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
drivers/dma/sun6i-dma.c
On Tue, 30 Aug 2016 18:26:13 +0200
Maxime Ripard wrote:
> > There are 2 flags saying that the new timing is used:
> > - the bit 'mode select' in the clock register, and
> > - the bit 'new timing' in the MMC register.
> > Both bits must be set/reset at the same
clk_round_rate() may return an error. Check it.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
Rebase on linux-next
---
drivers/mmc/host/sunxi-mmc.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
On Mon, 22 Aug 2016 02:23:51 +0800
Vishnu Patekar wrote:
> Thanks for followup patches for a83t modern clock.
>
> well, this patch series does not apply on sunxi/for-next.
Hi Vishnu,
This series is rather old!
Well, at this time, I was thinking that the 'modern'
On Tue, 16 Aug 2016 23:04:47 +0800
Icenowy Zheng wrote:
> > Also, please, may you give me a pointer to the AXP813 documentation?
> I got it on BaiduPan.
> https://pan.baidu.com/share/link?shareid=120641733=2121502978=169295081716431
> Here's a link, you can download it if you
On Tue, 16 Aug 2016 19:30:17 +0800
Icenowy Zheng wrote:
> > The X-Powers AXP803 and AXP813 PMICs are close to the AXP809 with some
> > more outputs.
> AXP803 and AXP813 is quite different.
> AXP803 have 6 DCDCs and 16 LDOs
> AXP813 have 7 DCDCs and 15 LDOs
> and AXP813 have an
The X-Powers AXP803 and AXP813 PMICs are close to the AXP809 with some
more outputs.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
The AXP813 has been tested in a Banana PI M3 board (needed for WiFi/BT).
v2:
- fix lack of support of dcdc frequency
- notice that the AXP803 i
-Francois Moine <moin...@free.fr>
---
Some explanations:
In the old timing, the phase delays are set in the clock only
(that's why there is a function clk_set_phase() which is called from
the MMC side).
In the new timing, the delays are in the MMC register SDXC_REG_NTSR
only.
The new timing work
The hardware phase delay may depend on some other settings as clock
reparenting, so, it has to be set each time.
Also, when the delay was the same as previously, an error was returned.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
drivers/clk/clk.c | 4
1 file chan
clk_round_rate() may return an error. Check it.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
---
This patch was initially sent in a patch series about the MMC new mode,
but it may be applied independently.
---
driv
On Tue, 9 Aug 2016 18:02:47 +0800
Chen-Yu Tsai wrote:
> > The 'parent's of the bus gates are of no interest.
> > They are supposed to be (no clear documentation) apb1, apb2, ahb1 and
> > ahb2, but, as you well noticed in the patch 5/7, these clocks are fixed
> > and have no gate.
On Mon, 8 Aug 2016 18:21:45 +0100
Andre Przywara wrote:
> The Allwinner H3 SoC introduced bus clock gates with potentially
> different parents per clock gate register. The H3 driver chose to
> hardcode the actual parent clock relation in the code.
> Add a new driver
On Tue, 2 Aug 2016 12:20:48 +0100
Mark Rutland wrote:
> > This mode is described at least in the Allwinner's documentation of the
> > A83T, A64 and H3.
>
> Is this publicly available? If not, can the gist of it be described?
The links are in the kernel
Hi Chen-Yu,
On Mon, 1 Aug 2016 21:52:48 +0800
Chen-Yu Tsai <w...@csie.org> wrote:
> On Mon, Aug 1, 2016 at 9:10 PM, Jean-Francois Moine <moin...@free.fr> wrote:
> > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > a 'New Timings' mode.
>
On Mon, 1 Aug 2016 16:30:19 +0100
Mark Rutland <mark.rutl...@arm.com> wrote:
> On Mon, Aug 01, 2016 at 03:10:29PM +0200, Jean-Francois Moine wrote:
> > Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
> > a 'New Timings' mode.
> > Set this capacit
On Sat, 30 Jul 2016 12:19:03 +0200
Hans de Goede wrote:
> Jean-Francois, can you submit a v2 of your patch and make the writing of
> SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?
>
> Also you should probably drop the bits about the clock stuff from the
> commit
Some MMC devices as mmc2 in the A83T or mmc1 and mmc2 in the H3 have
a 'New Timings' mode.
Set this capacity in the DT and use it when possible.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
I don't know if this mode works or is needed at 25MHz.
---
Documentation/devicetree/bi
On Fri, 29 Jul 2016 21:36:34 +0200
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Thu, Jul 21, 2016 at 11:26:55AM +0200, Jean-Francois Moine wrote:
> > On Thu, 21 Jul 2016 10:56:15 +0200
> > Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
>
On Fri, 29 Jul 2016 21:17:30 +0200
Maxime Ripard wrote:
> > > What happens if you actually want to set it to 100MHz?
> >
> > There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked
> > only for 8 bits DDR at 50MHz.
>
> You're missing the point.
>
On Thu, 28 Jul 2016 22:19:44 +0200
Maxime Ripard wrote:
> > Documentation/devicetree/bindings/mfd/axp20x.txt | 32 -
> > drivers/mfd/axp20x-rsb.c | 1 +
> > drivers/mfd/axp20x.c | 3 +
> >
On Thu, 28 Jul 2016 15:28:42 +0200
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Wed, Jul 27, 2016 at 10:36:49AM +0200, Jean-Francois Moine wrote:
> > On Wed, 27 Jul 2016 09:40:20 +0200
> > Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> &g
The X-Powers AXP813 PMIC is close enough to the AXP809 with some
more outputs.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 32 -
drivers/mfd/axp20x-rsb.c | 1 +
drivers/mfd/ax
On Wed, 27 Jul 2016 08:59:34 +0200
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Tue, Jul 26, 2016 at 07:43:06PM +0200, Jean-Francois Moine wrote:
> > On Tue, 26 Jul 2016 15:04:26 +0800
> > Chen-Yu Tsai <w...@csie.org> wrote:
> >
> > >
On Wed, 27 Jul 2016 09:40:20 +0200
Maxime Ripard wrote:
> > > Parenting functions would also not work as expected,
> > > clk_hw_get_parent_by_index being the obvious example, in that case
> > > returning the empty string for an invalid parent, while it should
>
On Tue, 26 Jul 2016 15:04:27 +0800
Chen-Yu Tsai wrote:
> Some clocks on the A31 have fixed pre-dividers on multiple parents.
> Add support for them.
This could be done by intermediate clocks.
--
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |
On Tue, 26 Jul 2016 15:04:26 +0800
Chen-Yu Tsai wrote:
> Some clock muxes have holes, i.e. invalid or unconnected inputs,
> between parent mux values.
>
> Add support for specifying a mux table to map clock parents to
> mux values.
Putting empty strings in the holes should work.
On Tue, 26 Jul 2016 15:04:30 +0800
Chen-Yu Tsai wrote:
> +static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
> + { .index = 0, .div = 750, },
> + { .index = 3, .div = 4, },
> + { .index = 4, .div = 4, },
> +};
No end of table.
--
Ken ar c'hentañ |
On Thu, 21 Jul 2016 11:18:51 +0200
Jean-Francois Moine <moin...@free.fr> wrote:
> > On Wed, Jul 20, 2016 at 08:28:47PM +0200, Jean-Francois Moine wrote:
> > > The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.
> >
> > Uh? The datasheet say
On Thu, 21 Jul 2016 10:56:15 +0200
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Wed, Jul 20, 2016 at 08:16:28PM +0200, Jean-Francois Moine wrote:
> > The 'new timing mode' with 8 bits DDR works correctly when the NewTiming
> > register is set.
>
>
On Thu, 21 Jul 2016 10:58:38 +0200
Maxime Ripard <maxime.rip...@free-electrons.com> wrote:
> On Wed, Jul 20, 2016 at 08:28:47PM +0200, Jean-Francois Moine wrote:
> > The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.
>
> Uh? The datasheet says to set
The 'new timing mode' with 8 bits DDR works correctly when the NewTiming
register is set.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
Note about the 'new timing mode'.
This patch assumes that, when the new mode is used, the clock driver
sets the mode select in the MMC
The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.
This patch sets the phase delays of the output and sample clocks
accordingly.
Signed-off-by: Jean-Francois Moine <moin...@free.fr>
---
Note: The impacted phase delays are only for 50MHz.
The phase delays are not used in
On Fri, 15 Jul 2016 12:38:54 +0200
Ondřej Jirman wrote:
> > If so, then yes, trying to switch to the 24MHz oscillator before
> > applying the factors, and then switching back when the PLL is stable
> > would be a nice solution.
> >
> > I just checked, and all the SoCs we've
On Fri, 1 Jul 2016 02:50:57 +0200
Ondřej Jirman wrote:
> > Since this is really specific, I guess you could simply make the
> > clk_ops for the nkmp clocks public, and just re-implement set_rate
> > using that logic.
>
> I would argue that this may be necessary for other PLL
On Fri, 1 Jul 2016 08:34:21 +0200
Ondřej Jirman wrote:
> > The documentation says that only the CPU and DDR PLLs can be dynamically
> > changed after boot.
>
> The question is what exactly is meant by after boot. :) Anyway, if the
> kernel has no business changing some other
On Thu, 30 Jun 2016 23:16:35 +0200
Maxime Ripard wrote:
> > > I'm sorry, but the whole point of the initial serie was to rework and
> > > simplify things, precisely because dealing with the clk_factors code
> > > was just too difficult nowadays. And this doesn't
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