Hello Clément,
On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Thu, 30 May 2019 at 16:55, Ondřej Jirman wrote:
> >
> > Hello Clément,
> >
> > On Tue, May 28, 2019 at 06:14:38PM +0200, Clément Péron wrote:
> > > All
Hello,
On Mon, May 27, 2019 at 06:22:31PM +0200, megous via linux-sunxi wrote:
> From: Ondrej Jirman
>
> This series implements support for Xunlong Orange Pi 3 board.
>
> Unfortunately, this board needs some small driver patches, so I have
> split the boards DT patch into chunks that require pa
Hi Clément,
On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Fri, 31 May 2019 at 14:46, Ondřej Jirman wrote:
> >
> > Hello Clément,
> >
> > On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> > > Hi Ondrej
Hi Clément,
On Tue, Jun 04, 2019 at 02:33:55PM +0200, verejna wrote:
> Hi Clément,
>
> On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Fri, 31 May 2019 at 14:46, Ondřej Jirman wrote:
> > >
> > > Hello Cléme
On Tue, May 28, 2019 at 06:14:31PM +0200, Clément Péron wrote:
> Allwiner A31 has a different memory mapping so add the compatible
> we will need it later.
>
> Signed-off-by: Clément Péron
> ---
> drivers/media/rc/sunxi-cir.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/dri
Hi Clément,
On Tue, Jun 04, 2019 at 05:04:07PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Tue, 4 Jun 2019 at 16:47, Ondřej Jirman wrote:
> >
> > Hi Clément,
> >
> > On Tue, Jun 04, 2019 at 02:33:55PM +0200, verejna wrote:
> > > Hi Clément,
>
Hi Jernej,
On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
> napisal(a):
> > From: Ondrej Jirman
> >
> > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > with the IR gate.
> >
> > Clo
Hello Jernej,
On Tue, Jun 04, 2019 at 05:35:48PM +0200, Jernej Škrabec wrote:
> Hi!
>
> Dne torek, 04. junij 2019 ob 17:31:20 CEST je 'Ondřej Jirman' via linux-sunxi
> napisal(a):
> > Hi Jernej,
> >
> > On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Š
Hi Clément,
On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
> wrote:
> >
> > From: Ondrej Jirman
> >
> > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > with the IR gate.
> >
> > Clock g
On Tue, Jun 11, 2019 at 03:52:06PM -0600, Rob Herring wrote:
> On Mon, 27 May 2019 18:22:35 +0200, meg...@megous.com wrote:
> > From: Ondrej Jirman
> >
> > Some Allwinner SoC using boards (Orange Pi 3 for example) need to enable
> > on-board voltage shifting logic for the DDC bus using a gpio to
Hi Jernej,
On Sun, Jun 16, 2019 at 01:05:13PM +0200, Jernej Škrabec wrote:
> Hi Ondrej!
>
> Dne ponedeljek, 27. maj 2019 ob 18:22:36 CEST je megous via linux-sunxi
> napisal(a):
> > From: Ondrej Jirman
> >
> > Orange Pi 3 board requires enabling a voltage shifting circuit via GPIO
> > for the
Hi Jernej,
On Thu, Jun 20, 2019 at 05:53:58PM +0200, Jernej Škrabec wrote:
> Hi!
>
> Dne četrtek, 20. junij 2019 ob 15:47:42 CEST je megous via linux-sunxi
> napisal(a):
> > From: Ondrej Jirman
> >
> > This series implements support for Xunlong Orange Pi 3 board.
> >
> > - ethernet support (p
On Thu, Jun 20, 2019 at 03:47:42PM +0200, verejna wrote:
> From: Ondrej Jirman
>
> This series implements support for Xunlong Orange Pi 3 board.
>
> - ethernet support (patches 1-3)
> - HDMI support (patches 4-6)
>
> For some people, ethernet doesn't work after reboot (but works on cold
> boot)
Hi Icenowy,
I already tried this approach to changing CPUX_PLL and it didn't work
well. I've written a test program for CPUS (additional RISC-V processor
on H3 SoC) for testing various NKMP clock change algorithms, by
randomly changing the PLL frequency. Everything except simply not using
dividers
Hi Maxime,
Maxime Ripard píše v Po 10. 04. 2017 v 08:59 +0200:
> On Mon, Apr 10, 2017 at 12:19:41AM +0800, Icenowy Zheng wrote:
> > According to the researching result of Ondrej Jirman, the factor M of
> > PLL1 shouldn't be used and the factor P should be used only if the
> > intended frequency is
ver, he didn't add
> a Signed-off-by tag here to his commit. So I take this code and added my
> Signed-off-by.
Well, here it is if that helps:
Signed-off-by: Ondřej Jirman
Though this might be somewhat difficult change to make. It works
perfectly when combined with kernel that will not
icen...@aosc.io píše v Po 10. 04. 2017 v 18:15 +0800:
> 在 2017-04-10 18:06，Ondřej Jirman 写道：
> > Hi Maxime,
> >
> > Maxime Ripard píše v Po 10. 04. 2017 v 08:59 +0200:
> > > On Mon, Apr 10, 2017 at 12:19:41AM +0800, Icenowy Zheng wrote:
> > > > According
Hi Lawrence,
Thanks for your work. I may take you on your word some day. I've been
also working on reverse engineering the arisc firmware and figuring out
what it does. It's a bit bloated with various debug functionality, IR
code, clock setup, regulator setup, etc. I hope the core functionality
co
Hi,
I have working cpufreq for H5 in this branch:
https://github.com/megous/linux/commits/orange-pi-4.11
regards,
Ondrej
Menion píše v St 28. 06. 2017 v 03:07 -0700:
> Hi all
> Googling a little bit, I have found reference to a series of 5 patches
> Icenowy Zheng provided for adding cpufreq
Hi,
Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800:
> From: Icenowy Zheng
>
> Now we have driver for the PRCM CCU, switch to use it instead of
> old-style clock nodes for apb0-related clocks in sunxi-h3-h5.dtsi .
>
> The mux 3 of R_CCU is still the internal oscillator, which is said to be
>
Hi Icenowy,
icen...@aosc.io píše v Čt 20. 07. 2017 v 16:21 +0800:
> 在 2017-07-20 06:59，Ondřej Jirman 写道：
> > Hi,
> >
> > Icenowy Zheng píše v Út 04. 04. 2017 v 17:50 +0800:
> > > From: Icenowy Zheng
> > >
> > > Now we have driver for the PRCM
Hi,
icen...@aosc.io píše v St 26. 07. 2017 v 15:36 +0800:
>
> > > >
> > > > Otherwse
> > > >
> > > > > + regulator-max-microvolt = <140>;
> > > > > + regulator-ramp-delay = <200>;
> > > >
> > > > Is this an actual constraint of the SoC? Or is it a characteristic
Maxime Ripard píše v St 26. 07. 2017 v 13:44 +0200:
> Hi,
>
> On Wed, Jul 26, 2017 at 12:23:48PM +0200, Ondřej Jirman wrote:
> > Hi,
> >
> > icen...@aosc.io píše v St 26. 07. 2017 v 15:36 +0800:
> > >
> > > > > >
> > > > >
Hi,
Jagan Teki píše v St 30. 08. 2017 v 19:48 +0530:
> On Wed, Aug 30, 2017 at 2:40 PM, Philipp Rossak wrote:
> >
> >
> > Am 30.08.2017 um 08:47 schrieb Jagan Teki:
> > >
> > > On Wed, Aug 30, 2017 at 6:02 AM, Philipp Rossak wrote:
> > > >
> > > > From: Philipp Rossak
> > > >
> > > > The s
Hello Yong,
I noticed one issue in the register macros. See below.
Yong Deng píše v Čt 27. 07. 2017 v 13:01 +0800:
> Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> and CSI1 is used for parallel interface. This is not documented in
> datasheet but by testing and guess.
>
Hi,
there's some pattern. This is the lookup table that the BSP driver
uses:
https://github.com/megous/h3-firmware/blob/master/clk.c#L166
If you stray too much from this you'll get PLL lockups on change and
have to do some acrobatics to restart the PLL, which is kind of
pointless if it can be av
Hi,
Icenowy Zheng píše v St 01. 11. 2017 v 08:31 +0800:
>
> And according to the Orange Pi PC2 and Prime schematics, they both
> start at 1.1V. (The Prime schematics even says "For H5 adjust
> VDD-CPUX to 1.1V).
>
Orange Pi PC2 starts at the same voltage as Orange Pi PC. That is at
1.308V.
It
'Ondřej Jirman' via linux-sunxi píše v St 01. 11. 2017 v 03:10 +0100:
> Hi,
>
> Icenowy Zheng píše v St 01. 11. 2017 v 08:31 +0800:
> >
> > And according to the Orange Pi PC2 and Prime schematics, they both
> > start at 1.1V. (The Prime schematics even say
Hello,
Thanks for your patches. I've been working with CSI on A83T, so I have
a few notes. My review is below. :)
Yong Deng píše v Po 13. 11. 2017 v 15:30 +0800:
> Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> and CSI1 is used for parallel interface. This is not documen
Hi,
for flow control, you need to configure relevant flow control pins for uart2
function too too. Perhaps DTS and CTS?
Add:
&pio {
> uart2_pins_ctsrts: uart2-ctsrts {
> pins = "PA#", "PA#"; // replace # with number of the CTS/DTS pin
> function = "uart2";
};
You can check pinctrl code fo
r,function:
>
> Am I interpreting this correctly that this has been deprecated for the
> generic
> pinctrl bindings and should be renamed?
Yes.
regards,
o.
>
> On Thursday, November 16, 2017 at 8:38:40 PM UTC+1, Ondřej Jirman wrote:
> > Hi,
> >
Chris Obbard píše v Ne 26. 11. 2017 v 15:24 +:
> Hi guys,
> Looking into the COU core voltage regulator on the opipc2. By default,
> through resistors on the PCB, the regulator is set to 1.1V and should be set
> by u-boot to 1.2V before bringing up the cpu core PLL as the cpu is spec'd at
>
;
> On 26 November 2017 at 16:15, Ondřej Jirman wrote:
> > Chris Obbard píše v Ne 26. 11. 2017 v 15:24 +:
> > > Hi guys,
> > > Looking into the COU core voltage regulator on the opipc2. By default,
> > > through resistors on the PCB, the regulator is set to 1
up the next dma buffer for next frame before the
> the current frame done IRQ triggered. This is not documented
> but reported by Ondřej Jirman.
> The BSP code has workaround for this too. It skip to mark the
> first buffer as frame done for VB2 and pass the second buffer
>
Hello,
On Mon, Dec 25, 2017 at 11:15:26AM +0800, Yong wrote:
> Hi,
>
> On Fri, 22 Dec 2017 14:46:48 +0100
> Ondřej Jirman wrote:
>
> > Hello,
> >
> > Yong Deng píše v Pá 22. 12. 2017 v 17:32 +0800:
> > >
> > > Test input 0:
> > &g
On Thu, Jan 04, 2018 at 03:06:25PM +0100, Maxime Ripard wrote:
> On Mon, Dec 25, 2017 at 09:58:02AM +0100, Ondřej Jirman wrote:
> > Hello,
> >
> > On Mon, Dec 25, 2017 at 11:15:26AM +0800, Yong wrote:
> > > Hi,
> > >
> > > On Fri, 22 De
Hi,
On Wed, Mar 07, 2018 at 02:17:42PM -0800, @lex wrote:
> Hi Jernej,
>
> Unfortunately, this patch did not fix the issue, unless I did something
> silly.
> Here is the complete
> bootlog: https://gist.github.com/avafinger/ac6b5e73da87797c6ff32d6746e5fac5
>
> *code excerpt:*
>
> static void
Hi,
On Thu, Mar 01, 2018 at 10:34:32PM +0100, Jernej Skrabec wrote:
> Currently exclusive TCON clock lock is never released, which, for
> example, prevents changing resolution on HDMI.
>
> In order to fix that, release clock when disabling TCON. TCON is always
> disabled first before new mode is
Hi Jernej,
On Thu, Mar 08, 2018 at 11:57:40PM +0100, Jernej Škrabec wrote:
> Hi,
>
> Dne četrtek, 08. marec 2018 ob 23:47:17 CET je Ondřej Jirman napisal(a):
> > Hi,
> >
> > On Thu, Mar 01, 2018 at 10:34:32PM +0100, Jernej Skrabec wrote:
> > > Currentl
set_status(..., 1,
false)
is called multiple times, which leads to unbalanced calls to
clk_set_rate_exclusive
and clk_rate_exclusive_put.
I don't know how to fix this.
regards,
o.
On Fri, Mar 09, 2018 at 01:13:14AM +0100, 'Ondřej Jirman' via linux-sunxi wrote:
> Hi Jernej,
Hi,
On Fri, Mar 09, 2018 at 07:19:33AM +0100, Jernej Škrabec wrote:
> Hi,
>
> Dne petek, 09. marec 2018 ob 01:44:55 CET je Ondřej Jirman napisal(a):
> > Hi,
> >
> > I've debugged this further and it seems that the code has incorrect
> > assumptions. See
Hi,
mainline kernel contains:
&emac {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
And it works fine.
Seems like you're just missing status = "okay" for some reason.
Perhaps it is some merge issue in sunxi-next? I
On Tue, Mar 13, 2018 at 08:20:35PM +0100, Martin Lucina wrote:
> Hi,
>
> > > However, while running the debootstrap 2nd stage on the board, it seems
> > > that
> > > the kernel is not stable:
> >
> > Another thing to check if you are seeing stability issues is the power
> > supply (including cab
On Wed, Mar 14, 2018 at 12:52:22PM +0100, Martin Lucina wrote:
> On Wednesday, 14.03.2018 at 00:45, 'Ondřej Jirman' via linux-sunxi wrote:
> > On Tue, Mar 13, 2018 at 08:20:35PM +0100, Martin Lucina wrote:
> > > Hi,
> > >
> > > > > However, whil
On Sat, Apr 07, 2018 at 12:00:10PM +0800, Chen-Yu Tsai wrote:
> On Sat, Apr 7, 2018 at 1:11 AM, Paul Kocialkowski wrote:
> > Hi,
> >
> > One of the servers I'm running has recently rebooted due to a kernel
> > paging request that could not be handled correctly.
> >
> > The server is a Lamobo-R1 wi
f that changes
anything.
regards,
o.
> Thanks,
> Nuno
>
> On Monday, July 30, 2018 at 7:41:13 PM UTC+2, Ondřej Jirman wrote:
> >
> > Hi,
> >
> > there's issue in mainline kernel, where some NKMP CPU clock rate changes
> > lockup the ARM cores (or cause so
On Fri, Aug 10, 2018 at 11:44:17AM +0200, Ondřej Jirman wrote:
> Hi,
>
> On Thu, Aug 09, 2018 at 09:42:21AM -0700, Nuno Gonçalves wrote:
> > Dear Ondřej,
> >
> > Thank you. I applied this patches to linux and u-boot and the number of
> > crashes did reduce, bu
On Fri, Aug 10, 2018 at 02:55:03AM -0700, Nuno Gonçalves wrote:
>
> >
> >
> > You may try a stress test and toggle the cpufreq frequency settings
> > manually
> > in a fast loop, to see if you can reproduce it faster. Because, waiting 8h
> > or more for a crash is not optimal. :)
> >
> > If ye
n I do a stress test. Being the core voltage and frequency
> the same, what can be increasing the power consumption?
That sounds normal. When idle, the CPU is not consuming much, probably because
of WFI instruction.
regards,
o.
> Thanks!
>
>
> On Friday, August 10, 2018 at 12:46:22 PM
Hello,
On Thu, Aug 30, 2018 at 05:45:09PM +0200, Philipp Rossak wrote:
> This patch adds support for the H3 ths sensor.
>
> The H3 supports interrupts. The interrupt is configured to update the
> the sensor values every second. The calibration data is writen at the
> begin of the init process.
>
Hello,
On Thu, Aug 30, 2018 at 05:45:18PM +0200, Philipp Rossak wrote:
> Since we have now thermal trotteling enabeled we can now add the full
> range of the OPP table.
I'm not sure we can. I have a tablet with A83T SoC and it gets unstable
at these frequencies even with thermal throttling on mai
On Thu, Aug 30, 2018 at 05:44:57PM +0200, Philipp Rossak wrote:
> We want to use this driver mostly as thermal sensor, that still supports
> the adc for the older chips, thus we threat the A33 as thermal sensor.
> We also remove the adc channel without thermal support.
Threat -> treat (in the titl
Hi,
Dne 14.3.2017 v 07:53 Jernej Škrabec napsal(a):
> Hi,
>
> Dne ponedeljek, 13. marec 2017 ob 13:33:43 CET je Simon Glass napisal(a):
>> Hi,
>>
>> On 8 March 2017 at 16:34, Jernej Skrabec wrote:
>>> This is needed for HDMI, which will be added later.
>>>
>>> Signed-off-by: Jernej Skrabec
>>>
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