Mirthful day,
On Sun, Mar 02, 2014 at 09:44:19PM +, bugzilla-dae...@bugzilla.kernel.org
wrote:
https://bugzilla.kernel.org/show_bug.cgi?id=71431
--- Comment #1 from Greg Kroah-Hartman g...@kroah.com ---
On Sun, Mar 02, 2014 at 08:01:09PM +, bugzilla-dae...@bugzilla.kernel.org
Hi Tony,
On 03/01/2014 12:56 AM, Tony Lindgren wrote:
* Roger Quadros rog...@ti.com [140227 06:21]:
Hi,
This patchset brings up USB Host ports and Ethernet port on
the OMAP5 uEVM board.
It also does some cleanup with respect to DT clock binding
for the mfd/omap-usb-host driver.
Please
Add fsl,imx6q-usbphy for imx6dq and imx6dl, add
fsl,imx6sl-usbphy for imx6sl, and fsl,imx23-usbphy
is still a fallback for other strings.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
Documentation/devicetree/bindings/usb/mxs-phy.txt |6 +-
1 files changed, 5 insertions(+), 1
The auto setting is used to open related power and clocks
automatically after receiving wakeup signal.
With this feature, the PHY's clock and power can be recovered
correctly from low power mode, it is guaranteed by IC logic.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
It is needed by imx6 SoC series, but not for imx23 and imx28.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
The mxs-phy has several bugs and features at different
versions, the driver code can get it through of_device_id.data.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c | 58 ++--
1 files changed, 49 insertions(+), 9
Add anatop phandle which is used to access anatop registers to
control PHY's power and other USB operations.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
Documentation/devicetree/bindings/usb/mxs-phy.txt |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
The serial adds power management support for MXS PHY, it includes:
- Add one PHY API .set_wakeup, and related API implementation at mxs phy driver
- misc changes and bug fixes for mxs phy to support low power mode and wakeup.
It is based on the lastest Greg's 3.14-rc3.
Changes for v12:
- typo
We need to use controller id to access different register regions
for mxs phy.
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Shawn Guo shawn@linaro.org
---
arch/arm/boot/dts/imx23.dtsi |1 +
arch/arm/boot/dts/imx28.dtsi |2 ++
2 files changed, 3 insertions(+), 0
Add anatop phandle for usbphy
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Shawn Guo shawn@linaro.org
---
arch/arm/boot/dts/imx6qdl.dtsi |2 ++
arch/arm/boot/dts/imx6sl.dtsi |2 ++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git
This API is used to set wakeup enable at PHY registers, in that
case, the PHY can be waken up from suspend due to external events,
like vbus change, dp/dm change and id change.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
include/linux/usb/phy.h | 16
1 files
We need to use controller id to access different register regions
for mxs phy.
Signed-off-by: Peter Chen peter.c...@freescale.com
Signed-off-by: Shawn Guo shawn@linaro.org
---
arch/arm/boot/dts/imx6qdl.dtsi |2 ++
arch/arm/boot/dts/imx6sl.dtsi |2 ++
2 files changed, 4
Two PHY bugs are fixed by IC logic, but these bits are not
enabled by default, so we enable them at driver.
The two bugs are: MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
which are described at code.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
Change high speed to HS
Change non-high speed to FS/LS
Implementation of notify_suspend and notify_resume will be different
according to mxs_phy_data-flags.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c |8
1 files changed, 4 insertions(+), 4
After clear portsc.phcd, PHY needs 200us stable time for switch
32K clock to AHB clock.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-mxs-usb.c
When we need the PHY can be waken up by external signals,
we can call this API. Besides, we call mxs_phy_disconnect_line
at this API to close the connection between USB PHY and
controller, after that, the line state from controller is SE0.
Once the PHY is out of power, without calling
It is used to access un-regulator registers according to
different controllers.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
drivers/usb/phy/phy-mxs-usb.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/phy/phy-mxs-usb.c
We need this to keep PHY's power on or off during the system
suspend mode. If we need to enable USB wakeup, then we
must keep PHY's power being on during the system suspend mode.
Otherwise, we need to keep PHY's power being off to save power.
Signed-off-by: Peter Chen peter.c...@freescale.com
---
This series
* Adds suport for AM437x USB2 PHY driver
* Address DRA7 PHY errata for false disconnect
* New compatible for OMAP5
Austin Beam (1):
phy: omap-usb2: Provide workaround for USB2PHY false disconnect
George Cherian (2):
phy: omap-usb2: Adapt phy-omap-usb2
Adapt phy-omap-usb2 driver for AM437x.
- Add new comaptible ti,am437x-usb2 for AM437x
- Pass proper data to differentiate AM437x and others.
- AM437x doesnot support set_vbus and start_srp.
- Also update the Documentation to add new compatible.
Signed-off-by:
From: Austin Beam austinb...@ti.com
Enable the dra7x errata workaround for false disconnect problem
with USB2PHY. False disconnects were detected with some of the devices.
Reduce the sensitivity of the disconnect logic within the USB2PHY subsystem
to enusre these false disconnects are not
From: Austin Beam austinb...@ti.com
Enable the dra7x errata workaround for false disconnect problem
with USB2PHY. False disconnects were detected with some of the devices.
Reduce the sensitivity of the disconnect logic within the USB2PHY subsystem
to enusre these false disconnects are not
Add a new compatible for OMAP5 since it does not use any of the
OTG operations as of now.
HAS_SRP and SET_VBUS functionalities are used only for OMAP4.
Update the Documentation also to add new comaptible.
Signed-off-by: George Cherian george.cher...@ti.com
---
From: Alan Stern
When testing 3.14-rc1 with a USB 3.0 Lexar flash drive, the drive fails
to be mounted.
...
That revealed the SCSI request fails because the USB core is rejecting a
scatter-gather list with an entry that isn't aligned to the max packet size:
Feb 28 09:45:30 xanatos
From: Austin Beam austinb...@ti.com
Enable the dra7x errata workaround for false disconnect problem
with USB2PHY. False disconnects were detected with some of the devices.
Reduce the sensitivity of the disconnect logic within the USB2PHY subsystem
to enusre these false disconnects are not
Added device tree bindings for dwc3, usb2 and usb3 PHYs. The documentation
of these can be found at Documentation/devicetree/bindings/phy/phy-bindings.txt
and Documentation/devicetree/bindings/phy/ti-phy.txt.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |
No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/.
Also removed the unused members of struct omap_usb (after phy-omap-pipe3
started using it's own header file)
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-omap-usb2.c |2 +-
Added support for optional PHY in dwc3 as not all SoCs having PHYs for DWC3
should be programmed. While this can be considered as a temporary fix,
a long term solution would be to add 'nop' PHY for platforms that does
not have programmable PHY.
Adapted DWC3 and USB3 PHY to use Generic PHY
Now that omap-usb2 is adapted to the new generic PHY framework,
*set_suspend* ops can be removed from omap-usb2 driver.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/phy/phy-omap-usb2.c |
Adapted omap-usb3 PHY driver to Generic PHY Framework and moved phy-omap-usb3
driver in drivers/usb/phy to drivers/phy and also renamed the file to
phy-ti-pipe3 since this same driver will be used for SATA PHY and
PCIE PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Adapted dwc3 core to use the Generic PHY Framework. So for init, exit,
power_on and power_off the following APIs are used phy_init(), phy_exit(),
phy_power_on() and phy_power_off().
However using the old USB phy library wont be removed till the PHYs of all
other SoC's using dwc3 core is adapted
Since PHYs for dwc3 is optional (not all SoCs having PHYs for DWC3
should be programmed), do not return from probe if the USB PHY library
returns -ENODEV as that indicates the platform does not have a
programmable PHY.
While this can be considered as a temporary fix, a long term solution
would be
Hi Kishon,
Which tree are these patches based on?
cheers,
-roger
On 03/03/2014 01:38 PM, Kishon Vijay Abraham I wrote:
Added support for optional PHY in dwc3 as not all SoCs having PHYs for DWC3
should be programmed. While this can be considered as a temporary fix,
a long term solution would
Roger,
On Monday 03 March 2014 05:51 PM, Roger Quadros wrote:
Hi Kishon,
Which tree are these patches based on?
mainline + Felipe's testing/next + Revert usb: dwc3: core: enable
Suspend bit for USB2/3 PHYs + Revert usb: dwc3: preparation for
adapting dwc3 to generic phy framework
Thanks
hi all:
when I plug 3g modem dongle to ehci port, it works
But when I plug in xhci port, it cannot successfully doing the modem
mode change.
The related 3G modem driver should be independent by host type, right?
Below is my host environment
and I also attach log about plug in xhci and ehci.
( as
Hi,
On Wednesday 29 January 2014 10:59 PM, Kamil Debski wrote:
Add a new driver for the Exynos USB PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.
Can the PHY part of this series be merged independently of the
On 05.02.2014 18:30, Olof Johansson wrote:
On Wed, Feb 5, 2014 at 7:57 AM, Kamil Debski k.deb...@samsung.com wrote:
Hi Olof,
Thank you for your review.
From: Olof Johansson [mailto:o...@lixom.net]
Sent: Wednesday, January 29, 2014 9:55 PM
Hi,
On Wed, Jan 29, 2014 at 9:29 AM, Kamil Debski
Hi Kishon,
From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
Sent: Monday, March 03, 2014 3:28 PM
Hi,
On Wednesday 29 January 2014 10:59 PM, Kamil Debski wrote:
Add a new driver for the Exynos USB PHY. The new driver uses the
generic PHY framework. The driver includes support for
The OMAP_USB2 and OMAP_PIP3 phy devices will not be
detected if the OMAP_OCP2SCP driver is not present.
So select it.
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index
Due to Errata i783, SATA breaks if its DPLL is idled. The recommeded
workaround to issue a softreset to the SATA controller doesn't seem to
work. Here we just prevent SATA DPLL from Idling and hence avoid
the issue altogether.
Signed-off-by: Roger Quadros rog...@ti.com
---
From: Nikhil Devshatwar nikhil...@ti.com
Add hwmods for ocp2scp3 and sata modules.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Paul Walmsley p...@pwsan.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Nikhil Devshatwar nikhil...@ti.com
Signed-off-by: Roger
From: Balaji T K balaj...@ti.com
Add nodes for OCP2SCP3 bus, SATA controller and SATA PHY.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 39
From: Balaji T K balaj...@ti.com
Add support for sata.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 40
Limit .power_on() and .power_off() to just control the
PHY power and not the DPLL. The DPLL will be enabled
in .init() and idled in .exit().
Don't reprogram the DPLL if it has been already locked
by the bootloader. This fixes a problem with SATA, where
it fails if SATA was used by the bootloader.
From: Keshava Munegowda keshava_mgo...@ti.com
Create hwmods for ocp2scp3 and sata modules.
[Roger Q] Clean up.
CC: Benoit Cousson bcous...@baylibre.com
CC: Paul Walmsley p...@pwsan.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Balaji T K balaj...@ti.com
Signed-off-by: Roger Quadros
From: Kishon Vijay Abraham I kis...@ti.com
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the corresponding changes in the users
of phy-omap-control.
Signed-off-by:
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Update the DT binding information.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 3 +-
Hi,
This series adds SATA support for OMAP5 uevm and DRA7-evm boards.
- Cleans up the ti-pipe3 PHY driver
- Adds SATA DPLL support to ti-pipe3 PHY driver
- Adds SATA nodes to hwmod and SoC DT data
Patches are based on [1].
To test SATA you will also need [2].
[1] -
Move omap-control binding information to the right location.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 25 ++
Documentation/devicetree/bindings/usb/omap-usb.txt | 24 -
2 files changed, 25
The pipe3-phy driver expects certain named clocks.
Provide the necessary clocks.
CC: Benoît Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/omap5.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git
As this driver is no longer USB specific, use generic clock names.
- Fix PLL_SD_SHIFT from 9 to 10
- As optclk and wkupclk may not be always required, don't bail out
if they aren't available.
- Don't separate prepare/unprepare clock from enable/disable. This
ensures optimal power savings.
Hi,
On Thu, Feb 27, 2014 at 02:49:31PM +0800, Chuansheng Liu wrote:
When the request length is aligned to maxpacketsize, sometimes
the return length ret the user space requested len.
At that time, we will use min_t(size_t, ret, len) to limit the
size in case of user data buffer overflow.
On Fri, Feb 28, 2014 at 03:34:01PM +0100, Gregory CLEMENT wrote:
The debug trace in the atmel_usba_stop function made the assumption
that the driver pointer passed in parameter was not NULL. Since the
commit usb: gadget: udc-core: fix a regression during gadget driver
unbinding, it was no more
Hi,
On Mon, Mar 03, 2014 at 05:08:09PM +0530, Kishon Vijay Abraham I wrote:
Added support for optional PHY in dwc3 as not all SoCs having PHYs for DWC3
should be programmed. While this can be considered as a temporary fix,
a long term solution would be to add 'nop' PHY for platforms that does
On Mon, Mar 03, 2014 at 05:38:49PM +0100, Gregory CLEMENT wrote:
On 03/03/2014 17:33, Felipe Balbi wrote:
On Fri, Feb 28, 2014 at 03:34:01PM +0100, Gregory CLEMENT wrote:
The debug trace in the atmel_usba_stop function made the assumption
that the driver pointer passed in parameter was not
Hi,
On Sat, Mar 01, 2014 at 04:07:53AM +0300, Sergei Shtylyov wrote:
Add support of the device tree probing for the Renesas R-Car generation 2 SoCs
documenting the device tree binding as necessary.
Signed-off-by: Sergei Shtylyov sergei.shtyl...@cogentembedded.com
Unless someone on
On 03/03/2014 17:33, Felipe Balbi wrote:
On Fri, Feb 28, 2014 at 03:34:01PM +0100, Gregory CLEMENT wrote:
The debug trace in the atmel_usba_stop function made the assumption
that the driver pointer passed in parameter was not NULL. Since the
commit usb: gadget: udc-core: fix a regression
The debug trace in the atmel_usba_stop function made the assumption
that the driver pointer passed in parameter was not NULL. Since the
commit usb: gadget: udc-core: fix a regression during gadget driver
unbinding, it was no more always true. This lead to a kernel crash.
This commit now use the
On Mon, Mar 03, 2014 at 05:46:34PM +0100, Alexandre Belloni wrote:
Hi Felipe,
On 28/02/2014 at 15:35:42 +0100, Nicolas Ferre wrote :
On 27/02/2014 16:42, Alexandre Belloni :
If no endpoints are present in the device tree, the kernel will cras
hwith the
s/cras hwith/crash with/
Hello.
On 03/03/2014 07:44 PM, Felipe Balbi wrote:
Add support of the device tree probing for the Renesas R-Car generation 2 SoCs
documenting the device tree binding as necessary.
Signed-off-by: Sergei Shtylyov sergei.shtyl...@cogentembedded.com
Unless someone on devicetree@vger gives me
Hi Felipe,
On 28/02/2014 at 15:35:42 +0100, Nicolas Ferre wrote :
On 27/02/2014 16:42, Alexandre Belloni :
If no endpoints are present in the device tree, the kernel will cras hwith
the
s/cras hwith/crash with/
Do you want me to send a v2 with that typo corrected or could you
correct
Hi,
On Mon, Mar 03, 2014 at 08:50:33PM +0300, Sergei Shtylyov wrote:
Hello.
On 03/03/2014 07:44 PM, Felipe Balbi wrote:
Add support of the device tree probing for the Renesas R-Car generation 2
SoCs
documenting the device tree binding as necessary.
Signed-off-by: Sergei Shtylyov
On Sun, Mar 2, 2014 at 10:04 AM, Peter Stuge pe...@stuge.se wrote:
David Mosberger wrote:
+++ b/drivers/usb/host/Kconfig
@@ -4,6 +4,16 @@
comment USB Host Controller Drivers
depends on USB
+config USB_MAX3421_HCD
+ tristate MAX3421 HCD (USB-over-SPI) support
+
during the conversion to a new method of finding
proper endpoints, we need to give our users a
grace period until full conversion is finished.
This patch adds a new internal and temporary
__uses_feature_flags flag which will tell gadget
framework that this UDC has been converted to
the new
On Fri, Feb 28, 2014 at 08:55:43AM +0100, Robert Baldyga wrote:
On 12/17/2013 02:23 AM, Felipe Balbi wrote:
Start matching endpoints against feature flags,
this will help us dropping the naming conventions
currently used by the Gadget Framework.
Signed-off-by: Felipe Balbi ba...@ti.com
I've just installed the latest 3.14.0-rc5 kernel on an AMD box that
has the ASMedia 1042 xhci controller and an ASX ax88179 USB3 Ge card.
This is still working as badly as it did last time I tried it.
(When I added a lot of diagnostics to try to find out what was wrong.)
When I ran 'ifconfig
On 03/03/2014 at 17:48:34 +0100, Gregory CLEMENT wrote :
The debug trace in the atmel_usba_stop function made the assumption
that the driver pointer passed in parameter was not NULL. Since the
commit usb: gadget: udc-core: fix a regression during gadget driver
unbinding, it was no more always
Hi Greg,
Here's a small xhci fix for 3.14 rc
Only one patch that prevents a panic on xhci_suspend() during xhci
initialization
on some specific intel platforms if autosuspend is set to 0.
We're already at rc5 and I'm not sure what is acceptable anymore at this stage
in
the cycle.
-Mathias
xHCI driver has its own pci probe function that will call usb_hcd_pci_probe
to register its usb-2 bus, and then continue to manually register the
usb-3 bus. usb_hcd_pci_probe does a pm_runtime_put_noidle at the end and
might thus trigger a runtime suspend before the usb-3 bus is ready.
Prevent
Am 01.03.2014 12:13, schrieb Richard Schütz:
Am 26.02.2014 22:41, schrieb Richard Schütz:
Am 26.02.2014 16:31, schrieb Alan Stern:
On Tue, 25 Feb 2014, Sarah Sharp wrote:
On Tue, Feb 25, 2014 at 11:22:57PM +0100, Richard Sch�tz wrote:
Hi everybody!
I am experiencing a problem with my USB
* Roger Quadros rog...@ti.com [140303 07:11]:
The OMAP_USB2 and OMAP_PIP3 phy devices will not be
detected if the OMAP_OCP2SCP driver is not present.
So select it.
Selecting drivers like this will easily lead into missing
dependencies. Especially it's bad for tristate driver
options that
* Roger Quadros rog...@ti.com [140303 07:10]:
Move omap-control binding information to the right location.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 25
++
Documentation/devicetree/bindings/usb/omap-usb.txt |
On Fri, 28 Feb 2014, Dan Williams wrote:
A hub indicates whether it supports per-port power control via the
wHubCharacteristics field in its descriptor. If it is not supported
a hub will still emulate ClearPortPower(PORT_POWER) requests by
stopping the link state machine. However, since
From: Alan Stern st...@rowland.harvard.edu
Evidently some wacky USB-ATA bridges don't recognize the SYNCHRONIZE
CACHE command, as shown in this email thread:
http://marc.info/?t=13897835622r=1w=2
The fact that we can't tell them to drain their caches shouldn't
prevent the system
On Fri, 28 Feb 2014, Dan Williams wrote:
The current port name portX is ambiguous. Before adding more port
messages rename ports to hub-device-name-portX
This is an ABI change, but the suspicion is that it will go unnoticed as
the port power control implementation has been broken since its
On Fri, 28 Feb 2014, Dan Williams wrote:
Once usb-acpi has set the port's connect type the usb_device's
-removable attribute can be set in the standard location
set_usb_port_removable().
This also changes behavior in the case where the firmware says that the
port connect type is unknown.
On Mon, 2014-03-03 at 16:18 -0500, Alan Stern wrote:
On Fri, 28 Feb 2014, Dan Williams wrote:
A hub indicates whether it supports per-port power control via the
wHubCharacteristics field in its descriptor. If it is not supported
a hub will still emulate ClearPortPower(PORT_POWER)
On 03/01/2014 07:53 AM, David Mosberger wrote:
Attached is v0.1 of the max3421 driver. This one actually is trying to do
(mostly) the right things. It's event-driven (no busy-waiting anymore).
The URB-scheduling implemented in max3421_next_ep() is still simplistic: it
runs all periodic
On Mon, 17 Feb 2014, James Bottomley wrote:
You can tell by the way the stack trace doesn't mention USB at all. In
fact, this is a known SCSI problem. It has been fixed by these two
patches:
http://marc.info/?l=linux-scsim=139031645920152w=2
Greg, Dave, Freddy, question about cross-subsystem reverts below:
On Fri, Feb 28, 2014 at 04:15:12PM -0500, Alan Stern wrote:
On Fri, 28 Feb 2014, Sarah Sharp wrote:
When testing 3.14-rc1 with a USB 3.0 Lexar flash drive, the drive fails
to be mounted. I added a bit of debugging to the
On Mon, 2014-03-03 at 16:31 -0500, Alan Stern wrote:
On Fri, 28 Feb 2014, Dan Williams wrote:
The current port name portX is ambiguous. Before adding more port
messages rename ports to hub-device-name-portX
This is an ABI change, but the suspicion is that it will go unnoticed as
the
Hello everyone,
I'd like to encrypt my external HDD using dm-crypt (luks) via USB 3.0.
The crypto-container creation works, but writing to it doesn't:
kernel: usb 4-2: reset SuperSpeed USB device number 2 using xhci_hcd
kernel: xhci_hcd :00:14.0: xHCI xhci_drop_endpoint called with
On Fri, 28 Feb 2014, Dan Williams wrote:
Assume that the peer of a superspeed port is the port with the same id
on the shared_hcd root hub. This identification scheme is required of
external hubs by the USB3 spec [1]. However, for root hubs, tier mismatch
may be in effect [2]. Tier
From: Dinh Nguyen dingu...@altera.com
The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064
32-bit words. But the GRXFSIZ, GNPTXFSIZ, and HPTXFSIZ register defaults
to 0x2000 or 8192 32-bit words. So the driver
On 03.03.2014 22:55, Merlin Chlosta wrote:
% uname -r
3.13.5-1
(also tested on 3.14rc4)
It works on 3.10.30-1-lts, I forgot to mention that.
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On Mon, Mar 03, 2014 at 02:46:32PM -0800, Greg KH wrote:
On Mon, Mar 03, 2014 at 11:04:02AM -0600, Felipe Balbi wrote:
during the conversion to a new method of finding
proper endpoints, we need to give our users a
grace period until full conversion is finished.
Who are these users?
From: Dinh Nguyen dingu...@altera.com
Moves the s3c-hsotg driver into the dwc2 folder and use the dwc2 defines in
hw.h. The s3c-hostg driver will now be built with a kconfig option under
the dwc2 kconfig. USB_DWC2_HOST and USB_S3C_HSOTG are mutually exclusive
build options.
Signed-off-by: Dinh
From: Dinh Nguyen dingu...@altera.com
This patch moves the data structures that are in the s3c-hsotg source into
core.h. This is a necessary step towards unifying the s3c-hsotg and dwc2 into
a single DRD.
Signed-off-by: Dinh Nguyen dingu...@altera.com
Cc: Greg Kroah-Hartman
From: Dinh Nguyen dingu...@altera.com
Remove reading the fifo sizes from dts in platform.c
Add dwc2_calculate_dynamic_fifo
Conflicts:
arch/arm/boot/dts/socfpga.dtsi
drivers/staging/dwc2/core.c
---
arch/arm/boot/dts/socfpga.dtsi |8 ---
drivers/usb/dwc2/core.c|
From: Dinh Nguyen dingu...@altera.com
Hi,
This is a shortened version of the v1 patch to combine the dwc2/s3c-hsotg into
a single dual-role driver. The series will only move the s3c-hsotg driver into
the dwc2 folder, use the defines in the dwc2 hw.h, and removes the s3c-hsotg.h
defines. This
usbip userspace has duplicated enum definition to report usbip device
status maintained by the kernel. A new uapi usbip.h now defines the
usbip device status for kernel and userspace to use. Change usbip
userspace to include uapi usbip.h for usbip device status.
Signed-off-by: Shuah Khan
usbip userspace has duplicated enum definition to report usbip device
status maintained by the kernel. Adding an usbip uapi header file will
define the kernel - userspace interface for this device status. This
new uapi file is added under usbip/uapi to keep the staging tree code
self-contained.
usbip userspace has duplicated enum definition to report usbip device
status maintained by the kernel. Adding an usbip uapi header file will
define the kernel - userspace interface for this device status. This
new uapi file is added under usbip/uapi to keep the staging tree code
self-contained.
usbip userspace has duplicated enum definition to report usbip device
status maintained by the kernel. A new uapi usbip.h now defines the
usbip device status for kernel and userspace to use. Change usbip
kernel space to include uapi usbip.h for usbip device status.
Signed-off-by: Shuah Khan
On Mon, 2014-03-03 at 16:36 -0500, Alan Stern wrote:
On Fri, 28 Feb 2014, Dan Williams wrote:
Once usb-acpi has set the port's connect type the usb_device's
-removable attribute can be set in the standard location
set_usb_port_removable().
This also changes behavior in the case where
Yep basically the nic doesn't work with the Asmedia 1042.
Not only that though, I moved to a SandyBridge platform and...
The nic stops working very quickly when using an onboard Etron controller.
The nic also stops working quickly when using an addon card with Renesas
controller.
I have a
On Mon, 2014-03-03 at 17:21 -0500, Alan Stern wrote:
On Fri, 28 Feb 2014, Dan Williams wrote:
Assume that the peer of a superspeed port is the port with the same id
on the shared_hcd root hub. This identification scheme is required of
external hubs by the USB3 spec [1]. However, for
On Mon, Mar 3, 2014 at 5:13 PM, Dan Williams dan.j.willi...@intel.com wrote:
On Mon, 2014-03-03 at 17:21 -0500, Alan Stern wrote:
On Fri, 28 Feb 2014, Dan Williams wrote:
Assume that the peer of a superspeed port is the port with the same id
on the shared_hcd root hub. This identification
Can anyone please explain me, how runtime d3 works for xhci.
I am trying to understand generic code/control flow. When usb bus is
ideal, how RTD3 (runtime d3) will be triggered and which code is
involved in it.
Thank you.
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Pratik
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On Mon, 2014-03-03 at 17:13 -0800, Dan Williams wrote:
On Mon, 2014-03-03 at 17:21 -0500, Alan Stern wrote:
On Fri, 28 Feb 2014, Dan Williams wrote:
Assume that the peer of a superspeed port is the port with the same id
on the shared_hcd root hub. This identification scheme is
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