Signed-off-by: Aneesh Kumar K.V
---
.../include/asm/book3s/64/pgalloc-hash-4k.h| 26 ++---
.../include/asm/book3s/64/pgalloc-hash-64k.h | 23 ++--
arch/powerpc/include/asm/book3s/64/pgalloc-hash.h | 36 +--
arch/powerpc/include/asm/book3s/64/pgalloc.h | 118 +++
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 44 +
arch/powerpc/include/asm/book3s/64/pgtable.h | 49
arch/powerpc/mm/slb.c| 1 -
3 files changed, 64 insertions(+), 30 deletions(-)
Also split pgalloc 64k and 4k headers
Signed-off-by: Aneesh Kumar K.V
---
.../include/asm/book3s/64/pgalloc-hash-4k.h| 92 ++
.../include/asm/book3s/64/pgalloc-hash-64k.h | 51 ++
arch/powerpc/include/asm/book3s/64/pgalloc-hash.h | 59 ++
arch/powerpc/include/as
We will later make the generic functions do conditial radix or hash
page table access. This patch doesn't do hugepage api update yet.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 138 +++---
arch/powerpc/include/asm/book3s/64/pgtable.h | 262
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/book3s/64/pgalloc.h
b/arch/powerpc/include/asm/book3s/64/pgalloc.h
index f06ad7354d68..23b0dd07f9ae 100644
--- a/arch/powe
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/tlbflush-hash.h | 28 ++-
arch/powerpc/include/asm/book3s/64/tlbflush.h | 56 ++
arch/powerpc/include/asm/tlbflush.h| 2 +-
arch/powerpc/mm/tlb_hash64.c |
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 8
arch/powerpc/include/asm/book3s/64/hash.h| 9 +
arch/powerpc/include/asm/nohash/pgtable.h| 9 +
arch/powerpc/mm/hugetlbpage.c| 5 +
4 files changed, 27 insert
This is needed so that we can support both hash and radix page table
using single kernel. Radix kernel uses a 4 level table.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/asm/book3s/64/hash-4k.h | 33 +--
a
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgalloc.h | 6 +++---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 23 +++---
arch/powerpc/include/asm/book3s/pgalloc.h | 19 ++
.../asm/{pgalloc-32.h => nohash/32/pgallo
cp pgalloc-32.h book3s/32/pgalloc.h
cp pgalloc-64.h book3s/64/pgalloc.h
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgalloc.h | 109 +++
arch/powerpc/include/asm/book3s/64/pgalloc.h | 262 +++
2 files changed, 371 insertions(+)
create m
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/mmu-hash.h | 6 +-
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 61 +-
arch/powerpc/include/asm/book3s/64/mmu.h | 93 +++
arch/powerpc/include/asm/mmu.h| 25 +++-
No code changes. We will later add a radix variant that is big endian
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/page.h | 104 +--
arch/powerpc/include/asm/pgtable-types.h | 100 +
2 files changed, 101 insertions(
64bit book3s now always have 4 level page table irrespective of linux
page size. Move the related code out of #ifdef
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/pgalloc.h | 55 +---
1 file changed, 18 insertions(+), 37 deletions(-)
diff --git a
They are dependent on hash pte bits, so move them to hash64 header
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 42
arch/powerpc/include/asm/book3s/64/pgtable.h | 42
2 files changed, 42 insertions(+)
Not really needed. But this brings it back to as it was before
Check this
41743a4e34f0777f51c1cf0675b91508ba143050
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hash64_64k.c | 4 ++--
arch/powerpc/mm/hugepage-hash64.c| 2 +-
arch/powerpc/mm/hugetlbpage-hash64.c | 2 +-
3 files
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 10
arch/powerpc/include/asm/book3s/64/hash-64k.h | 14 +--
arch/powerpc/include/asm/book3s/64/pgalloc-hash.h | 7 ++
arch/powerpc/include/asm/book3s/64/pgalloc.h | 9 +++
a
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 1 +
arch/powerpc/include/asm/nohash/64/pgtable.h | 2 +
arch/powerpc/mm/Makefile | 3 +-
arch/powerpc/mm/init_64.c| 114 +
arch/powerpc/mm/mem.c
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/{mmu-hash32.h => book3s/32/mmu-hash.h} | 0
arch/powerpc/include/asm/{mmu-hash64.h => book3s/64/mmu-hash.h} | 0
arch/powerpc/include/asm/mmu.h | 4 ++--
arch/powerpc/kernel/idle_power7.S
With radix, we will have to dynamically switch between different
protection map. Hence override vm_get_page_prot instead of using
arch_vm_get_page_prot.We could also drop arch_vm_get_page_prot since
only powerpc define it. But then matching arch_calc_vm_prot_bits also
need to be changed. So for now
We will have different values for hash and radix. Hence we
cannot use #define constants. Add helper
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 5 +
arch/powerpc/include/asm/book3s/64/hash.h| 5 +
arch/powerpc/include/asm/nohash/pgtable.h| 5
Architecture supporting multiple page table formats have the hugepage
related values as variable. So we can't use them in #define constants
Signed-off-by: Aneesh Kumar K.V
---
arch/arm/include/asm/pgtable-3level.h | 8
arch/arm64/include/asm/pgtable.h | 7 +++
arch/mips/inclu
We need this to be the pte page not the pgtable_t
Signed-off-by: Aneesh Kumar K.V
---
include/linux/mm_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
index c67ea476991e..c9a1ebec07c4 100644
--- a/include/linux/mm_ty
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/tlbflush-hash.h | 94 ++
arch/powerpc/include/asm/tlbflush.h| 92 +
2 files changed, 95 insertions(+), 91 deletions(-)
create mode 100644 arch/powerpc/include/asm/book3s
They differ between radix and hash. Hence we need a helper
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 11 +++
arch/powerpc/include/asm/book3s/64/hash.h| 11 +++
arch/powerpc/include/asm/nohash/pgtable.h| 20
arc
This should not have any impact for hash linux implementation. But radix
would require us to flush tlb after clearing accessed bit. Also move
code that is not dependent on pte bits to generic header.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash.h| 45 +-
The radix variant is going to require a flush_tlb_range. We can't then
have this as static inline because of the usage of HPAGE_PMD_SIZE. So
we are forced to make it a function in which case we can use the generic
version.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/p
We will later make the generic functions do conditial radix or hash
page table access. This patch doesn't do hugepage api update yet.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 15 +
arch/powerpc/include/asm/book3s/64/hash.h| 12 ++-
arch/p
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/mmu_context.h | 63 +++---
arch/powerpc/kernel/swsusp.c | 2 +-
arch/powerpc/mm/mmu_context_hash64.c | 16 -
arch/powerpc/mm/mmu_context_nohash.c | 3 +-
drivers/cpufreq/pmac32-cpufreq
We strictly don't need to do this. But enables us to not depend on
pgtable_free_tlb for radix.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/hugetlbpage-book3e.c | 187 ++
arch/powerpc/mm/hugetlbpage-hash64.c | 150
arch/powerpc/
Hello,
This is a large series, mostly consisting of code movement. No new features
are done in this series. The changes are done to accomodate the upcoming new
memory
model in future powerpc chips. The details of the new MMU model can be found at
http://ibm.biz/power-isa3 (Needs registration)
This patch renames _PAGE* -> H_PAGE*. This enables us to support
different page table format in the same kernel.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 60 ++--
arch/powerpc/include/asm/book3s/64/hash-64k.h | 111
arch/powerpc/includ
We move large part of fsl related code to hugetlbpage-book3e.c.
Only code movement. This also avoid #ifdef in the code.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/hugetlb.h | 1 +
arch/powerpc/mm/hugetlbpage-book3e.c | 293 +
arch/powerpc/mm/hugetlbp
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/pgtable-hash64.c | 341 +++
arch/powerpc/mm/pgtable_64.c | 341 ---
2 files changed, 341 insertions(+), 341 deletions(-)
diff --git a/arch/powerpc/mm/pgtable-hash64.c b
Quite often drivers set only "write" permission assuming that this
includes "read" permission as well and this works on plenty platforms.
However IODA2 is strict about this and produces an EEH when "read"
permission is not and reading happens.
This adds a workaround in IODA code to always add the
On Tue, 2016-01-12 at 14:44 +1100, Stewart Smith wrote:
> Michael Ellerman writes:
> > On Fri, 2015-27-11 at 06:23:07 UTC, Russell Currey wrote:
> > > On BMC machines, console output is controlled by the OPAL firmware and is
> > > only flushed when its pollers are called. When the kernel is in a
Michael Ellerman writes:
> On Fri, 2015-27-11 at 06:23:07 UTC, Russell Currey wrote:
>> On BMC machines, console output is controlled by the OPAL firmware and is
>> only flushed when its pollers are called. When the kernel is in a panic
>> state, it no longer calls these pollers and thus console
On 01/10/2016 06:18 AM, Michael S. Tsirkin wrote:
On mips dma_rmb, dma_wmb, smp_store_mb, read_barrier_depends,
smp_read_barrier_depends, smp_store_release and smp_load_acquire match
the asm-generic variants exactly. Drop the local definitions and pull in
asm-generic/barrier.h instead.
This sta
On 11-01-16, 14:23, Greg KH wrote:
> On Mon, Jan 11, 2016 at 02:54:36PM -0600, Shilpasri G Bhat wrote:
> > In POWER8, OCC(On-Chip-Controller) can throttle the frequency of the
> > CPU when the chip crosses its thermal and power limits. Currently,
> > powernv-cpufreq driver detects and reports this
Mark Brown wrote:
Quite possibly (it'll be more efficient and it's intended for such use
cases) but as I said in my other reply that then has the issue that it
implicitly gives default values to all the registers so I'd expect we
still need to handle the cache initialisation explicitly (or
altern
On Mon, Jan 11, 2016 at 07:23:54PM -0600, Timur Tabi wrote:
> Mark Brown wrote:
> >regcache handles this fine, it's perfectly happy to just go and allocate
> >the cache as registers get used (this is why the code that's doing the
> >allocation exists...). What is causing problems here is that the
Mark Brown wrote:
regcache handles this fine, it's perfectly happy to just go and allocate
the cache as registers get used (this is why the code that's doing the
allocation exists...). What is causing problems here is that the first
access to the register is happening in interrupt context so we
On Wed, 2016-01-06 at 08:40 +, Lakshmi wrote:
> I have been trying to figure out what is the vector number used for external
> IRQ4 and IRQ5 in P4080ds.
>
> According to board document xpedite5470-p4080
> IRQ4: VPX GP Input 0 (GPI0)
> IRQ5 VPX GP Input 1 (GPI1)
>
> In p4080 user guide OpenPI
On Mon, 2016-01-11 at 21:19 +0530, Aneesh Kumar K.V wrote:
> Core kernel expect swp_entry_t to be consisting of
> only swap type and swap offset. We should not leak pte bits to
> swp_entry_t. This breaks swapoff which use the swap type and offset
> to build a swp_entry_t and later compare that to
On Mon, 2016-01-11 at 15:07 -0800, dwal...@fifo99.com wrote:
> On Tue, Jan 12, 2016 at 09:17:53AM +1100, Michael Ellerman wrote:
> > On Mon, 2016-01-11 at 08:49 -0800, dwal...@fifo99.com wrote:
> > > On Mon, Jan 11, 2016 at 02:09:34PM +1100, Michael Ellerman wrote:
> > > > On Fri, 2016-01-08 at 09:
On Tue, Jan 12, 2016 at 09:17:53AM +1100, Michael Ellerman wrote:
> On Mon, 2016-01-11 at 08:49 -0800, dwal...@fifo99.com wrote:
> > On Mon, Jan 11, 2016 at 02:09:34PM +1100, Michael Ellerman wrote:
> > > On Fri, 2016-01-08 at 09:45 -0800, dwal...@fifo99.com wrote:
> > > > Hi,
> > > >
> > > > A po
We used the PME_ prefix earlier to avoid some macro/variable name
collisions. We have since changed the way we define/use the event
macros so we no longer need the prefix.
By dropping the prefix, we keep the the event macros consistent with
their official names.
Reported-by: Michael Ellerman
Si
Power8 supports a large number of events in each susbystem so when a
user runs:
perf stat -e branch-instructions sleep 1
perf stat -e L1-dcache-loads sleep 1
it is not clear as to which PMU events were monitored.
Export the generic hardware and cache perf events for Power8 to sys
On Mon, Jan 11, 2016 at 02:54:36PM -0600, Shilpasri G Bhat wrote:
> In POWER8, OCC(On-Chip-Controller) can throttle the frequency of the
> CPU when the chip crosses its thermal and power limits. Currently,
> powernv-cpufreq driver detects and reports this event as a console
> message. Some machines
Michael Ellerman wrote on 01/10/2016 08:59:04 PM:
> From: Michael Ellerman
> To:
> Cc: tul...@linux.vnet.ibm.com, adhemerval.zane...@linaro.org,
> c...@linux.vnet.ibm.com, berg...@vnet.ibm.com, Steve Munroe/
> Rochester/IBM@IBMUS
> Date: 01/10/2016 08:59 PM
> Subject: [PATCH] powerpc: Add HWCAP
On Mon, 2016-01-11 at 08:49 -0800, dwal...@fifo99.com wrote:
> On Mon, Jan 11, 2016 at 02:09:34PM +1100, Michael Ellerman wrote:
> > On Fri, 2016-01-08 at 09:45 -0800, dwal...@fifo99.com wrote:
> > > Hi,
> > >
> > > A powerpc machine I'm working on has this problem where the
> > > simple_alloc_ini
On Mon, 2016-01-11 at 13:00 +0200, Michael S. Tsirkin wrote:
> As part of memory barrier cleanup, this patchset
> extends checkpatch to make it easier to stop
> incorrect memory barrier usage.
Thanks Michael.
Acked-by: Joe Perches
___
Linuxppc-dev mai
On Monday 11 January 2016 17:34:52 Scott Wood wrote:
> >>
> >> I think you need a 'depends on THERMAL' to prevent the driver from being
> >> built-in when THERMAL=m.
> >>
> >> Arnd
> >
> > Correct. I need to add following lines to the Kconfig file:
> > depends on !CPU_THERMAL || THERMAL=y
> >
> >
Create sysfs attributes to export throttle information in
/sys/devices/system/cpu/cpufreq/chipN. The newly added sysfs files are as
follows:
1)/sys/devices/system/cpu/cpufreq/chip0/throttle_frequencies
This gives the throttle stats for each of the available frequencies.
The throttle stat of a
Record the throttle event with a trace print replacing the printk,
except for events like throttling below nominal and occ reset
event which print a warning message.
Signed-off-by: Shilpasri G Bhat
---
Changes from v3:
- Separate this patch to contain trace_point changes
- Move struct chip member
This patch adds the powernv_throttle tracepoint to trace the CPU
frequency throttling event, which is used by the powernv-cpufreq
driver in POWER8.
Signed-off-by: Shilpasri G Bhat
CC: Ingo Molnar
CC: Steven Rostedt
---
No changes from v2 and v3.
include/trace/events/power.h | 22 +
cpu_to_chip_id() does a DT walk through to find out the chip id by taking a
contended device tree lock. This adds an unnecessary overhead in a hot-path.
So instead of cpu_to_chip_id() use PIR of the cpu to find the chip id.
Reported-by: Anton Blanchard
Signed-off-by: Shilpasri G Bhat
---
driver
In POWER8, OCC(On-Chip-Controller) can throttle the frequency of the
CPU when the chip crosses its thermal and power limits. Currently,
powernv-cpufreq driver detects and reports this event as a console
message. Some machines may not sustain the max turbo frequency in all
conditions and can be thro
On 01/11/2016 02:55 PM, Tulio Magno Quites Machado Filho wrote:
> "Carlos O'Donell" writes:
>
>> On 01/11/2016 10:16 AM, Tulio Magno Quites Machado Filho wrote:
>>> Adhemerval Zanella writes:
>>>
On 08-01-2016 13:36, Peter Bergner wrote:
> On Fri, 2016-01-08 at 11:25 -0200, Tulio Magno
On 01/11/2016 08:54 AM, Hongtao Jia wrote:
> Sorry for the late response. I got a knee surgery to do.
> See comments at the end.
>
>> -邮件原件-
>> 发件人: Arnd Bergmann [mailto:a...@arndb.de]
>> 发送时间: Saturday, December 19, 2015 6:33 AM
>> 收件人: Rafael J. Wysocki
>> 抄送: Jia Hongtao ; edubez...@g
Sorry for the late response. I got a knee surgery to do.
See comments at the end.
> -邮件原件-
> 发件人: Arnd Bergmann [mailto:a...@arndb.de]
> 发送时间: Saturday, December 19, 2015 6:33 AM
> 收件人: Rafael J. Wysocki
> 抄送: Jia Hongtao ; edubez...@gmail.com;
> viresh.ku...@linaro.org; linux...@vger.ker
On Mon, 11 Jan 2016, Aneesh Kumar K.V wrote:
> Core kernel expect swp_entry_t to be consisting of
> only swap type and swap offset. We should not leak pte bits to
> swp_entry_t. This breaks swapoff which use the swap type and offset
> to build a swp_entry_t and later compare that to the swp_entry_
"Carlos O'Donell" writes:
> On 01/11/2016 10:16 AM, Tulio Magno Quites Machado Filho wrote:
>> Adhemerval Zanella writes:
>>
>>> On 08-01-2016 13:36, Peter Bergner wrote:
On Fri, 2016-01-08 at 11:25 -0200, Tulio Magno Quites Machado Filho wrote:
> Peter, this solves the issue you repor
On Mon, Jan 11, 2016 at 02:09:34PM +1100, Michael Ellerman wrote:
> On Fri, 2016-01-08 at 09:45 -0800, dwal...@fifo99.com wrote:
> > Hi,
> >
> > A powerpc machine I'm working on has this problem where the
> > simple_alloc_init() area is trampling the initrd. The two are placed fairly
> > close tog
This fixes the incorrect return statement in the function
mpic_set_default_irq_routing from always returning zero
to signal success to this function's caller to instead
return the return value of kvm_set_irq_routing as this
function can fail and we need to correctly signal the
caller of mpic_set_de
On Mon, Jan 11, 2016 at 09:45:37AM -0600, Timur Tabi wrote:
> Ok, I'm confused. Granted, all of this regcache stuff was added after I
> stopped working on this driver, so I'm out of the loop. But it appears that
> the regcache cannot properly handle an uninitialized cache. I would expect
> it t
On 10/01/2016 01:54, Hugh Dickins wrote:
> Swapoff after swapping hangs on the G5, when CONFIG_CHECKPOINT_RESTORE=y
> but CONFIG_MEM_SOFT_DIRTY is not set. That's because the non-zero
> _PAGE_SWP_SOFT_DIRTY bit, added by CONFIG_HAVE_ARCH_SOFT_DIRTY=y, is not
> discounted when CONFIG_MEM_SOFT_DIRTY
Hi Timur,
Thanks for review.
On 10.01.2016 22:33, Timur Tabi wrote:
> Maciej S. Szmigiero wrote:
>> +regmap_write(regs, CCSR_SSI_SACNT,
>> +ssi_private->regcache_sacnt);
>
> So I'm not familiar with all of the regcache features, but I understand this
> patch.
> I was wondering i
Core kernel expect swp_entry_t to be consisting of
only swap type and swap offset. We should not leak pte bits to
swp_entry_t. This breaks swapoff which use the swap type and offset
to build a swp_entry_t and later compare that to the swp_entry_t
obtained from linux page table pte. Leaking pte bits
Mark Brown wrote:
That's possibly problematic because the flat cache will of necessity end
up with defaults (of 0 from the kzalloc()) for all the registers.
You'll still have default values in the cache, though some of the
behaviour around optimising syncs does change without them explicitly
give
Adhemerval Zanella writes:
> On 08-01-2016 13:36, Peter Bergner wrote:
>> On Fri, 2016-01-08 at 11:25 -0200, Tulio Magno Quites Machado Filho wrote:
>>> Peter, this solves the issue you reported previously [1].
>>>
>>> [1] https://sourceware.org/ml/libc-alpha/2015-12/msg00522.html
>>
>> Agreed,
On 01/11/2016 10:16 AM, Tulio Magno Quites Machado Filho wrote:
> Adhemerval Zanella writes:
>
>> On 08-01-2016 13:36, Peter Bergner wrote:
>>> On Fri, 2016-01-08 at 11:25 -0200, Tulio Magno Quites Machado Filho wrote:
Peter, this solves the issue you reported previously [1].
[1] h
On Mon, 11 Jan 2016 14:30:31 +1100
Michael Ellerman wrote:
> Sorry, yep I'll take it.
>
> I trimmed the change log a bit, final version below.
>
> cheers
>
Thanks, appreciate it!
-- Steve
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
On Mon, Jan 11, 2016 at 03:10:20PM +0100, Maciej S. Szmigiero wrote:
> On 11.01.2016 15:00, Mark Brown wrote:
> > I suspect not, it looks like the driver is using the cache for
> > suspend/resume handling. I've dropped the patch for now. Either the
> > driver should explicitly write to the relev
On Mon, Jan 11, 2016 at 10:10:56AM -0200, Fabio Estevam wrote:
> On Mon, Jan 11, 2016 at 10:04 AM, Fabio Estevam wrote:
> > [2.526984] [ cut here ]
> > [2.531632] WARNING: CPU: 1 PID: 1 at kernel/locking/lockdep.c:2755
> > lockdep_trace_alloc+0xf4/0x124()
> This f
On 11.01.2016 15:00, Mark Brown wrote:
> On Mon, Jan 11, 2016 at 10:10:56AM -0200, Fabio Estevam wrote:
>> On Mon, Jan 11, 2016 at 10:04 AM, Fabio Estevam wrote:
>
>>> [2.526984] [ cut here ]
>>> [2.531632] WARNING: CPU: 1 PID: 1 at kernel/locking/lockdep.c:2755
>>
Hi Maciej,
On Mon, Jan 11, 2016 at 11:57 AM, Maciej S. Szmigiero
wrote:
> Hi Fabio,
> This will disable register cache so it isn't right.
> Could you try REGCACHE_FLAT instead, please?
Yes, with REGCACHE_FLAT I don't get the warning.
Regards,
Fabio Estevam
632] WARNING: CPU: 1 PID: 1 at kernel/locking/lockdep.c:2755
>> lockdep_trace_alloc+0xf4/0x124()
>> [2.540771] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
>> [2.546175] Modules linked in:
>> [2.549447] CPU: 1 PID: 1 Comm: swapper/0 Not tainted
>> 4.4.0-rc8-n
On 01/11/2016 05:22 PM, Raghavendra K T wrote:
On 01/10/2016 04:33 AM, Jan Stancek wrote:
Hi,
I'm seeing bare metal ppc64le system crashing early during boot
with latest upstream kernel (4.4.0-rc8):
Jan,
Do you mind sharing the .config you used for the kernel.
Not able to reproduce with the
> [2.540771] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
> [2.546175] Modules linked in:
> [2.549447] CPU: 1 PID: 1 Comm: swapper/0 Not tainted
> 4.4.0-rc8-next-20160111 #204
> [2.557021] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
> [2.5
issue in linux-next:
[2.526984] [ cut here ]
[2.531632] WARNING: CPU: 1 PID: 1 at kernel/locking/lockdep.c:2755
lockdep_trace_alloc+0xf4/0x124()
[2.540771] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
[2.546175] Modules linked in:
[2.549447] CPU: 1 PID:
On 01/10/2016 04:33 AM, Jan Stancek wrote:
Hi,
I'm seeing bare metal ppc64le system crashing early during boot
with latest upstream kernel (4.4.0-rc8):
Jan,
Do you mind sharing the .config you used for the kernel.
Not able to reproduce with the one that I have :(
On 10/01/16 14:21, Michael S. Tsirkin wrote:
> drivers/xen/events/events_fifo.c uses rmb() to communicate with the
> other side.
>
> For guests compiled with CONFIG_SMP, smp_rmb would be sufficient, so
> rmb() here is only needed if a non-SMP guest runs on an SMP host.
>
> Switch to the virt_rmb
Hi Rob,
> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Wednesday, December 30, 2015 6:28 PM
> To: Igal Liberman
> Cc: devicet...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; Scott Wood
> ; Madalin-Cristian Bucur
> ; shaohui@freescale.com
> Subject: Re: [v
On Tue, Jan 05, 2016 at 12:09:30AM +, James Hogan wrote:
> Hi Michael,
>
> On Thu, Dec 31, 2015 at 09:08:22PM +0200, Michael S. Tsirkin wrote:
> > This defines __smp_xxx barriers for metag,
> > for use by virtualization.
> >
> > smp_xxx barriers are removed as they are
> > defined correctly b
Hi Michael,
On Mon, Jan 11, 2016 at 10:04 PM, Michael S. Tsirkin wrote:
> On Mon, Jan 11, 2016 at 12:59:25PM +0200, Michael S. Tsirkin wrote:
>> As part of memory barrier cleanup, this patchset
>> extends checkpatch to make it easier to stop
>> incorrect memory barrier usage.
>>
>> This replaces
On Mon, Jan 11, 2016 at 12:59:25PM +0200, Michael S. Tsirkin wrote:
> As part of memory barrier cleanup, this patchset
> extends checkpatch to make it easier to stop
> incorrect memory barrier usage.
>
> This replaces the checkpatch patches in my series
> arch: barrier cleanup + barriers for
Add virt_ barriers to list of barriers to check for
presence of a comment.
Signed-off-by: Michael S. Tsirkin
---
scripts/checkpatch.pl | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 25476c2..c7bf1aa 100755
--- a/scripts/c
Introduction of __smp barriers cleans up a bunch of duplicate code, but
it gives people an additional handle onto a "new" set of barriers - just
because they're prefixed with __* unfortunately doesn't stop anyone from
using it (as happened with other arch stuff before.)
Add a checkpatch test so it
SMP-only barriers were missing in checkpatch.pl
Refactor code slightly to make adding more variants easier.
Signed-off-by: Michael S. Tsirkin
---
scripts/checkpatch.pl | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/scripts/checkpatch.pl b/scripts/chec
As part of memory barrier cleanup, this patchset
extends checkpatch to make it easier to stop
incorrect memory barrier usage.
This replaces the checkpatch patches in my series
arch: barrier cleanup + barriers for virt
and will be included in the pull request including
the series.
changes
On Mon, Jan 11, 2016 at 09:40:18PM +1100, Julian Calaby wrote:
> Hi Michael,
>
> On Mon, Jan 11, 2016 at 9:35 PM, Michael S. Tsirkin wrote:
> > On Sun, Jan 10, 2016 at 02:52:16PM -0800, Joe Perches wrote:
> >> On Mon, 2016-01-11 at 09:13 +1100, Julian Calaby wrote:
> >> > On Mon, Jan 11, 2016 at
Hi Michael,
On Mon, Jan 11, 2016 at 9:35 PM, Michael S. Tsirkin wrote:
> On Sun, Jan 10, 2016 at 02:52:16PM -0800, Joe Perches wrote:
>> On Mon, 2016-01-11 at 09:13 +1100, Julian Calaby wrote:
>> > On Mon, Jan 11, 2016 at 6:31 AM, Michael S. Tsirkin
>> > wrote:
>> > > Add virt_ barriers to list
On Sun, Jan 10, 2016 at 02:52:16PM -0800, Joe Perches wrote:
> On Mon, 2016-01-11 at 09:13 +1100, Julian Calaby wrote:
> > On Mon, Jan 11, 2016 at 6:31 AM, Michael S. Tsirkin wrote:
> > > Add virt_ barriers to list of barriers to check for
> > > presence of a comment.
> []
> > > diff --git a/scrip
From: Madhavan Srinivasan
Add sample_reg_mask array with pt_regs registers.
This is needed for printing supported regs ( -I? option).
Signed-off-by: Madhavan Srinivasan
---
tools/perf/arch/powerpc/util/Build | 1 +
tools/perf/arch/powerpc/util/perf_regs.c | 48 ++
Map ID values with corresponding register names. These names are then
displayed when user issues perf record with the -I option
followed by perf report/script with -D option.
To test this patchset,
Eg:
$ perf record -I ls # record machine state at interrupt
$ perf script -D # read the perf
The perf infrastructure uses a bit mask to find out valid
registers to display. Define a register mask for supported
registers defined in asm/perf_regs.h. The bit positions also
correspond to register IDs which is used by perf infrastructure
to fetch the register values. CONFIG_HAVE_PERF_REGS enabl
This short patch series adds the ability to sample the interrupted
machine state for each hardware sample.
To test this patchset,
Eg:
$ perf record -I? # list supported registers
output:
available registers: gpr0 gpr1 gpr2 gpr3 gpr4 gpr5 gpr6 gpr7 gpr8 gpr9 gpr10
gpr11 gpr12 gpr13 gpr14
The enum definition assigns an 'id' to each register in "struct pt_regs"
of arch/powerpc. The order of these values in the enum definition are
based on the corresponding macros in arch/powerpc/include/uapi/asm/ptrace.h.
Signed-off-by: Anju T
Reviewed-by : Madhavan Srinivasan
---
arch/powerpc/i
When converting a swp_entry_t to pte, we need to add _PAGE_PTE,
because we later compare the pte with linux page table entries to
find a matching pte. We do set _PAGE_PTE on pte entries on linux page
table even if it is a swap entry. So add them when converting
swp_entry_t to pte_t
The stack trace
On Mon, 2015-21-12 at 06:38:41 UTC, Andrew Donnellan wrote:
> A few of the config prompts for powerpc self-tests have periods at the
> end, which is inconsistent with the rest of the prompts. Remove the
> periods.
>
> Signed-off-by: Andrew Donnellan
Applied to powerpc next, thanks.
https://git.
1 - 100 of 108 matches
Mail list logo
