On Fri, Sep 09, 2022 at 08:45:19AM +0800, Hamilton Alex wrote:
> Hi, Richard:
> I am not quite understand. I am using Calnex master-->board slave, if the
> linuxptp print out is correct, that means local clock
> has the same frequency and phase as master clock, then the 1PPS out should
> near the
Hi, Luigi:
yes, you are right. A mean path delay ~ 9us is reasonable, it is typical
Calnex behavior. I am using Calnex 100G.
Thanks
Alex
Luigi 'Comio' Mantellini 于2022年9月8日周四 21:42写道：
> A delay ~9ms is typical Calnex X behavior.
>
> Il giorno gio 8 set 2022 alle ore 15:29 Miroslav Lichvar
> h
Hi, Richard:
I am not quite understand. I am using Calnex master-->board slave, if the
linuxptp print out is correct, that means local clock
has the same frequency and phase as master clock, then the 1PPS out should
near the reference 1PPS.
why path asymmetry would affect the 1PPS out?
Thanks
A
Hi, Miroslav:
I am using calnex to test ptp. calnex can mimic the long path delay so it
is reasonable.
I am using switch chip, it has MAC timestamping and rx_delay, tx_delay are
compensated.
Thanks
Alex
Miroslav Lichvar 于2022年9月8日周四 21:26写道：
> On Thu, Sep 08, 2022 at 07:41:53PM +0800, Hamilton
On Thu, Sep 08, 2022 at 01:56:59PM +0200, Luigi 'Comio' Mantellini wrote:
> - How is the 1PPS driven? Is there any reclocking logic? You need to ask
> your FPGA-experts.
+1
The circuit the produces the 1 PPS could well delay the signal by ten
or more nanoseconds.
Thanks,
Richard
On Thu, Sep 08, 2022 at 06:40:26AM -0700, Richard Cochran wrote:
> On Thu, Sep 08, 2022 at 07:41:53PM +0800, Hamilton Alex wrote:
>
> > however, the 1pps time error is around 40 NS, which means my board is
> > ahead of the reference for about 40NS, which doesn't match the result
> > dumped by ptp
A delay ~9ms is typical Calnex X behavior.
Il giorno gio 8 set 2022 alle ore 15:29 Miroslav Lichvar
ha scritto:
>
> On Thu, Sep 08, 2022 at 07:41:53PM +0800, Hamilton Alex wrote:
> > ptp4l[130171.662]: rms1 max2 freq-49 +/- 3 delay 9058 +/- 0
>
> > my board has 1PPS output, I con
On Thu, Sep 08, 2022 at 07:41:53PM +0800, Hamilton Alex wrote:
> however, the 1pps time error is around 40 NS, which means my board is
> ahead of the reference for about 40NS, which doesn't match the result
> dumped by ptp4l.
>
> anyone has met similar issue before? how to debug such issue?
Th
On Thu, Sep 08, 2022 at 07:41:53PM +0800, Hamilton Alex wrote:
> ptp4l[130171.662]: rms1 max2 freq-49 +/- 3 delay 9058 +/- 0
> my board has 1PPS output, I connect it to the master and compared with
> reference PPS.
> however, the 1pps time error is around 40 NS, which means my bo
Hi, Luigi:
I am really thankful for your nice suggestions.
1. The delay for pps cable to calnex is already compensated in calnex
configuration.
2. Yes, RX and TX path are asymmetry. the calnex can measure the T1, T4
and 2way time error, those time errors are only a few nano seconds, that
means cor
s/guile/guide/g
Sorry...
ciao
luigi
Il giorno gio 8 set 2022 alle ore 13:56 Luigi 'Comio' Mantellini <
luigi.mantell...@gmail.com> ha scritto:
> Hi Alex,
>
> some guile line that I follow during my debug sessions:
>
> - Are you using a good cable-delay estimation for your cable? (Consider
> ~
Hi Alex,
some guile line that I follow during my debug sessions:
- Are you using a good cable-delay estimation for your cable? (Consider
~5ns/m for classical eth cables) I suggest you to physically measure the
delay and place it as Dcable cell in Calnex configuration.
- Have you checked about a
Hi:
I got an issue that linuxptp result doesn't match 1PPS measurement.
my board is acting as a slave, the calnex is acting as a master with
reference clock.
after ptp4l runs, result is below, looks pretty good:
ptp4l[130166.661]: rms1 max2 freq-50 +/- 4 delay 9059 +/- 0
ptp4l[130
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