[llvm-branch-commits] [llvm] release/18.x: [X86] Enable EVEX512 when host CPU has AVX512 (#90479) (PR #90545)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90545 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [RISCV][ISel] Fix types in `tryFoldSelectIntoOp` (#90659) (PR #90682)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90049 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

@@ -194,15 +194,12 @@ define void @vpmerge_vpload_store( %passthru, ptr %p, , i64 } @llvm.riscv.vleff.nxv2i32(, ptr, i64) define @vpmerge_vleff( %passthru, ptr %p, %m, i32 zeroext %vl) { ; CHECK-LABEL: vpmerge_vleff: ; CHECK: # %bb.0: -; CHECK-NEXT:vsetvli zero,

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -47,6 +47,12 @@ include "RISCVSchedSiFiveP600.td" include "RISCVSchedSyntacoreSCR1.td" include "RISCVSchedXiangShanNanHu.td" +//===--===// +// RISC-V profiles supported.

[llvm-branch-commits] [RISCV] Remove hasSideEffects=1 for saturating/fault-only-first instructions (PR #90049)

topperc wrote: > For saturating instructions, they may write vxsat. This is like floating-point instructions that may write fflags, but we don't model floating-point instructions as hasSideEffects=1. That's because floating point instructions use mayRaiseFPExceptions=1. And STRICT_* nodes set

[llvm-branch-commits] [llvm] release/18.x: [X86] Fix miscompile in combineShiftRightArithmetic (PR #86728)

topperc wrote: > > @phoebewang What do you think about backporting this? > > I didn't review on it. Maybe @topperc can evaluate it. I think this is ok to backport. https://github.com/llvm/llvm-project/pull/86728 ___ llvm-branch-commits mailing list

[llvm-branch-commits] [llvm] Revert "[Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072)" (PR #88818)

topperc wrote: > > Hi @nikic (or anyone else). If you would like to add a note about this fix > > in the release notes (completely optional). Please reply to this comment > > with a one or two sentence description of the fix. > > I'm not sure if this description is accurate: Fix the issue

[llvm-branch-commits] [RISCV] Use the thread local stack protector for Android targets (PR #87672)

topperc wrote: > s/master/main/ in the url to get the current version. (master "works" but > it's frozen in time; main will track future changes.) > > otherwise lgtm... Probably someone should update AArch64 which has the same comment? https://github.com/llvm/llvm-project/pull/87672

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -;

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -212,19 +185,13 @@ body: | ; CHECK-NEXT: $v7 = VMV1R_V $v14 ; CHECK-NEXT: $v8 = VMV1R_V $v15 ; CHECK-NEXT: $v9 = VMV1R_V $v16 -; CHECK-NEXT: $v4 = VMV1R_V $v10 -; CHECK-NEXT: $v5 = VMV1R_V $v11 -; CHECK-NEXT: $v6 = VMV1R_V $v12 -;

[llvm-branch-commits] [llvm] release/18.x: [Mips] Restore wrong deletion of instruction 'and' in unsigned min/max processing. (#85902) (PR #86424)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/86424 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV][NFC] Pass LMUL to copyPhysRegVector (PR #84448)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84448 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -483,90 +482,16 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock , } // VR->VR copies. - if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { -copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCVII::LMUL_1); -return; - } - - if

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

@@ -2001,8 +2225,6 @@ define i16 @test_umax_16(ptr nocapture %ptr, i16 signext %val) { ; MIPSELR6-NEXT: $BB6_1: # %entry ; MIPSELR6-NEXT:# =>This Inner Loop Header: Depth=1 ; MIPSELR6-NEXT:ll $2, 0($6) -; MIPSELR6-NEXT:and $2, $2, $8 topperc

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84566 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [Mips] Fix missing sign extension in expansion of sub-word atomic max (#77072) (PR #84566)

@@ -2001,8 +2225,6 @@ define i16 @test_umax_16(ptr nocapture %ptr, i16 signext %val) { ; MIPSELR6-NEXT: $BB6_1: # %entry ; MIPSELR6-NEXT:# =>This Inner Loop Header: Depth=1 ; MIPSELR6-NEXT:ll $2, 0($6) -; MIPSELR6-NEXT:and $2, $2, $8 topperc

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

topperc wrote: > > JFYI, I don't find the AArch64 data particularly convincing for RISCV. The > > magnitude of the change even on AArch64 is small, and could easily be swung > > one direction or the other by differences in implementation between the > > backends. > > Yeah! The result will

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -1046,6 +1046,14 @@ def FeatureFastUnalignedAccess def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; +def FeaturePredictableSelectIsExpensive + :

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, topperc wrote: > I think the impact

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84455 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Use larger copies when register tuples are aligned (PR #84455)

@@ -302,102 +302,87 @@ void RISCVInstrInfo::copyPhysRegVector(MachineBasicBlock , RISCVII::VLMUL LMul, unsigned NF) const { const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - unsigned Opc; - unsigned SubRegIdx; - unsigned

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/84894 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -14,12 +14,33 @@ #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H #include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #define GET_REGINFO_HEADER #include "RISCVGenRegisterInfo.inc" namespace llvm { +enum { + // The

[llvm-branch-commits] [llvm] [RISCV] Store VLMul/NF into RegisterClass's TSFlags (PR #84894)

@@ -14,12 +14,33 @@ #define LLVM_LIB_TARGET_RISCV_RISCVREGISTERINFO_H #include "llvm/CodeGen/TargetRegisterInfo.h" +#include "llvm/TargetParser/RISCVTargetParser.h" #define GET_REGINFO_HEADER #include "RISCVGenRegisterInfo.inc" namespace llvm { +enum { + // The

[llvm-branch-commits] [llvm][lld][RISCV] Support x3_reg_usage (PR #84598)

@@ -1136,11 +1136,35 @@ static void mergeAtomic(DenseMap , }; } +static void mergeX3RegUse(DenseMap , + const InputSectionBase *oldSection, + const InputSectionBase *newSection, + unsigned int

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, topperc wrote: But we added a bunch

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -101,6 +101,11 @@ static cl::opt EnableMISchedLoadClustering( cl::desc("Enable load clustering in the machine scheduler"), cl::init(false)); +static cl::opt +EnableSelectOpt("riscv-select-opt", cl::Hidden, topperc wrote: If no in tree targets

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

https://github.com/topperc deleted https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Support select optimization (PR #80124)

@@ -1046,6 +1046,14 @@ def FeatureFastUnalignedAccess def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", "UsePostRAScheduler", "true", "Schedule again after register allocation">; +def FeaturePredictableSelectIsExpensive + :

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

@@ -11724,13 +11726,27 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, Results.push_back(Result); break; } - case ISD::READCYCLECOUNTER: { -assert(!Subtarget.is64Bit() && - "READCYCLECOUNTER only has custom type legalization on riscv32"); +

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

@@ -363,7 +365,7 @@ def CSRSystemRegister : AsmOperandClass { let DiagnosticType = "InvalidCSRSystemRegister"; } -def csr_sysreg : RISCVOp { +def csr_sysreg : RISCVOp, ImmLeaf(Imm);"> { topperc wrote: TImmLeaf

[llvm-branch-commits] [llvm] [RISCV] Support llvm.readsteadycounter intrinsic (PR #82322)

@@ -126,9 +126,10 @@ enum NodeType : unsigned { // Floating point fmax and fmin matching the RISC-V instruction semantics. FMAX, FMIN, - // READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target - // (returns (Lo, Hi)). It takes a chain operand. -

[llvm-branch-commits] [RISCV] Support select optimization (PR #80124)

https://github.com/topperc edited https://github.com/llvm/llvm-project/pull/80124 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Support select optimization (PR #80124)

@@ -445,6 +450,9 @@ void RISCVPassConfig::addIRPasses() { if (EnableLoopDataPrefetch) addPass(createLoopDataPrefetchPass()); +if (EnableSelectOpt && getOptLevel() == CodeGenOptLevel::Aggressive) topperc wrote: Shoudl this be after addIRPasses

[llvm-branch-commits] [Clang][RISCV] Refactor builtins to TableGen (PR #80280)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/80280 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [RISCV] Backport 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112 to release/18.x (PR #79931)

topperc wrote: @tstellar Backport looks good to me. https://github.com/llvm/llvm-project/pull/79931 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] PR for llvm/llvm-project#79479 (PR #79907)

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/79907 Resolves https://github.com/llvm/llvm-project/issues/79479. >From 8fb154776db1627da75e6d67cf468d5b55868e93 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 25 Jan 2024 09:14:52 -0800 Subject: [PATCH 1/2]

[llvm-branch-commits] [llvm] b92bf0d - [RISCV] Disable clang-format around the RISCVISD opcode enum. NFC

Author: Craig Topper Date: 2023-11-29T14:01:30-08:00 New Revision: b92bf0dad6ec9760e008a0fa22d7dbd0b045c776 URL: https://github.com/llvm/llvm-project/commit/b92bf0dad6ec9760e008a0fa22d7dbd0b045c776 DIFF: https://github.com/llvm/llvm-project/commit/b92bf0dad6ec9760e008a0fa22d7dbd0b045c776.diff

[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC

Author: Craig Topper Date: 2023-11-22T19:49:52-08:00 New Revision: dc683d2e66de79bbea786f51788961eec5d0b793 URL: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793 DIFF: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff

[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.

Author: Craig Topper Date: 2023-11-22T18:59:41-08:00 New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c URL: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c DIFF: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff

[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC

Author: Craig Topper Date: 2023-11-22T19:49:52-08:00 New Revision: dc683d2e66de79bbea786f51788961eec5d0b793 URL: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793 DIFF: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff

[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.

Author: Craig Topper Date: 2023-11-22T18:59:41-08:00 New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c URL: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c DIFF: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff

[llvm-branch-commits] [llvm] dc683d2 - [X86] Remove unused IES_IDENTIFIER state from IntelExprState. NFC

Author: Craig Topper Date: 2023-11-22T19:49:52-08:00 New Revision: dc683d2e66de79bbea786f51788961eec5d0b793 URL: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793 DIFF: https://github.com/llvm/llvm-project/commit/dc683d2e66de79bbea786f51788961eec5d0b793.diff

[llvm-branch-commits] [llvm] e99ee06 - [X86] Reject fpsr in inline asm constraints other than clobber.

Author: Craig Topper Date: 2023-11-22T18:59:41-08:00 New Revision: e99ee06400404d3058e6f379465b9ac50aedb74c URL: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c DIFF: https://github.com/llvm/llvm-project/commit/e99ee06400404d3058e6f379465b9ac50aedb74c.diff

[llvm-branch-commits] [llvm] 4eb4f89 - [RISCV] Use sign extend for i32 arguments and returns in makeLibCall on RV64.

Author: Craig Topper Date: 2021-01-25T09:33:48-08:00 New Revision: 4eb4f8963f1e4998748bca66a512c3298f6d2289 URL: https://github.com/llvm/llvm-project/commit/4eb4f8963f1e4998748bca66a512c3298f6d2289 DIFF: https://github.com/llvm/llvm-project/commit/4eb4f8963f1e4998748bca66a512c3298f6d2289.diff

[llvm-branch-commits] [llvm] 12d0753 - [RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertzexti32.

Author: Craig Topper Date: 2021-01-24T13:58:14-08:00 New Revision: 12d0753aca22896fda2cf76781b0ee0524d55065 URL: https://github.com/llvm/llvm-project/commit/12d0753aca22896fda2cf76781b0ee0524d55065 DIFF: https://github.com/llvm/llvm-project/commit/12d0753aca22896fda2cf76781b0ee0524d55065.diff

[llvm-branch-commits] [llvm] f22aa8f - [RISCV] Add test cases for missed opportunities to use *W instructions for div/rem when inputs are sign/zero extended from i8/16 instead of i32.

Author: Craig Topper Date: 2021-01-24T13:56:38-08:00 New Revision: f22aa8f87931075834f973cebaa84c07ab1a26b1 URL: https://github.com/llvm/llvm-project/commit/f22aa8f87931075834f973cebaa84c07ab1a26b1 DIFF: https://github.com/llvm/llvm-project/commit/f22aa8f87931075834f973cebaa84c07ab1a26b1.diff

[llvm-branch-commits] [llvm] 60ebf64 - [RISCV] Add test cases for missed opportunities to use fcvt.*.w(u) instructions on RV64 when input is known to be extended from i8/i16.

Author: Craig Topper Date: 2021-01-24T13:48:29-08:00 New Revision: 60ebf6408e965635deb94bcdead8ac9451bf0ee9 URL: https://github.com/llvm/llvm-project/commit/60ebf6408e965635deb94bcdead8ac9451bf0ee9 DIFF: https://github.com/llvm/llvm-project/commit/60ebf6408e965635deb94bcdead8ac9451bf0ee9.diff

[llvm-branch-commits] [llvm] 116177a - [RISCV] Use SRLIWPat in the PACKUW pattern.

Author: Craig Topper Date: 2021-01-24T10:41:58-08:00 New Revision: 116177afcce88d807c1beffcb9221999ad8a69a9 URL: https://github.com/llvm/llvm-project/commit/116177afcce88d807c1beffcb9221999ad8a69a9 DIFF: https://github.com/llvm/llvm-project/commit/116177afcce88d807c1beffcb9221999ad8a69a9.diff

[llvm-branch-commits] [llvm] c50457f - [RISCV] Make the code in MatchSLLIUW ignore the lower bits of the AND mask where the shift has guaranteed zeros.

Author: Craig Topper Date: 2021-01-24T00:34:45-08:00 New Revision: c50457f3e4209b0cd0d4a6baa881bac30a9d3016 URL: https://github.com/llvm/llvm-project/commit/c50457f3e4209b0cd0d4a6baa881bac30a9d3016 DIFF: https://github.com/llvm/llvm-project/commit/c50457f3e4209b0cd0d4a6baa881bac30a9d3016.diff

[llvm-branch-commits] [llvm] c7d5d8f - [RISCV] Group some Zbs isel patterns together and remove a stale comment. NFC

Author: Craig Topper Date: 2021-01-23T16:45:05-08:00 New Revision: c7d5d8fa33a0f23b262b695d17fdffdefa8dc940 URL: https://github.com/llvm/llvm-project/commit/c7d5d8fa33a0f23b262b695d17fdffdefa8dc940 DIFF: https://github.com/llvm/llvm-project/commit/c7d5d8fa33a0f23b262b695d17fdffdefa8dc940.diff

[llvm-branch-commits] [llvm] 998057e - [RISCV] Add isel patterns to remove masks on SLO/SRO shift amounts.

Author: Craig Topper Date: 2021-01-23T15:57:41-08:00 New Revision: 998057ec06ae7e0fb1e0be0f2702df4d6338a128 URL: https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128 DIFF: https://github.com/llvm/llvm-project/commit/998057ec06ae7e0fb1e0be0f2702df4d6338a128.diff

[llvm-branch-commits] [llvm] 5a73daf - [RISCV] Add test cases for SRO/SLO with shift amounts masked to bitwidth-1. NFC

Author: Craig Topper Date: 2021-01-23T15:45:51-08:00 New Revision: 5a73daf907873a8757213932f814361a59f02da5 URL: https://github.com/llvm/llvm-project/commit/5a73daf907873a8757213932f814361a59f02da5 DIFF: https://github.com/llvm/llvm-project/commit/5a73daf907873a8757213932f814361a59f02da5.diff

[llvm-branch-commits] [llvm] d2927f7 - [RISCV] Add isel patterns to remove (and X, 31) from sllw/srlw/sraw shift amounts.

Author: Craig Topper Date: 2021-01-23T15:08:18-08:00 New Revision: d2927f786e877410d90c1e6f0e0c7d99524529c5 URL: https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5 DIFF: https://github.com/llvm/llvm-project/commit/d2927f786e877410d90c1e6f0e0c7d99524529c5.diff

[llvm-branch-commits] [llvm] 147c0c2 - [TargetLowering] Use isOneConstant to simplify some code. NFC

Author: Craig Topper Date: 2021-01-22T19:32:19-08:00 New Revision: 147c0c263d88a9702aba17fbeac62ff83e6c1319 URL: https://github.com/llvm/llvm-project/commit/147c0c263d88a9702aba17fbeac62ff83e6c1319 DIFF: https://github.com/llvm/llvm-project/commit/147c0c263d88a9702aba17fbeac62ff83e6c1319.diff

[llvm-branch-commits] [llvm] d65e8ee - [RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate.

Author: Craig Topper Date: 2021-01-22T14:51:22-08:00 New Revision: d65e8ee507f82ddca018267d0ce627518dd07337 URL: https://github.com/llvm/llvm-project/commit/d65e8ee507f82ddca018267d0ce627518dd07337 DIFF: https://github.com/llvm/llvm-project/commit/d65e8ee507f82ddca018267d0ce627518dd07337.diff

[llvm-branch-commits] [llvm] 607e5a5 - [RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32.

Author: Craig Topper Date: 2021-01-22T13:52:26-08:00 New Revision: 607e5a5000bddec24061b54a7e7955d51fe0d049 URL: https://github.com/llvm/llvm-project/commit/607e5a5000bddec24061b54a7e7955d51fe0d049 DIFF: https://github.com/llvm/llvm-project/commit/607e5a5000bddec24061b54a7e7955d51fe0d049.diff

[llvm-branch-commits] [llvm] 095e245 - [RISCV] Add isel patterns for SH*ADD(.UW)

Author: Craig Topper Date: 2021-01-22T13:28:41-08:00 New Revision: 095e245e164584b5de3c2938452b48d1f8ba4dda URL: https://github.com/llvm/llvm-project/commit/095e245e164584b5de3c2938452b48d1f8ba4dda DIFF: https://github.com/llvm/llvm-project/commit/095e245e164584b5de3c2938452b48d1f8ba4dda.diff

[llvm-branch-commits] [llvm] f25f7e8 - [RISCV] Add xperm.* instructions to Zbp extension.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff URL: https://github.com/llvm/llvm-project/commit/f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff DIFF: https://github.com/llvm/llvm-project/commit/f25f7e8ecd914baf5bcc0f51cb893d5a696d85ff.diff

[llvm-branch-commits] [llvm] 4d5aa76 - [RISCV] Add support for rev8 and orc.b to Zbb.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 4d5aa760a7d78b601fcfbda4d6196091a9188ea6 URL: https://github.com/llvm/llvm-project/commit/4d5aa760a7d78b601fcfbda4d6196091a9188ea6 DIFF: https://github.com/llvm/llvm-project/commit/4d5aa760a7d78b601fcfbda4d6196091a9188ea6.diff

[llvm-branch-commits] [llvm] 3c94cee - [RISCV] Add zext.h instruction to Zbb.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 3c94cee63b401ca12457395bb1f4d70e161f9ec4 URL: https://github.com/llvm/llvm-project/commit/3c94cee63b401ca12457395bb1f4d70e161f9ec4 DIFF: https://github.com/llvm/llvm-project/commit/3c94cee63b401ca12457395bb1f4d70e161f9ec4.diff

[llvm-branch-commits] [llvm] 83c92fd - [RISCV] Move pack instructions to Zbp extension only.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 83c92fdeda6be9a42739fa699926d41ce8a001fb URL: https://github.com/llvm/llvm-project/commit/83c92fdeda6be9a42739fa699926d41ce8a001fb DIFF: https://github.com/llvm/llvm-project/commit/83c92fdeda6be9a42739fa699926d41ce8a001fb.diff

[llvm-branch-commits] [llvm] 5ae92f1 - [RISCV] Change zext.w to be an alias of add.uw rd, rs1, x0 instead of pack.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 5ae92f1e11ab4ee23dee32f5a637abbed7fe2dcc URL: https://github.com/llvm/llvm-project/commit/5ae92f1e11ab4ee23dee32f5a637abbed7fe2dcc DIFF: https://github.com/llvm/llvm-project/commit/5ae92f1e11ab4ee23dee32f5a637abbed7fe2dcc.diff

[llvm-branch-commits] [llvm] efbcd66 - [RISCV] Rename Zbs instructions to start with just 'b' instead of 'sb' to match 0.93 bitmanip spec.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: efbcd66861dbfe4bb3c3c2d83515ca38bb7f18e2 URL: https://github.com/llvm/llvm-project/commit/efbcd66861dbfe4bb3c3c2d83515ca38bb7f18e2 DIFF: https://github.com/llvm/llvm-project/commit/efbcd66861dbfe4bb3c3c2d83515ca38bb7f18e2.diff

[llvm-branch-commits] [llvm] 9d499e0 - [RISCV] Modify add.uw patterns to put the masked operand in rs1 to match 0.93 bitmanip spec.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 9d499e037e6bc3365e6ad1423a388dc7a37627b0 URL: https://github.com/llvm/llvm-project/commit/9d499e037e6bc3365e6ad1423a388dc7a37627b0 DIFF: https://github.com/llvm/llvm-project/commit/9d499e037e6bc3365e6ad1423a388dc7a37627b0.diff

[llvm-branch-commits] [llvm] 1355458 - [RISCV] Move Shift Ones instructions from Zbb to Zbp to match 0.93 bitmanip spec.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 1355458ef665b3044e3dfb57acf0c2e7439560fe URL: https://github.com/llvm/llvm-project/commit/1355458ef665b3044e3dfb57acf0c2e7439560fe DIFF: https://github.com/llvm/llvm-project/commit/1355458ef665b3044e3dfb57acf0c2e7439560fe.diff

[llvm-branch-commits] [llvm] 4e6ad11 - [RISCV] Add Zba feature and move add.uw and slli.uw to it.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 4e6ad11bc6f29eecfbef7f5d5b7e581dd26e2024 URL: https://github.com/llvm/llvm-project/commit/4e6ad11bc6f29eecfbef7f5d5b7e581dd26e2024 DIFF: https://github.com/llvm/llvm-project/commit/4e6ad11bc6f29eecfbef7f5d5b7e581dd26e2024.diff

[llvm-branch-commits] [llvm] 83a93ae - [RISCV] Add SH*ADD(.UW) instructions to Zba extension based on 0.93 bitmanip spec.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 83a93ae63b1c8cc515a08c7fc4b78813e448c874 URL: https://github.com/llvm/llvm-project/commit/83a93ae63b1c8cc515a08c7fc4b78813e448c874 DIFF: https://github.com/llvm/llvm-project/commit/83a93ae63b1c8cc515a08c7fc4b78813e448c874.diff

[llvm-branch-commits] [llvm] d985c73 - [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: d985c7321f0b9cbaf8f8423a7faa645bb5966fc8 URL: https://github.com/llvm/llvm-project/commit/d985c7321f0b9cbaf8f8423a7faa645bb5966fc8 DIFF: https://github.com/llvm/llvm-project/commit/d985c7321f0b9cbaf8f8423a7faa645bb5966fc8.diff

[llvm-branch-commits] [llvm] b825278 - [RISCV] Rename mnemonics slliu.w->slli.uw and addu.w->add.uw to match 0.93 bitmanip spec.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: b825278364d9551ec3e8eb9f776f722238c9b3d8 URL: https://github.com/llvm/llvm-project/commit/b825278364d9551ec3e8eb9f776f722238c9b3d8 DIFF: https://github.com/llvm/llvm-project/commit/b825278364d9551ec3e8eb9f776f722238c9b3d8.diff

[llvm-branch-commits] [llvm] b2f8595 - [RISCV] Remove addiwu, addwu, subwu, subuw, clmulw, clmulrw, clmulhw to match 0.93 bitmanip spec.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: b2f859500f196f98a73d531c2ec847b7f23875af URL: https://github.com/llvm/llvm-project/commit/b2f859500f196f98a73d531c2ec847b7f23875af DIFF: https://github.com/llvm/llvm-project/commit/b2f859500f196f98a73d531c2ec847b7f23875af.diff

[llvm-branch-commits] [llvm] 6aced6b - [RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec.

Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: 6aced6bf396b78b0021a224bf210ffc3598c3047 URL: https://github.com/llvm/llvm-project/commit/6aced6bf396b78b0021a224bf210ffc3598c3047 DIFF: https://github.com/llvm/llvm-project/commit/6aced6bf396b78b0021a224bf210ffc3598c3047.diff

[llvm-branch-commits] [llvm] c953a83 - [TargetLowering] Use getBoolConstant instead of assuming zero or one for boolean contents.

Author: Craig Topper Date: 2021-01-22T00:26:14-08:00 New Revision: c953a8334707951d172e8061c8dc9054eb0c5c3f URL: https://github.com/llvm/llvm-project/commit/c953a8334707951d172e8061c8dc9054eb0c5c3f DIFF: https://github.com/llvm/llvm-project/commit/c953a8334707951d172e8061c8dc9054eb0c5c3f.diff

[llvm-branch-commits] [llvm] 5660dc5 - [TargetLowering] Simplify some code in SimplifySetCC that tries to handle SIGN_EXTEND_INREG operand types that should never happen. NFCI

Author: Craig Topper Date: 2021-01-21T23:56:37-08:00 New Revision: 5660dc5968ec6dacba1917b741d660c582f69e9e URL: https://github.com/llvm/llvm-project/commit/5660dc5968ec6dacba1917b741d660c582f69e9e DIFF: https://github.com/llvm/llvm-project/commit/5660dc5968ec6dacba1917b741d660c582f69e9e.diff

[llvm-branch-commits] [llvm] f8f1b20 - [RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions

Author: Craig Topper Date: 2021-01-21T19:29:02-08:00 New Revision: f8f1b20e6b30624d2c0d18dc6a2d61643650d0c4 URL: https://github.com/llvm/llvm-project/commit/f8f1b20e6b30624d2c0d18dc6a2d61643650d0c4 DIFF: https://github.com/llvm/llvm-project/commit/f8f1b20e6b30624d2c0d18dc6a2d61643650d0c4.diff

[llvm-branch-commits] [llvm] 4ab0f51 - Recommit "[RISCV] Legalize select when Zbt extension available"

Author: Michael Munday Date: 2021-01-21T12:07:44-08:00 New Revision: 4ab0f51a7518332b8b7691915b5fdad4c1ed045f URL: https://github.com/llvm/llvm-project/commit/4ab0f51a7518332b8b7691915b5fdad4c1ed045f DIFF:

[llvm-branch-commits] [llvm] 6cab3f8 - [RISCV] Use update_llc_test_checks.py to regenerate check lines in vleff-rv32.ll and vleff-rv64.ll.

Author: Craig Topper Date: 2021-01-20T18:51:02-08:00 New Revision: 6cab3f88ee4dbc59c8c5abb70490fea3f3f6d46c URL: https://github.com/llvm/llvm-project/commit/6cab3f88ee4dbc59c8c5abb70490fea3f3f6d46c DIFF: https://github.com/llvm/llvm-project/commit/6cab3f88ee4dbc59c8c5abb70490fea3f3f6d46c.diff

[llvm-branch-commits] [llvm] 0f8386c - [RISCV] Add addu.w and slliu.w test that uses getelementptr with zero extended indices.

Author: Craig Topper Date: 2021-01-20T14:54:40-08:00 New Revision: 0f8386c4f6aa804fe43814fcb3ae29d271da82d7 URL: https://github.com/llvm/llvm-project/commit/0f8386c4f6aa804fe43814fcb3ae29d271da82d7 DIFF: https://github.com/llvm/llvm-project/commit/0f8386c4f6aa804fe43814fcb3ae29d271da82d7.diff

[llvm-branch-commits] [llvm] e996f1d - [RISCV] Add another isel pattern for slliu.w.

Author: Craig Topper Date: 2021-01-20T14:54:40-08:00 New Revision: e996f1d4194bccf1c8ca984d695b848c0093bc23 URL: https://github.com/llvm/llvm-project/commit/e996f1d4194bccf1c8ca984d695b848c0093bc23 DIFF: https://github.com/llvm/llvm-project/commit/e996f1d4194bccf1c8ca984d695b848c0093bc23.diff

[llvm-branch-commits] [llvm] 9d792fe - [RISCV] Remove unnecessary APInt copy. NFC

Author: Craig Topper Date: 2021-01-20T10:33:09-08:00 New Revision: 9d792fef577843b213aa11954820512942dc31c7 URL: https://github.com/llvm/llvm-project/commit/9d792fef577843b213aa11954820512942dc31c7 DIFF: https://github.com/llvm/llvm-project/commit/9d792fef577843b213aa11954820512942dc31c7.diff

[llvm-branch-commits] [llvm] b11b6ab - [RISCV] Add way to mark CompressPats that should only be used for compressing.

Author: Craig Topper Date: 2021-01-20T09:20:15-08:00 New Revision: b11b6ab3e09464e88e57b69ff4a8fc8e1c00cc5b URL: https://github.com/llvm/llvm-project/commit/b11b6ab3e09464e88e57b69ff4a8fc8e1c00cc5b DIFF: https://github.com/llvm/llvm-project/commit/b11b6ab3e09464e88e57b69ff4a8fc8e1c00cc5b.diff

[llvm-branch-commits] [llvm] e75a4b6 - [RISCV] Remove NotHasStdExtZbb predicate from zext.h/sext.b/sext.h InstAliases. NFC

Author: Craig Topper Date: 2021-01-19T14:31:48-08:00 New Revision: e75a4b6ea9e950181049f1c2f8a78835754852fe URL: https://github.com/llvm/llvm-project/commit/e75a4b6ea9e950181049f1c2f8a78835754852fe DIFF: https://github.com/llvm/llvm-project/commit/e75a4b6ea9e950181049f1c2f8a78835754852fe.diff

[llvm-branch-commits] [llvm] ce8b393 - [RISCV] Add DAG combine to turn (setcc X, 1, setne) -> (setcc X, 0, seteq) if we can prove X is 0/1.

Author: Craig Topper Date: 2021-01-19T11:21:48-08:00 New Revision: ce8b3937ddad39536e6e715813682d9198229fb5 URL: https://github.com/llvm/llvm-project/commit/ce8b3937ddad39536e6e715813682d9198229fb5 DIFF: https://github.com/llvm/llvm-project/commit/ce8b3937ddad39536e6e715813682d9198229fb5.diff

[llvm-branch-commits] [llvm] 1c31459 - [RISCV] Remove empty Sched instantiations from the end of InstAlias defs. NFCI

Author: Craig Topper Date: 2021-01-18T14:08:29-08:00 New Revision: 1c31459153647a21da9b5cdbb01f78bccfb341a5 URL: https://github.com/llvm/llvm-project/commit/1c31459153647a21da9b5cdbb01f78bccfb341a5 DIFF: https://github.com/llvm/llvm-project/commit/1c31459153647a21da9b5cdbb01f78bccfb341a5.diff

[llvm-branch-commits] [llvm] 79e798a - Recommit "[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results."

Author: Craig Topper Date: 2021-01-18T11:08:28-08:00 New Revision: 79e798aca38baa260b9f3318991232dd1b5fc3f6 URL: https://github.com/llvm/llvm-project/commit/79e798aca38baa260b9f3318991232dd1b5fc3f6 DIFF: https://github.com/llvm/llvm-project/commit/79e798aca38baa260b9f3318991232dd1b5fc3f6.diff

[llvm-branch-commits] [llvm] 5d431c3 - Revert "[RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results."

Author: Craig Topper Date: 2021-01-18T11:00:20-08:00 New Revision: 5d431c3d32c7736d74c6a9dfe4a9a43f183d880f URL: https://github.com/llvm/llvm-project/commit/5d431c3d32c7736d74c6a9dfe4a9a43f183d880f DIFF: https://github.com/llvm/llvm-project/commit/5d431c3d32c7736d74c6a9dfe4a9a43f183d880f.diff

[llvm-branch-commits] [llvm] 2c51bef - [RISCV] Add a test of vector sadd.overflow to demonstrate intrinsics with multiple scalable vector results.

Author: Craig Topper Date: 2021-01-18T10:41:36-08:00 New Revision: 2c51bef76cbf0149101b9e7c7c658b4a58657929 URL: https://github.com/llvm/llvm-project/commit/2c51bef76cbf0149101b9e7c7c658b4a58657929 DIFF: https://github.com/llvm/llvm-project/commit/2c51bef76cbf0149101b9e7c7c658b4a58657929.diff

[llvm-branch-commits] [llvm] 383b650 - [RISCV] Use tail agnostic policy for instructions with tied defs if the use operand is IMPLICIT_DEF.

Author: Craig Topper Date: 2021-01-17T23:47:58-08:00 New Revision: 383b6501ffedc85c2ecfaa7852ec1a9e9c374e3f URL: https://github.com/llvm/llvm-project/commit/383b6501ffedc85c2ecfaa7852ec1a9e9c374e3f DIFF: https://github.com/llvm/llvm-project/commit/383b6501ffedc85c2ecfaa7852ec1a9e9c374e3f.diff

[llvm-branch-commits] [llvm] cfec6cd - [IR] Allow scalable vectors in structs to support intrinsics returning multiple values.

Author: Craig Topper Date: 2021-01-17T23:29:51-08:00 New Revision: cfec6cd50c36f3db2fcd4084a8ef4df834a4eb24 URL: https://github.com/llvm/llvm-project/commit/cfec6cd50c36f3db2fcd4084a8ef4df834a4eb24 DIFF: https://github.com/llvm/llvm-project/commit/cfec6cd50c36f3db2fcd4084a8ef4df834a4eb24.diff

[llvm-branch-commits] [llvm] 2b6a926 - [RISCV] Simplify mergeCondAndCode in RISCVCompressInstEmitter.cpp. NFC

Author: Craig Topper Date: 2021-01-16T20:59:48-08:00 New Revision: 2b6a92625fdf11928bff1a31cdc06d7dbd193f85 URL: https://github.com/llvm/llvm-project/commit/2b6a92625fdf11928bff1a31cdc06d7dbd193f85 DIFF: https://github.com/llvm/llvm-project/commit/2b6a92625fdf11928bff1a31cdc06d7dbd193f85.diff

[llvm-branch-commits] [llvm] 061f681 - [RISCV] Remove an extra map lookup from RISCVCompressInstEmitter. NFC

Author: Craig Topper Date: 2021-01-16T21:20:53-08:00 New Revision: 061f681c0dfa4d279dc656802bf81f3b9bfa3d34 URL: https://github.com/llvm/llvm-project/commit/061f681c0dfa4d279dc656802bf81f3b9bfa3d34 DIFF: https://github.com/llvm/llvm-project/commit/061f681c0dfa4d279dc656802bf81f3b9bfa3d34.diff

[llvm-branch-commits] [llvm] 1327c73 - [RISCV] Few more minor cleanups to RISCVCompressInstEmitter. NFC

Author: Craig Topper Date: 2021-01-16T21:09:43-08:00 New Revision: 1327c730bb9a0bff963af3745869cf244ae37241 URL: https://github.com/llvm/llvm-project/commit/1327c730bb9a0bff963af3745869cf244ae37241 DIFF: https://github.com/llvm/llvm-project/commit/1327c730bb9a0bff963af3745869cf244ae37241.diff

[llvm-branch-commits] [llvm] 97f7e4e - [RISC] Replace dyn_casts that are only checked by an assert with a cast. NFC

Author: Craig Topper Date: 2021-01-16T20:23:48-08:00 New Revision: 97f7e4e8c9309e0806f9b8f8afcf8ce2ef63656c URL: https://github.com/llvm/llvm-project/commit/97f7e4e8c9309e0806f9b8f8afcf8ce2ef63656c DIFF: https://github.com/llvm/llvm-project/commit/97f7e4e8c9309e0806f9b8f8afcf8ce2ef63656c.diff

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