Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

> On Feb 8, 2016, at 08:08, Tom Stellard wrote: > > Do SI/CI support fp64 denorms? If so, won't this hurt performance? This is the only mode that should ever be used. I’m not sure why these are options. There technically are separate flush on input or flush on output

Re: [Mesa-dev] [PATCH] st/mesa: move VS creation in bitmap code

On 02/08/2016 07:52 AM, Nicolai Hähnle wrote: On 05.02.2016 19:55, Brian Paul wrote: Do this one-time init with the other on-time inits. Since Bitmap is something that few programs use, wouldn't it be better to move in the other direction and do all the one-time inits on-demand rather than at

[Mesa-dev] [PATCH 04/23] i965: Don't try to create aux buffer for non-msrt aux-buffer

In addition to simply calling miptree_create() the higher level call intel_miptree_create() also considers if the buffer should be associated with an auxiliary buffer based on the given format. Here we are allocating an auxiliary buffer which in turn has such format that would mislead

[Mesa-dev] [PATCH 14/23] i965: Add means for limiting color resolves

Until now there has been only one type of color buffer that needs to resolved - namely single sampled fast clear. As even the sampler engine in GPU doesn't understand the associated meta data, the color values need to be always resolved prior to reading them. From SKL onwards there is new scheme

[Mesa-dev] [PATCH 20/23] i965: Expose logic telling if non-msrt mcs is supported

Alos use the opportunity to mark inputs constant. (Context has to be given as read-write to intel_miptree_supports_non_msrt_fast_clear() to support debug output). Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +

[Mesa-dev] [PATCH 16/23] i965: Add a few assertions on lossless compression

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 src/mesa/drivers/dri/i965/brw_context.c | 4 2 files changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp

[Mesa-dev] [PATCH 06/23] i965/gen9: Add buffer layout representing lossless compression

Skylake introduces compression support also for the single-sampled color buffers. Similarly to the multi-sampled case the color buffer will be associated with an auxiliary surface tracking the compression state. Signed-off-by: Topi Pohjolainen ---

[Mesa-dev] [PATCH 15/23] i965: Add a flag telling color resolve pass to ignore CCS_E

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 12 +++- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 9 + 3 files changed, 29 insertions(+), 2

[Mesa-dev] [PATCH 17/23] i965: Set buffer cleared after actually clearing it

Subsequent patch will modify the surface state to set state to unresolved whenever the surface is used as render target. Color resolve itself will use the same surface setup path and marking the buffer as cleared after the draw call ensures that the state correct after the resolve Signed-off-by:

[Mesa-dev] [PATCH 18/23] i965/gen9: Prepare surface state setup for lossless compression

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h| 1 + src/mesa/drivers/dri/i965/gen8_surface_state.c | 6 ++ 2 files changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h

[Mesa-dev] [PATCH 13/23] i965: Resolve color buffer also in lossless compression case

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index

[Mesa-dev] [PATCH 19/23] i965/gen9: Refactor msrt mcs initialization

This will be re-used to initialize auxiliary buffers in lossless compression case. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 --- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git

[Mesa-dev] [PATCH 01/23] i965: Let caller of intel_miptree_create_layout() decide msaa layout

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index

[Mesa-dev] [PATCH 08/23] i965: Allow fast clear to be used with lossless compression

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c index

[Mesa-dev] [PATCH 09/23] i965: Add resolve option for lossless compression

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h | 1 + src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 5 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h

[Mesa-dev] i965/gen9: Compression support for single-sampled

This series enables compression for single sampled color surfaces, also referred to as "lossless compression". This is yet only for driver internal use easing pressure on memory bandwidth and caches when writing, blending and sampling surfaces uing gpu. As a side effect the need for color buffer

[Mesa-dev] [PATCH 03/23] i965: Separate miptree creation from auxiliary buffer setup

Currently the logic allocating and setting up miptrees is closely combined with decision making when to re-allocate buffers in X-tiled layout and when to associate colors with auxiliary buffers. These auxiliary buffers are in turn also represented as miptrees and are created by the same miptree

[Mesa-dev] [PATCH 05/23] i965: Stop considering if msrt aux buffers need aux buffer

Auxiliary buffers are always created with sample number of zero which effectively prevents intel_miptree_create_layout() from trying to associate auxiliary buffers with auxiliary buffers. Now that there is more direct path available lets start using it instead and stop even checking for such

[Mesa-dev] [PATCH 07/23] i965/gen9: Allow halign == 16 also for losslessly compressed

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index

[Mesa-dev] [PATCH 12/23] i965: Refactor resolving of auxiliary mode

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 62 -- 1 file changed, 29 insertions(+), 33 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

> On Feb 8, 2016, at 08:08, Tom Stellard wrote: > > Do SI/CI support fp64 denorms? If so, won't this hurt performance? > > We should tell the compiler we are enabling fp-64 denorms by adding > +fp64-denormals to the feature string. It would also be better to > read the

Re: [Mesa-dev] [PATCH 1/2] draw: use util_pstipple_create_fragment_shader

On 02/08/2016 07:59 AM, Nicolai Hähnle wrote: Ping? Looks good. For both: Reviewed-by: Brian Paul On 22.01.2016 11:56, Nicolai Hähnle wrote: From: Nicolai Hähnle This reduces code duplication. It also adds support for drivers where the

[Mesa-dev] [PATCH 11/23] i965/gen8: Remove dead assertion

The assertion is inside a condition mandating num_samples > 1 and therefore the first half of the constraint is always met. The second half in turn would only be applicable for single sampled case and moreover it is trying to falsely check against surface type instead of format. Subsequent patches

[Mesa-dev] [PATCH 02/23] i965: Use miptree non-aligned dimensions directly for x-tiled

The logic in intel_miptree_create() uses the local copies for 64-byte aligned equivalent but only for stencil buffers which in turn are never x-tiled. This makes the logic a little more explicit and helps to keep subsequent patches easier to read. Signed-off-by: Topi Pohjolainen

[Mesa-dev] [PATCH 22/23] i965: Add helper for checking for lossless compressible

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21 + src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 21/23] i965/gen9: Setup MCS for compressed texture surfaces

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index

[Mesa-dev] [PATCH 23/23] i965/gen9: Enable lossless compression

I tried first creating the auxiliary buffer the same time with the color buffer. That, however, led me into a situation where we would later create the rest of the mip-levels and the compression would need to be disabled (it is only supported for single level buffers). Here we try to create it on

[Mesa-dev] [PATCH 10/23] i965: Use constant pointer when checking for compression

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_surface_formats.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h

Re: [Mesa-dev] [PATCH] winsys/radeon: fix a wrong NUM_TILE_PIPES value from the kernel

On 08.02.2016 04:25, Marek Olšák wrote: > From: Marek Olšák > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94019 > --- > src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git

Re: [Mesa-dev] [PATCH] mesa: move GL_ARB_debug_output code into new debug_output.c file

On 02/05/2016 06:28 PM, Timothy Arceri wrote: On Fri, 2016-02-05 at 17:54 -0700, Brian Paul wrote: The errors.c file had grown quite large so split off this extension code into its own file. This involved making a handful of functions non-static. I was going to do this when I added KHR_debug

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

On Sat, Feb 06, 2016 at 01:15:42PM +0100, Marek Olšák wrote: > From: Marek Olšák > > This fixes FP16 conversion instructions for VI, which has 16-bit floats, > but not SI & CI, which can't disable denorms for those instructions. Do you know why this fixes FP16 conversions?

[Mesa-dev] [PATCH 2/3] st/mesa: move the setup_bitmap_vertex_data() code into draw_bitmap_quad()

Now all the code to setup the vertex data and draw it is in one place. --- src/mesa/state_tracker/st_cb_bitmap.c | 168 -- 1 file changed, 78 insertions(+), 90 deletions(-) diff --git a/src/mesa/state_tracker/st_cb_bitmap.c b/src/mesa/state_tracker/st_cb_bitmap.c

[Mesa-dev] [PATCH 1/3] st/mesa: refactor some bitmap drawing code

Move setup/restoration of rendering state into helper functions. This makes the draw_bitmap_quad() function much more concise. --- src/mesa/state_tracker/st_cb_bitmap.c | 90 ++- 1 file changed, 57 insertions(+), 33 deletions(-) diff --git

[Mesa-dev] [PATCH 3/3] st/mesa: don't allocate bitmap drawing state until needed

Most apps don't use glBitmap so don't allocate the bitmap cache or gallium state objects/shaders/etc until the first call to st_Bitmap(). --- src/mesa/state_tracker/st_cb_bitmap.c | 145 ++ src/mesa/state_tracker/st_cb_bitmap.h | 3 -

Re: [Mesa-dev] [PATCH 2/7] st/mesa: implement GL_ATI_fragment_shader

I see that the shader doesn't specify texture target types and they must be obtained from the current GL states. That means texture targets have to be properly listed in the shader key. The shader compilation *must not* read any states from the current context. The shader key is the only place

Re: [Mesa-dev] [PATCH v2 i-g-t] igt/list-workarounds: Extend the script to Mesa

On Fri, Feb 05, 2016 at 04:12:08PM -0800, Dylan Baker wrote: > > > parse(work_arounds) > > > + print "\nList of workarounds found in %s:" % project > > Hey Damien, the script says it's python 3, and this ^^^ is broken syntax > in python 3 (but not in 2). :( I did notice the python2

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

On Mon, Feb 8, 2016 at 1:11 PM, Roland Scheidegger wrote: > This looks good to me, albeit I know nothing about the hw. > So VI could do (just with some restrictios) even full-speed fp32 denorms > whereas SI/CI can't? Interesting, I suppose that would be intended for Yes, VI

Re: [Mesa-dev] [PATCH 5/5] st/mesa: enable AoA for gallium drivers reporting GLSL 1.30

Cool, thanks. On Mon, 8 Feb 2016, 4:33 a.m. Dave Airlie wrote: > On 8 February 2016 at 14:26, Mike Lothian wrote: > > Does that also add in AoA for OpenGL ES 3.1 or will that require more > work? > > Good question, I've no idea. but I think desktop is >

Re: [Mesa-dev] [PATCH 0/2] Simple Klocwork patches

Hi, On 08.02.2016 00:07, Matt Turner wrote: On Sun, Feb 7, 2016 at 1:37 PM, Juha-Pekka Heikkilä wrote: I know there are lot of places where there is malloc unchecked still -- and then there is ralloc which is a story of its own. Reason why I think checking these

Re: [Mesa-dev] [PATCH 10/12] st/nine: Remove usage of SQRT in ff code

On Mon, Feb 8, 2016 at 12:33 AM, Ilia Mirkin wrote: > On Sun, Feb 7, 2016 at 6:26 PM, Axel Davy wrote: >> On 08/02/2016 00:21, Ilia Mirkin wrote: >>> >>> On Sun, Feb 7, 2016 at 6:13 PM, Axel Davy wrote: SQRT is not supported

Re: [Mesa-dev] [PATCH v2 4/5] st/mesa: make use of the occlusion predicate query

Reviewed-by: Marek Olšák On Sun, Feb 7, 2016 at 2:54 AM, Ilia Mirkin wrote: > Signed-off-by: Ilia Mirkin > Reviewed-by: Marek Olšák (v1) > > v1 -> v2: read .b for result of predicate > --- >

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

Am 06.02.2016 um 22:30 schrieb Marek Olšák: > On Sat, Feb 6, 2016 at 2:45 PM, Rob Clark wrote: >> On Sun, Jan 31, 2016 at 3:16 PM, Rob Clark wrote: >>> + // XXX get from pipe_screen? Or just let pipe driver provide? >>> + nir_options.lower_fpow =

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

This looks good to me, albeit I know nothing about the hw. So VI could do (just with some restrictios) even full-speed fp32 denorms whereas SI/CI can't? Interesting, I suppose that would be intended for compute. intel x86 can't even do that (actually, I think skylake can), though certainly other

[Mesa-dev] New stable-branch 11.1 candidate pushed

Hello list, The candidate for the Mesa 11.1.2 is now available. Currently we have: - 45 queued - 14 nominated (outstanding) - and 2 rejected/obsolete patches With the current queue nothing in particular stands out - we have fixes all over the place - core mesa, glsl, i965, nouveau, r600,

Re: [Mesa-dev] [PATCH] mesa: rewrite save_CallLists() code

On 02/08/2016 06:25 PM, Ian Romanick wrote: On 02/08/2016 05:06 PM, Brian Paul wrote: When glCallLists() is compiled into a display list, preserve the call as a single glCallLists rather than 'n' glCallList calls. This will matter for an upcoming display list optimization project. I think

[Mesa-dev] [Bug 94040] clGetPlatformIDs causes futex race condition

https://bugs.freedesktop.org/show_bug.cgi?id=94040 --- Comment #7 from b...@bob131.so --- In the specific case of blender, there are 31 hung up threads with around 9 each waiting on __lll_lock_wait () at ../sysdeps/unix/sysv/linux/x86_64/lowlevellock.S:135 pthread_cond_wait@@GLIBC_2.3.2 () at

Re: [Mesa-dev] [PATCH] [v2] i965: Make sure we blit a full compressed block

On Sat, Feb 6, 2016 at 6:11 PM, Ben Widawsky wrote: > This fixes an assertion failure in [at least] one of the Unreal Engine > Linux > demo/games that uses DXT1 compression. Specifically, the "Vehicle Game". > > At some point, the game ends up trying to blit mip

[Mesa-dev] [Bug 94040] clGetPlatformIDs causes futex race condition

https://bugs.freedesktop.org/show_bug.cgi?id=94040 --- Comment #8 from Francisco Jerez --- (In reply to bob from comment #7) > In the specific case of blender, there are 31 hung up threads with around 9 > each waiting on > > __lll_lock_wait () at

[Mesa-dev] Request for someone who understands viewports, clip control, etc

https://bugs.freedesktop.org/show_bug.cgi?id=93813 Can someone who *actually* understands what's going on rule on this one way or the other? I've tried to catch people's attention on IRC, but unsuccessfully. If this is a real bug, seems like a very bad one... -ilia

Re: [Mesa-dev] [PATCH v2] workarounds: Update workaround names and platforms

On Fri, Feb 05, 2016 at 01:59:23PM -0800, Sameer Kibey wrote: > Update the format in which workarounds are documented > in the source code. This allows mesa to be parsed > by the list-workarounds utility in intel-gpu-tools. > > Signed-off-by: Sameer Kibey > --- > changed

Re: [Mesa-dev] [PATCH 4/7] mesa: remove check_compatible() in make_current

On 02/05/2016 01:11 PM, Miklós Máté wrote: > this was marked for removal since 2007 > ctx::Visual is also removed, since this was its only legit user > --- > .../drivers/dri/radeon/radeon_common_context.c | 2 +- > src/mesa/main/blend.c | 4 +- >

Re: [Mesa-dev] [PATCH] [v2] i965: Make sure we blit a full compressed block

On Sat, Feb 6, 2016 at 6:11 PM, Ben Widawsky wrote: > This fixes an assertion failure in [at least] one of the Unreal Engine Linux > demo/games that uses DXT1 compression. Specifically, the "Vehicle Game". > > At some point, the game ends up trying to blit mip level

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

> On Feb 8, 2016, at 12:38, Marek Olšák wrote: > >> >> We should tell the compiler we are enabling fp-64 denorms by adding >> +fp64-denormals to the feature string. It would also be better to >> read the float_mode value from the config registers emitted by the >> compiler.

Re: [Mesa-dev] [PATCH v2 0/5] st/mesa: use PIPE_QUERY_OCCLUSION_PREDICATE

Patch 4 & 5: Reviewed-by: Nicolai Hähnle On 06.02.2016 20:53, Ilia Mirkin wrote: Resending this as a bunch of the patches ended up with updates. They seem rather trivial, but wanted to make sure people had a chance to object. Ilia Mirkin (5): ilo: add

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger wrote: > Am 06.02.2016 um 22:30 schrieb Marek Olšák: >> On Sat, Feb 6, 2016 at 2:45 PM, Rob Clark wrote: >>> On Sun, Jan 31, 2016 at 3:16 PM, Rob Clark wrote: + // XXX get

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

On 06.02.2016 07:15, Marek Olšák wrote: From: Marek Olšák This fixes FP16 conversion instructions for VI, which has 16-bit floats, but not SI & CI, which can't disable denorms for those instructions. Reviewed-by: Nicolai Hähnle ---

Re: [Mesa-dev] [PATCH] st/mesa: move VS creation in bitmap code

On 05.02.2016 19:55, Brian Paul wrote: Do this one-time init with the other on-time inits. Since Bitmap is something that few programs use, wouldn't it be better to move in the other direction and do all the one-time inits on-demand rather than at context init? Cheers, Nicolai ---

Re: [Mesa-dev] [PATCH 1/2] draw: use util_pstipple_create_fragment_shader

Ping? On 22.01.2016 11:56, Nicolai Hähnle wrote: From: Nicolai Hähnle This reduces code duplication. It also adds support for drivers where the fragment position is a system value. Suggested-by: Jose Fonseca --- A basic polygon stippling test

Re: [Mesa-dev] [PATCH] gallium: pass the robust buffer access context flag to drivers

On 06.02.2016 16:26, Marek Olšák wrote: From: Marek Olšák radeonsi will not do bounds checking for loads if this is not set. --- src/gallium/include/pipe/p_defines.h | 6 ++ src/mesa/state_tracker/st_manager.c | 6 +- 2 files changed, 11 insertions(+), 1

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

On Mon, Feb 8, 2016 at 1:01 PM, Ilia Mirkin wrote: > On Mon, Feb 8, 2016 at 8:59 AM, Rob Clark wrote: >> On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger >> wrote: >>> Am 06.02.2016 um 22:30 schrieb Marek Olšák: On Sat, Feb

Re: [Mesa-dev] [PATCH 4/5] nir: Handle large unsigned values in opt_algebraic.

This seems perfectly fine to me. For what it's worth: Reviewed-by: Dylan Baker Quoting Matt Turner (2016-02-04 17:48:00) > The next patch adds an algebraic rule that uses the constant 0xff00ff00. > > Without this change, the build fails with > >return

Re: [Mesa-dev] [PATCH v2] workarounds: Update workaround names and platforms

> -Original Message- > From: Widawsky, Benjamin > Sent: Saturday, February 06, 2016 10:30 AM > To: Kibey, Sameer > Cc: mesa-dev@lists.freedesktop.org; Sharp, Sarah A > Subject: Re: [PATCH v2] workarounds: Update workaround names and > platforms > > On Fri, Feb 05, 2016 at 01:59:23PM

Re: [Mesa-dev] [PATCH v2] workarounds: Update workaround names and platforms

On Mon, Feb 08, 2016 at 09:09:30AM -0800, Kibey, Sameer wrote: > > > > -Original Message- > > From: Widawsky, Benjamin > > Sent: Saturday, February 06, 2016 10:30 AM > > To: Kibey, Sameer > > Cc: mesa-dev@lists.freedesktop.org; Sharp, Sarah A > > Subject: Re: [PATCH v2] workarounds:

Re: [Mesa-dev] [PATCH 3/3] st/mesa: don't allocate bitmap drawing state until needed

2016-02-08 18:07 GMT+01:00 Brian Paul : > Most apps don't use glBitmap so don't allocate the bitmap cache or > gallium state objects/shaders/etc until the first call to st_Bitmap(). > --- > src/mesa/state_tracker/st_cb_bitmap.c | 145 > ++ >

Re: [Mesa-dev] [PATCH 3/5] nir: Do opt_algebraic in reverse order.

On Feb 8, 2016 9:17 AM, "Matt Turner" wrote: > > On Sun, Feb 7, 2016 at 8:06 AM, Jason Ekstrand wrote: > > > > On Feb 4, 2016 5:45 PM, "Matt Turner" wrote: > >> > >> Walking the SSA definitions in order means that we consider the

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

Am 08.02.2016 um 14:59 schrieb Rob Clark: > On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger wrote: >> Am 06.02.2016 um 22:30 schrieb Marek Olšák: >>> On Sat, Feb 6, 2016 at 2:45 PM, Rob Clark wrote: On Sun, Jan 31, 2016 at 3:16 PM, Rob Clark

Re: [Mesa-dev] [PATCH 3/3] st/mesa: don't allocate bitmap drawing state until needed

On 02/08/2016 10:10 AM, Gustaw Smolarczyk wrote: 2016-02-08 18:07 GMT+01:00 Brian Paul : Most apps don't use glBitmap so don't allocate the bitmap cache or gallium state objects/shaders/etc until the first call to st_Bitmap(). --- src/mesa/state_tracker/st_cb_bitmap.c | 145

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

On Mon, Feb 8, 2016 at 8:59 AM, Rob Clark wrote: > On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger wrote: >> Am 06.02.2016 um 22:30 schrieb Marek Olšák: >>> On Sat, Feb 6, 2016 at 2:45 PM, Rob Clark wrote: On Sun, Jan 31,

Re: [Mesa-dev] [PATCH 3/5] nir: Do opt_algebraic in reverse order.

On Sun, Feb 7, 2016 at 8:06 AM, Jason Ekstrand wrote: > > On Feb 4, 2016 5:45 PM, "Matt Turner" wrote: >> >> Walking the SSA definitions in order means that we consider the smallest >> algebraic optimizations before larger optimizations. So if a smaller

Re: [Mesa-dev] [PATCH 3/5] nir: Do opt_algebraic in reverse order.

On Mon, Feb 8, 2016 at 9:52 AM, Jason Ekstrand wrote: > Good enough for me. Please add that to the commit message. R-B Thanks, will do. Do you plan to review any of the others in the series? ___ mesa-dev mailing list

Re: [Mesa-dev] [PATCH 1/2] draw: use util_pstipple_create_fragment_shader

Thanks for this this. Series looks good to me. Reviewed-by: Jose Fonseca Sorry for not replying sooner -- I missed it. (Unfortunately I haven't been able to keep up with mesa-dev traffic and if I'm not CC'ed the odds are I miss things.) Jose On 08/02/16 14:59,

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

On Mon, Feb 8, 2016 at 1:55 PM, Rob Clark wrote: > On Mon, Feb 8, 2016 at 1:01 PM, Ilia Mirkin wrote: >> On Mon, Feb 8, 2016 at 8:59 AM, Rob Clark wrote: >>> On Mon, Feb 8, 2016 at 6:58 AM, Roland Scheidegger

Re: [Mesa-dev] [PATCH] mesa/extensions: Fix NVX_gpu_memory_info lexicographical order.

On Sat, Feb 06, 2016 at 01:20:30PM +0100, Kai Wasserbäch wrote: > Hey Vinson, > I would say the test is wrong. If I sort as a human, "NV_" comes before > "NVX_". > > And running this through sort (the tool), it agrees: > > $ echo -e "NVX_gpu_memory_info\nNV_blend_square" | sort -d >

Re: [Mesa-dev] [PATCH 5/5] nir: Recognize open-coded bitfield_reverse.

Quoting Jason Ekstrand (2016-02-08 12:04:15) [snip] > >I trust Dylan on patch 4.  I was just trying to ensure that we got/used a >32-bit value. >--Jason >  I mentioned to you offline, but I think it might be worth converting at least the opt algebraic passes to use numpy,

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

On Mon, Feb 8, 2016 at 5:16 PM, Matt Arsenault wrote: > > On Feb 8, 2016, at 08:08, Tom Stellard wrote: > > Do SI/CI support fp64 denorms? If so, won't this hurt performance? > > We should tell the compiler we are enabling fp-64 denorms by adding >

Re: [Mesa-dev] [PATCH 5/5] nir: Recognize open-coded bitfield_reverse.

On Thu, Feb 4, 2016 at 5:48 PM, Matt Turner wrote: > Helps 11 shaders in UnrealEngine4 demos. > > I seriously hope they would have given us bitfieldReverse() if we > exposed GL 4.0 (but we do expose ARB_gpu_shader5, so why not use that > anyway?). > > instructions in affected

Re: [Mesa-dev] [PATCH 2/5] nir: Recognize sum of open-coded pow()s.

On Mon, Feb 8, 2016 at 12:01 PM, Jason Ekstrand wrote: > On Thu, Feb 4, 2016 at 5:47 PM, Matt Turner wrote: >> >> Prevents regressions in the next commit. >> --- >> src/compiler/nir/nir_opt_algebraic.py | 1 + >> 1 file changed, 1 insertion(+) >> >>

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

On Mon, Feb 8, 2016 at 5:08 PM, Tom Stellard wrote: > On Sat, Feb 06, 2016 at 01:15:42PM +0100, Marek Olšák wrote: >> From: Marek Olšák >> >> This fixes FP16 conversion instructions for VI, which has 16-bit floats, >> but not SI & CI, which can't disable

[Mesa-dev] [Bug 94040] clGetPlatformIDs causes futex race condition

https://bugs.freedesktop.org/show_bug.cgi?id=94040 Francisco Jerez changed: What|Removed |Added CC|

[Mesa-dev] [PATCH] i965: Don't add barrier deps for FB write messages.

There are never render target reads, so there are no scheduling hazards. Giving the extra flexibility to the scheduler makes it possible to do FB writes as soon as their sources are available, reducing register pressure. It also makes it possible to do the payload setup for more than one FB

Re: [Mesa-dev] [PATCH] i965: Don't add barrier deps for FB write messages.

Reviewed-by: Connor Abbott FWIW, in this area, another place where we unnecessarily introduce dependencies between instructions is when multiple instructions write to different parts of a virtual register, for example when setting up message headers. Instead of tracking

[Mesa-dev] [Bug 94050] test_vec4_register_coalesce regression

https://bugs.freedesktop.org/show_bug.cgi?id=94050 Bug ID: 94050 Summary: test_vec4_register_coalesce regression Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Keywords:

[Mesa-dev] [Bug 94050] test_vec4_register_coalesce regression

https://bugs.freedesktop.org/show_bug.cgi?id=94050 --- Comment #1 from Ilia Mirkin --- >From a quick glance, this appears to be a test shortcoming, not an issue with the actual patch. It assumes that prog_data is there, which is true in real life, but I guess the test

Re: [Mesa-dev] [RFCv3 11/11] mesa/st: add support for NIR as possible driver IR

On Mon, Feb 8, 2016 at 2:00 PM, Ilia Mirkin wrote: > On Mon, Feb 8, 2016 at 1:55 PM, Rob Clark wrote: >> On Mon, Feb 8, 2016 at 1:01 PM, Ilia Mirkin wrote: >>> On Mon, Feb 8, 2016 at 8:59 AM, Rob Clark wrote:

Re: [Mesa-dev] [PATCH] i965: Don't add barrier deps for FB write messages.

On Mon, Feb 8, 2016 at 11:31 AM, Kenneth Graunke wrote: > There are never render target reads, so there are no scheduling hazards. > > Giving the extra flexibility to the scheduler makes it possible to do > FB writes as soon as their sources are available, reducing register

Re: [Mesa-dev] [PATCH 2/5] nir: Recognize sum of open-coded pow()s.

On Thu, Feb 4, 2016 at 5:47 PM, Matt Turner wrote: > Prevents regressions in the next commit. > --- > src/compiler/nir/nir_opt_algebraic.py | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/compiler/nir/nir_opt_algebraic.py >

Re: [Mesa-dev] [PATCH 1/6] nir: const_index helpers

On Mon, Feb 8, 2016 at 12:16 PM, Rob Clark wrote: > On Mon, Feb 8, 2016 at 3:13 PM, Jason Ekstrand > wrote: > >> + if (info->index_map[NIR_INTRINSIC_BASE] || > >> + info->index_map[NIR_INTRINSIC_WRMASK]) { > >> + fprintf(fp, " /*"); > >> +

Re: [Mesa-dev] [PATCH 2/5] nir: Recognize sum of open-coded pow()s.

On Mon, Feb 8, 2016 at 12:18 PM, Matt Turner wrote: > On Mon, Feb 8, 2016 at 12:01 PM, Jason Ekstrand > wrote: > > On Thu, Feb 4, 2016 at 5:47 PM, Matt Turner wrote: > >> > >> Prevents regressions in the next commit. > >> --- > >>

Re: [Mesa-dev] OpenGL ES context using EGL on framebuffer

Perhaps you'd be interested in having a look at kmscube: https://github.com/robclark/kmscube This is a simple demo which uses GBM and passes the resulting buffers to KMS for scanout. Make sure you build mesa with --enable-gbm and --enable-egl-platforms=drm [and x11 if you still want egl to work

Re: [Mesa-dev] [PATCH 4/5] nir: Handle large unsigned values in opt_algebraic.

On Thursday, February 4, 2016 5:48:00 PM PST Matt Turner wrote: > The next patch adds an algebraic rule that uses the constant 0xff00ff00. > > Without this change, the build fails with > >return hex(struct.unpack('I', struct.pack('i', self.value))[0]) >struct.error: 'i' format requires

[Mesa-dev] OpenGL ES context using EGL on framebuffer

Is there a way to create an OpenGL ES context using EGL on a Intel Atom E3845 without XServer? For an embedded board running a Linux (based on Yocto

[Mesa-dev] [PATCH 4/4] mesa/readpix: Dedent former _mesa_readpixels() if block

From: Nanley Chery Formatting patch split out for easy reviewing. Signed-off-by: Nanley Chery --- src/mesa/main/readpix.c | 58 - 1 file changed, 29 insertions(+), 29 deletions(-) diff --git

[Mesa-dev] [PATCH 2/4] mesa/readpix: Clip ReadPixels() area to the ReadBuffer's

From: Nanley Chery The fast path for Intel's ReadPixels() unintentionally omits clipping the specified area to a valid one. Rather than clip in various corner-cases, perform this operation in the API validation stage. The bug in intel_readpixels_tiled_memcpy() showed

[Mesa-dev] [PATCH 3/4] mesa/readpix: Don't clip in _mesa_readpixels()

From: Nanley Chery The clipping is performed higher up in the call-chain. Signed-off-by: Nanley Chery --- src/mesa/main/readpix.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git

[Mesa-dev] [PATCH 1/4] mesa/image: Make _mesa_clip_readpixels() work with renderbuffers

From: Nanley Chery v2: Use gl_renderbuffer::{Width,Height} (Jason) Cc: "11.0 11.1" Signed-off-by: Nanley Chery --- src/mesa/main/image.c | 22 +- 1 file changed, 17 insertions(+), 5

[Mesa-dev] [PATCH] mesa: add missing error check in _mesa_CallLists()

Generate GL_INVALID_VALUE if n < 0. Return early if n==0. --- src/mesa/main/dlist.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c index cd8e3b6..24aea35 100644 --- a/src/mesa/main/dlist.c +++ b/src/mesa/main/dlist.c @@ -9105,6 +9105,15

Re: [Mesa-dev] [PATCH] mesa: add missing error check in _mesa_CallLists()

On 02/08/2016 02:31 PM, Brian Paul wrote: > Generate GL_INVALID_VALUE if n < 0. Return early if n==0. > --- > src/mesa/main/dlist.c | 9 + > 1 file changed, 9 insertions(+) > > diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c > index cd8e3b6..24aea35 100644 > ---

Re: [Mesa-dev] [PATCH] radeonsi: enable denorms for 64-bit and 16-bit floats

Am 09.02.2016 um 00:53 schrieb Ian Romanick: > On 02/08/2016 03:37 PM, Roland Scheidegger wrote: >> Am 09.02.2016 um 00:02 schrieb Ian Romanick: >>> On 02/08/2016 12:38 PM, Marek Olšák wrote: On Mon, Feb 8, 2016 at 5:08 PM, Tom Stellard wrote: > On Sat, Feb 06, 2016 at

Re: [Mesa-dev] [PATCH 3/5] nir: Do opt_algebraic in reverse order.

On Mon, Feb 8, 2016 at 3:57 PM, Ian Romanick wrote: > On 02/04/2016 05:47 PM, Matt Turner wrote: >> Walking the SSA definitions in order means that we consider the smallest >> algebraic optimizations before larger optimizations. So if a smaller >> rule is part of a larger

Re: [Mesa-dev] [PATCH 4/5] nir: Handle large unsigned values in opt_algebraic.

On Monday, February 8, 2016 4:01:37 PM PST Ian Romanick wrote: > On 02/08/2016 01:59 PM, Kenneth Graunke wrote: > > On Thursday, February 4, 2016 5:48:00 PM PST Matt Turner wrote: > >> The next patch adds an algebraic rule that uses the constant 0xff00ff00. > >> > >> Without this change, the build

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