Re: [Mesa-dev] Call i965 GLSL IR backend optimisation from the common linker

On Tue, Jul 26, 2016 at 10:20 PM, Timothy Arceri wrote: > The ultimate goal is to be able to convert to NIR and make use of its > optimisations before assigning varying and uniform locations. This > should allow us to start removing some of the GLSL IR optimisation >

Re: [Mesa-dev] [PATCH 00/11] Make more use of state already tracked in the VAO.

Hi, This should have been some preparing cleanup for some patches doing less work in the fast draw path. I have updated the comment as requested and now resent with the new comment. And I believe that _mesa_all_varyings_in_vbos is equivalent to vbo_all_varyings_in_vbos but working on a VAO. Else

Re: [Mesa-dev] [PATCH 03/11] mesa: Implement _mesa_all_varyings_in_vbos.

Hi, On Thursday, June 23, 2016 16:53:59 Fredrik Höglund wrote: > On Friday 17 June 2016, mathias.froehl...@gmx.net wrote: > > From: Mathias Fröhlich > > > > Implement the equivalent of vbo_all_varyings_in_vbos for > > vertex array objects. > > > > Signed-off-by:

Re: [Mesa-dev] [PATCH v2 15/35] i965/blorp: Add an isl_view to blorp_surface_info

On Tue, Jul 26, 2016 at 03:02:06PM -0700, Jason Ekstrand wrote: > Eventually, this will be the actual view that gets passed into isl to > create the surface state. For now, we just use it for the format and the > swizzle. > --- > src/mesa/drivers/dri/i965/brw_blorp.c | 38 >

Re: [Mesa-dev] [PATCH v2 15/35] i965/blorp: Add an isl_view to blorp_surface_info

On Tue, Jul 26, 2016 at 03:02:06PM -0700, Jason Ekstrand wrote: > Eventually, this will be the actual view that gets passed into isl to > create the surface state. For now, we just use it for the format and the > swizzle. > --- > src/mesa/drivers/dri/i965/brw_blorp.c | 38 >

[Mesa-dev] [PATCH 03/11] mesa: Implement _mesa_all_varyings_in_vbos.

From: Mathias Fröhlich Implement the equivalent of vbo_all_varyings_in_vbos for vertex array objects. v2: Update comment. Signed-off-by: Mathias Fröhlich --- src/mesa/main/arrayobj.c | 35 +++

[Mesa-dev] [PATCH 13/13] glsl: free hash tables earlier

These are only used by get_matching_input() which has been call at this point so free the hash tables. --- src/compiler/glsl/link_varyings.cpp | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/compiler/glsl/link_varyings.cpp b/src/compiler/glsl/link_varyings.cpp

[Mesa-dev] [PATCH 07/13] glsl: disable dead code removal of lowered ubos

This lets us assign uniform storage for packed UBOs after they have been lowered otherwise the var is removed too early. --- src/compiler/glsl/glsl_parser_extras.cpp | 5 +++-- src/compiler/glsl/ir_optimization.h| 4 +++- src/compiler/glsl/link_varyings.cpp| 2 +-

[Mesa-dev] [PATCH 11/13] mesa/i965: create Driver.ProcessGLSLIR()

This allows us to do backend specific processing on GLSL IR from the shared linker. --- src/mesa/drivers/dri/i965/brw_link.cpp | 12 ++-- src/mesa/drivers/dri/i965/brw_program.c | 1 + src/mesa/drivers/dri/i965/brw_shader.h | 4 src/mesa/main/dd.h | 3 +++ 4

[Mesa-dev] [PATCH 10/13] i965: move common optimisation loop to a helper

--- src/mesa/drivers/dri/i965/brw_link.cpp | 50 -- 1 file changed, 30 insertions(+), 20 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index efd67e7..e56df93 100644 ---

[Mesa-dev] [PATCH 04/13] glsl: remove remaining tabs in link_uniform_initializers.cpp

--- src/compiler/glsl/link_uniform_initializers.cpp | 78 - 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/src/compiler/glsl/link_uniform_initializers.cpp b/src/compiler/glsl/link_uniform_initializers.cpp index 3750021..021e950 100644 ---

Re: [Mesa-dev] [PATCH v2 13/35] i965/blorp: Refactor interleaved multisample destination handling

On Tue, Jul 26, 2016 at 03:02:04PM -0700, Jason Ekstrand wrote: > We put all of the code for fake IMS together. This requires moving a bit > of the program key setup code further down so that it gets the right values > out of the final surface. > > Reviewed-by: Topi Pohjolainen

[Mesa-dev] [PATCH 05/13] glsl: move uniform linking code to new link_setup_uniform_remap_tables()

This makes link_assign_uniform_locations() easier to follow. --- src/compiler/glsl/link_uniforms.cpp | 330 +++- src/compiler/glsl/linker.cpp| 4 +- src/compiler/glsl/linker.h | 5 +- 3 files changed, 177 insertions(+), 162 deletions(-) diff

[Mesa-dev] [PATCH 02/13] glsl: remove dead builtins before assigning varying locations

Builtins already have locations assigned so this shouldn't changing anything. We want to call it earlier so we can tranform GLSL IR to NIR earlier. --- src/compiler/glsl/linker.cpp | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/compiler/glsl/linker.cpp

[Mesa-dev] [PATCH 09/13] i965: stop passing stage as a function parameter

We already pass the shader so we can just get the stage from this. --- src/mesa/drivers/dri/i965/brw_link.cpp | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 3b85f79..efd67e7 100644

[Mesa-dev] [PATCH 03/13] glsl: use UniformHash to find storage location

There is no need to be looping over all the uniforms. --- src/compiler/glsl/link_uniform_initializers.cpp | 29 ++--- 1 file changed, 11 insertions(+), 18 deletions(-) diff --git a/src/compiler/glsl/link_uniform_initializers.cpp

[Mesa-dev] [PATCH 08/13] glsl: move update_uniform_buffer_variables() to lower UBO

This make more sense here as its lowering that uses the results of this function. This allows us to call lower_ubo_reference() before assigning uniform locations which is useful for calling backend specific optimisations on the IR before assigning uniform and varying locations. While we are at

[Mesa-dev] [PATCH 01/13] glsl: split out varying and uniform linking code

Here a new function link_varyings_and_uniforms() is created this should help make it easier to follow the code in link_shader() which was getting very large. Note the end of the new function contains a for loop with some lowering calls that currently don't seem related to varyings or uniforms but

[Mesa-dev] [PATCH 12/13] glsl/i965: call backend optimisations from glsl linker

Here we get the backend to do its extra GLSL IR passes before assigning varying and uniform locations. We move the lower_variable_index_to_cond_assign() call to brw_link_shader() as this must be called after we have done varying packing to avoid regressions. Broadwell shader-db results: total

[Mesa-dev] [PATCH 06/13] glsl: move uniform linking code to link_assign_uniform_storage()

This makes link_assign_uniform_locations() easier to follow. --- src/compiler/glsl/link_uniforms.cpp | 132 +++- 1 file changed, 69 insertions(+), 63 deletions(-) diff --git a/src/compiler/glsl/link_uniforms.cpp b/src/compiler/glsl/link_uniforms.cpp index

[Mesa-dev] Call i965 GLSL IR backend optimisation from the common linker

The ultimate goal is to be able to convert to NIR and make use of its optimisations before assigning varying and uniform locations. This should allow us to start removing some of the GLSL IR optimisation passes. This series falls short of making use of NIR because lower_packed_varyings() modifies

Re: [Mesa-dev] [PATCH 1/5] i965/surface_formats: Don't advertise 8 or 16-bit RGB formats

On Wed, Jul 27, 2016 at 1:04 AM, Jason Ekstrand wrote: > We have implicitly been not advertising these formats since we had them > turned off in the format capabilities table. We are about to update that > table and this prevents a change in behavior. The only change in

[Mesa-dev] [PATCH 4/5] anv/image: Don't create invalid render target surfaces

--- src/intel/vulkan/anv_image.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index dff51bc..ce08979 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -531,7 +531,18 @@

[Mesa-dev] [PATCH 5/5] isl/state: Add some asserts about format capabilities

This keeps invalid surface states from leaking through and potentially hanging the GPU. We shouldn't actually be hitting this on a regular basis, but a helpful assert is better than a hang. --- src/intel/isl/isl_surface_state.c | 5 + 1 file changed, 5 insertions(+) diff --git

[Mesa-dev] [PATCH 3/5] isl/formats: Update the table with more samplable formats

There were a lot of formats where support was added on Haswell or later but we never updated the format table. --- src/intel/isl/isl_format.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/intel/isl/isl_format.c

[Mesa-dev] [PATCH 0/5] isl: Update the format table and add asserts

The real objective of this series is patch 5 which prevents us from accidentally creating a surface state with a format unsupported by the hardware. This turns some of the new Vulkan CTS tests from a hang into an informative crash. In order to get there, however, we needed to update the format

[Mesa-dev] [PATCH 2/5] isl/formats: Report ETC as being samplable on Bay Trail

--- src/intel/isl/isl_format.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c index e0b91bb..366d32e 100644 --- a/src/intel/isl/isl_format.c +++ b/src/intel/isl/isl_format.c @@ -372,6 +372,15 @@

[Mesa-dev] [PATCH 1/5] i965/surface_formats: Don't advertise 8 or 16-bit RGB formats

We have implicitly been not advertising these formats since we had them turned off in the format capabilities table. We are about to update that table and this prevents a change in behavior. The only change in behavior created by this patch is that we no longer advertise support for

Re: [Mesa-dev] [PATCH v2 11/35] i965/blorp: Use isl_msaa_layout instead of intel_msaa_layout

On Tue, Jul 26, 2016 at 03:02:02PM -0700, Jason Ekstrand wrote: > We also remove brw_blorp_surface_info::msaa_layout. > --- > src/mesa/drivers/dri/i965/brw_blorp.c| 18 - > src/mesa/drivers/dri/i965/brw_blorp.h| 14 +--- > src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 111

Re: [Mesa-dev] [PATCH v2 08/35] i965/blorp: Make sample count asserts a bit more lazy

We could have a small rational here: Until now blorp used internally the sample count of zero to represent single sampled surfaces. However, incoming single sampled surfaces may have the sample count set as zero or one, and once the stomping to zero is dropped these asserts would fire. On Tue,

[Mesa-dev] [Bug 96950] Another regression from bc4e0c486: vbo: Use a bitmask to track the active arrays in vbo_exec*.

https://bugs.freedesktop.org/show_bug.cgi?id=96950 --- Comment #9 from Mathias Fröhlich --- I have verified 0ad with the provided trace here, updated as requested and pushed. Thanks for testing and review on your side. I assume the originator verifies and closes the

Re: [Mesa-dev] Interest in GL_ARB_gl_spirv support?

On Tue, Jul 26, 2016 at 9:16 PM, Jason Ekstrand wrote: > On Tue, Jul 26, 2016 at 4:50 PM, Ilia Mirkin wrote: >> >> On Tue, Jul 26, 2016 at 7:44 PM, Marek Olšák wrote: >> > On Wed, Jul 27, 2016 at 12:29 AM, oscar bg

Re: [Mesa-dev] Interest in GL_ARB_gl_spirv support?

On Tue, Jul 26, 2016 at 4:50 PM, Ilia Mirkin wrote: > On Tue, Jul 26, 2016 at 7:44 PM, Marek Olšák wrote: > > On Wed, Jul 27, 2016 at 12:29 AM, oscar bg wrote: > >> Hi, > >> seems this year 2016 OpenGL ARB update brings a small number

Re: [Mesa-dev] [PATCH] anv/pipeline: Enable only one dispatch width in case of per sample shading

On Jul 26, 2016 12:54 PM, "Anuj Phogat" wrote: > > Fixes ~45 DEQP sample shading tests: > ./deqp-vk --deqp-case=dEQP-VK.pipeline.multisample.min_sample_shading* > > Many tests exited with VK_ERROR_OUT_OF_DEVICE_MEMORY without this patch. > > Cc: Jason Ekstrand

Re: [Mesa-dev] [PATCH v2 26/27] i965/blorp: brw_blorp_blit.cpp -> blorp_blit.c

On Jul 26, 2016 6:49 PM, "Matt Turner" wrote: > > On Tue, Jul 26, 2016 at 3:11 PM, Jason Ekstrand wrote: > > --- > > src/mesa/drivers/dri/i965/Makefile.sources |2 +- > > src/mesa/drivers/dri/i965/blorp_blit.c | 1662

Re: [Mesa-dev] [PATCH v2 26/27] i965/blorp: brw_blorp_blit.cpp -> blorp_blit.c

On Tue, Jul 26, 2016 at 3:11 PM, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/Makefile.sources |2 +- > src/mesa/drivers/dri/i965/blorp_blit.c | 1662 > ++ > src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 1662 >

Re: [Mesa-dev] [PATCH] st_glsl_to_tgsi: only skip over slots of an input array that are present

Reviewed-by: Marek Olšák Marek On Mon, Jul 25, 2016 at 6:08 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > When an application declares varying arrays but does not actually do any > indirect indexing, some array indices

[Mesa-dev] [PATCH] glsl: free hash tables earlier

These are only used by get_matching_input() which has been call at this point so free the hash tables. --- src/compiler/glsl/link_varyings.cpp | 10 +++--- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/compiler/glsl/link_varyings.cpp b/src/compiler/glsl/link_varyings.cpp

Re: [Mesa-dev] Interest in GL_ARB_gl_spirv support?

On Tue, Jul 26, 2016 at 7:44 PM, Marek Olšák wrote: > On Wed, Jul 27, 2016 at 12:29 AM, oscar bg wrote: >> Hi, >> seems this year 2016 OpenGL ARB update brings a small number of extensions.. >> seems the most important is GL_ARB_gl_spirv.. seems like SPIRV as

Re: [Mesa-dev] Mesa (master): Revert "radeon/llvm: Use alloca instructions for larger arrays"

> On Jul 26, 2016, at 14:37, Marek Olšák wrote: > > On Sat, Jul 23, 2016 at 4:07 PM, Nicolai Hähnle > wrote: >> On 22.07.2016 12:08, Michel Dänzer wrote: >>> >>> On 21.07.2016 18:17, Matt Arsenault wrote: > > On Jul

Re: [Mesa-dev] Interest in GL_ARB_gl_spirv support?

On Wed, Jul 27, 2016 at 12:29 AM, oscar bg wrote: > Hi, > seems this year 2016 OpenGL ARB update brings a small number of extensions.. > seems the most important is GL_ARB_gl_spirv.. seems like SPIRV as a binary > format for OpenGL and Mesa doesn't have any binary format even

Re: [Mesa-dev] [PATCH 1/3] nvc0: fix up TCP header on GM107+

On Tue, Jul 26, 2016 at 6:53 PM, Samuel Pitoiset wrote: > The number of outputs patch (limited to 255) has moved in the TCP > header, but blob seems to also set the old position. Also, the high > 8-bits are now located inbetween the min/max parallel output read >

Re: [Mesa-dev] [PATCH 2/3] gm107/ir: add a legalize SSA pass for PFETCH

On Tue, Jul 26, 2016 at 6:53 PM, Samuel Pitoiset wrote: > PFETCH, actually ISBERD on GM107+ ISA only accepts a GPR for src0. > > Signed-off-by: Samuel Pitoiset > --- > .../nouveau/codegen/nv50_ir_lowering_gm107.cpp | 33 >

Re: [Mesa-dev] Mesa (master): gallium/radeon: degrade tiled textures mapped often to linear

On Tue, Jun 7, 2016 at 11:02 AM, Marek Olšák wrote: > On Tue, Jun 7, 2016 at 9:14 AM, Michel Dänzer wrote: >> On 02.06.2016 21:20, Michel Dänzer wrote: >>> On 02.06.2016 00:35, Marek =?UNKNOWN?B?T2zFocOhaw==?= wrote: Module: Mesa Branch: master

[Mesa-dev] [PATCH 0/3] nvc0: add support for tessellation on Maxwell+

Hi, This series adds support for GL_ARB_tessellation_shader on GM107+ *and* exposes GL 4.1! :) This has been tested on GM107 and GM206 (this also enables tess on Pascal, but I can't test, hopefully it will not break the universe) Actually, it seems like we can re-use most of the existing code

[Mesa-dev] [PATCH 3/3] nvc0: enable ARB_tessellation_shader on GM107+

This exposes OpenGL 4.1 on Maxwell (tested on GM107 and GM206). Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

[Mesa-dev] [PATCH 1/3] nvc0: fix up TCP header on GM107+

The number of outputs patch (limited to 255) has moved in the TCP header, but blob seems to also set the old position. Also, the high 8-bits are now located inbetween the min/max parallel output read address at position 20. Signed-off-by: Samuel Pitoiset ---

[Mesa-dev] [PATCH 2/3] gm107/ir: add a legalize SSA pass for PFETCH

PFETCH, actually ISBERD on GM107+ ISA only accepts a GPR for src0. Signed-off-by: Samuel Pitoiset --- .../nouveau/codegen/nv50_ir_lowering_gm107.cpp | 33 ++ .../nouveau/codegen/nv50_ir_lowering_gm107.h | 11

Re: [Mesa-dev] [RFC] i965: Delete brw_do_channel_expressions().

I re-ran these numbers with my SSO patches for shader-db and my move_interpolation_to_top() pass fixed. They're pretty similar: (didn't run Haswell) On Broadwell: total instructions in shared programs: 11632138 -> 11641224 (0.08%) instructions in affected programs: 1525250 -> 1534336 (0.60%)

[Mesa-dev] [PATCH shader-db v2 2/2] run: Mark shaders with only one stage as separable.

There are a couple cases where a single shader might happen: - compute shaders (only one stage, no inputs and outputs; separable shouldn't matter) - vertex shaders with transform feedback (we want to retain outputs, but transform feedback varyings are specified via the API, not the shader

[Mesa-dev] [PATCH shader-db v2 1/2] run: Add separate shader objects support.

With this patch, if a .shader_test file contains [require] ... SSO ENABLED then we'll use glCreateShaderProgramv to create each shader, so that they're compiled as separate shader objects. This prevents the linker from removing unused inputs and outputs. Drivers may also choose to

[Mesa-dev] Interest in GL_ARB_gl_spirv support?

Hi, seems this year 2016 OpenGL ARB update brings a small number of extensions.. seems the most important is GL_ARB_gl_spirv.. seems like SPIRV as a binary format for OpenGL and Mesa doesn't have any binary format even supporting ARB_program_binary ext.. a Nvidia driver is already providing

[Mesa-dev] [PATCH v2 01/35] isl: Fix the parameter names for get_intratile_offset

It's been in elements for a while but, for whatever reason, the parameter names in the header file never got updated. --- src/intel/isl/isl.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 19673f8..d0bac5d 100644 ---

[Mesa-dev] [PATCH v2 14/35] i965/blorp: Move intratile offset calculations out of surface state setup

Previously we multiplied full x/y offsets, resolved tile aligned buffer offset and intra tile offset based on that. Now we let ISL to take into account the msaa setting and we only multiply the resolved intra tile offsets. Reviewed-by: Topi Pohjolainen ---

[Mesa-dev] [PATCH v2 07/35] i965/blorp: Get rid of brw_blorp_surface_info::map_stencil_as_y_tiled

Now that we're carrying around the isl_surf, we can just modify it directly instead of passing an extra bit around. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c| 12 ++--- src/mesa/drivers/dri/i965/brw_blorp.h| 15

[Mesa-dev] [PATCH v2 23/35] isl: Take the slice0_extent shortcut for interleaved MSAA

The shortcut works just fine for MSAA and the comment even says so. Reviewed-by: Nanley Chery --- src/intel/isl/isl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index a9208f6..500eb2d 100644 ---

[Mesa-dev] [PATCH v2 21/35] i965/blorp: Use the isl_view from the blorp_surface_info

--- src/mesa/drivers/dri/i965/brw_blorp.c | 18 +- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 78707ca..d9b5554 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++

[Mesa-dev] [PATCH v2 08/35] i965/blorp: Make sample count asserts a bit more lazy

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index

[Mesa-dev] [PATCH v2 25/35] i965/blorp: Map 1-D render targets with DIM_LAYOUT_GEN4_2D as 2D on gen9

The sampling hardware can handle them ok. It just looks at the tiling to determine whether it's the new gen9 1-D layout or the old one. The render hardware isn't so smart. --- src/mesa/drivers/dri/i965/brw_blorp.c | 6 ++ 1 file changed, 6 insertions(+) diff --git

[Mesa-dev] [PATCH v2 17/35] isl: Add functions for computing surface offsets in samples

--- src/intel/isl/isl.c | 24 src/intel/isl/isl.h | 48 2 files changed, 60 insertions(+), 12 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index a713eeb..f65f9c8 100644 --- a/src/intel/isl/isl.c +++

[Mesa-dev] [PATCH v2 28/35] i965/blorp: Add a z_offset field to blorp_surface_info

The layer field is in terms of physical layers which isn't quite what the sampler will want for 2-D MS array textures. --- src/mesa/drivers/dri/i965/brw_blorp.c| 9 + src/mesa/drivers/dri/i965/brw_blorp.h| 3 +++ src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 11

[Mesa-dev] [PATCH v2 35/35] isl/state: Add an assertion for IVB multisample array textures

--- src/intel/isl/isl_surface_state.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index fb23414..990b763 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -239,6

Re: [Mesa-dev] [PATCH] glsl: fix optimization of discard nested multiple levels

On Tuesday, July 26, 2016 10:14:12 AM PDT Nicolai Hähnle wrote: > From: Nicolai Hähnle > > The order of optimizations can lead to the conditional discard optimization > being applied twice to the same discard statement. In this case, we must > ensure that both conditions

[Mesa-dev] [PATCH v2 13/35] i965/blorp: Refactor interleaved multisample destination handling

We put all of the code for fake IMS together. This requires moving a bit of the program key setup code further down so that it gets the right values out of the final surface. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 71

[Mesa-dev] [PATCH v2 22/35] isl: Remove duplicate px->sa conversions

In all three cases, we start with width and height taken from isl_surf::phys_slice0_extent_sa which is already in samples. There is no need to do the conversion and doing so gives us an incorrect value. Reviewed-by: Nanley Chery --- src/intel/isl/isl.c | 20

[Mesa-dev] [PATCH v2 15/35] i965/blorp: Add an isl_view to blorp_surface_info

Eventually, this will be the actual view that gets passed into isl to create the surface state. For now, we just use it for the format and the swizzle. --- src/mesa/drivers/dri/i965/brw_blorp.c | 38 +++ src/mesa/drivers/dri/i965/brw_blorp.h | 16

[Mesa-dev] [PATCH v2 16/35] isl: Fix get_image_offset_sa_gen4_2d for multisample surfaces

The function takes a logical array layer but was assuming it was a physical array layer. While we'er here, we also make it not assert-fail on gen9 3-D surfaces. --- src/intel/isl/isl.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/intel/isl/isl.c

[Mesa-dev] [PATCH v2 04/35] i965/blorp/clear: Initialize surface info after allocating an MCS

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp index

[Mesa-dev] [PATCH v2 34/35] isl: Add a #define for DEV_IS_BAYTRAIL

--- src/intel/isl/isl.h | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 68ad8a4..b8b48f0 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -79,6 +79,10 @@ struct brw_image_param; #define ISL_DEV_IS_HASWELL(__dev)

[Mesa-dev] [PATCH v2 20/35] i965/blorp: Get rid of brw_blorp_surface_info::width/height

Instead, we manually mutate the surface size as needed. --- src/mesa/drivers/dri/i965/brw_blorp.c| 21 ++--- src/mesa/drivers/dri/i965/brw_blorp.h| 12 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 19 +++

[Mesa-dev] [PATCH v2 12/35] i965/blorp: Get rid of brw_blorp_surface_info::array_layout

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 1 - src/mesa/drivers/dri/i965/brw_blorp.h | 9 - 2 files changed, 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index

[Mesa-dev] [PATCH v2 03/35] isl/state: Use a valid alignment for 1-D textures

The alignment we use doesn't matter (see the comment) but it should at least be an alignment we can represent with the enums. Reviewed-by: Topi Pohjolainen --- src/intel/isl/isl_surface_state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH v2 05/35] i965/blorp: Create the isl_surf up-front

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 25 ++--- src/mesa/drivers/dri/i965/brw_blorp.h | 5 + 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c

[Mesa-dev] [PATCH v2 00/35] i965: Rework blorp to use ISL internally

This series is mostly just a resend of an earlier series that makes blorp use ISL internally. The original series can be found here: https://lists.freedesktop.org/archives/mesa-dev/2016-June/121891.html The patches haven't really changed but they've been rebased and a few new patches squashed

[Mesa-dev] [PATCH v2 02/35] i965/miptree: Remove the stencil_as_y_tiled parameter from get_tile_masks

It's only used to stomp the tiling to Y and it's only used by blorp so there's no reason why blorp can't do it itself. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 6 -- src/mesa/drivers/dri/i965/brw_misc_state.c| 6 +++---

[Mesa-dev] [PATCH v2 27/35] i965/blorp: Pass the Z component into all texture operations

Multisample array surfaces on IVB don't support the minimum array element surface attribute so it needs to come through the sampler message. We may as well just pass it through everything. --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 77 +--- 1 file changed, 35

[Mesa-dev] [PATCH v2 10/35] i965/blorp: Use the ISL aux_layout for deciding whether to do an MCS fetch

Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 2 ++ src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 16 +--- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h

[Mesa-dev] [PATCH v2 23/27] i965/blorp: Break the guts of do_single_blorp_clear into two helpers

The helpers are completely miptree-unaware and each fairly cleanly do a single thing. This does come at the downside of not doing proper debug reporting on whether or not we're doing replicated clears. --- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 175 -- 1 file

[Mesa-dev] [PATCH v2 06/35] i965/blorp: Remove compute_tile_offsets

We have a handy little function is ISL that does exactly the same thing. Reviewed-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 34 +- src/mesa/drivers/dri/i965/brw_blorp.h | 5 - 2 files changed, 5

[Mesa-dev] [PATCH v2 26/35] i965/blorp: Rework hiz rect alignment calculations

At the moment, the minify operation does nothing because params.depth.view.base_level is always zero. However, as soon as we start using actual base miplevels and array slices, we are going to need the minification. Also, we only need to align the surface dimensions in the case where we are

[Mesa-dev] [PATCH v2 18/35] i965/blorp: Use ISL to compute image offsets

For the moment, we still call the old miptree function; we just assert that the two are equal. --- src/mesa/drivers/dri/i965/brw_blorp.c | 94 +-- 1 file changed, 91 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c

[Mesa-dev] [PATCH v2 20/27] i965/blorp: Refactor fast-clear logic a bit

This pulls the mcs allocation into the if statement where we initially determine that we are doing a fast clear and moves the programming of wm_inputs and figuring out the fast clear rect into it's own if statement. The next commit will put code inbetween the two. ---

[Mesa-dev] [PATCH v2 17/27] i965/blorp: Stop calling brw_meta_get_buffer_rect

We already have an inlined version of the function slightly higher up in do_single_blorp_clear and all calling it does is stomp the values with the same thing. We might as well just get rid of it. --- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 3 ---

[Mesa-dev] [PATCH v2 22/27] i965/meta_util: Convert get_fast_clear_rect to take an isl_surf

--- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +- src/mesa/drivers/dri/i965/brw_meta_util.c | 27 +++ src/mesa/drivers/dri/i965/brw_meta_util.h | 2 +- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git

[Mesa-dev] [PATCH v2 16/27] i965/blorp: Pull the guts of resolve_color into a miptree-agnostic helper

--- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 43 --- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp index d242f24..d574eac 100644 ---

[Mesa-dev] [PATCH v2 24/27] i965/blorp: Factor the guts of blorp_hiz_exec into a helper

--- src/mesa/drivers/dri/i965/brw_blorp.c | 43 --- 1 file changed, 25 insertions(+), 18 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 64bbf4c..c862dfd 100644 ---

[Mesa-dev] [PATCH v2 27/27] i965/blorp: brw_blorp_clear.cpp -> blorp_clear.c

--- src/mesa/drivers/dri/i965/Makefile.sources| 2 +- src/mesa/drivers/dri/i965/blorp_clear.c | 190 + src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 194 -- 3 files changed, 191 insertions(+), 195 deletions(-) create mode 100644

[Mesa-dev] [PATCH v2 11/27] i965/blorp: Do gen6 stencil offsets up-front

This keeps all of the nastyness of gen6 stencil on the i965 side of the API line and lets us delete that nasty hand-rolled ISL-based offset path that we were using for ALL_SLICES_AT_EACH_LOD. --- src/mesa/drivers/dri/i965/brw_blorp.c| 108 ---

[Mesa-dev] [PATCH v2 18/27] i965/meta_util: Only modify the input parameters in get_fast_clear_rect

We had another inline copy of brw_meta_get_buffer_rect embedded in get_fast_clear_rect for no good reason. This lets us get rid of the gl_frameuffer parameter to get_fast_clear_rect. --- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 2 +- src/mesa/drivers/dri/i965/brw_meta_util.c | 14

[Mesa-dev] [PATCH v2 13/27] i965/blorp: Add a new brw_blorp_surf intermediate struct

At the moment, this seems to make all of the interfaces messier rather than clener. However, it does provide a representation of a surface that simultaneously contains everything and is completely unaware of miptrees. --- src/mesa/drivers/dri/i965/brw_blorp.c | 205

[Mesa-dev] [PATCH v2 21/27] i965/blorp/clear: Move isl_surf setup higher in the function

--- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 20 ++-- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp index a66e955..cb288de 100644 ---

[Mesa-dev] [PATCH v2 08/27] i965/blorp: Stop using the miptree in state setup for tex/rt surfaces

Instead, we add a bo and offset field to brw_blorp_surface_info and use those in the backend. --- src/mesa/drivers/dri/i965/brw_blorp.c| 10 +--- src/mesa/drivers/dri/i965/brw_blorp.h| 3 ++- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 +++-

[Mesa-dev] [PATCH v2 15/27] i965/meta_util: Convert get_resolve_rect to use ISL

--- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 5 ++-- src/mesa/drivers/dri/i965/brw_meta_util.c | 43 +-- src/mesa/drivers/dri/i965/brw_meta_util.h | 8 ++--- 3 files changed, 28 insertions(+), 28 deletions(-) diff --git

[Mesa-dev] [PATCH v2 12/27] i965/blorp: Use the isl_surf for more params setup

The isl_surf munging doesn't happen until fairly late in the blorp_blit function. We can use the isl_surf for the vast majority if not all of our params setup. --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 79 1 file changed, 21 insertions(+), 58 deletions(-)

[Mesa-dev] [PATCH v2 07/27] i965/blorp/blit: Move format work-arounds before surface_info_init

--- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 30 +--- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 007c061..ed68734 100644 ---

[Mesa-dev] [PATCH v2 19/27] i965/blorp/clear: Stop stomping the destination format

The blorp_surface_info_init call above should ste the format for us and stomping it later does nothing whatsoever. --- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp

[Mesa-dev] [PATCH v2 10/27] i965/blorp: Set up HiZ surfaces up-front

--- src/mesa/drivers/dri/i965/brw_blorp.c | 59 +- src/mesa/drivers/dri/i965/brw_blorp.h | 2 -- src/mesa/drivers/dri/i965/gen6_blorp.c | 19 +++ src/mesa/drivers/dri/i965/gen7_blorp.c | 10 +++--- 4 files changed, 59 insertions(+), 31 deletions(-) diff

[Mesa-dev] [PATCH v2 09/27] i964/blorp: Set up most aux surfaces up-front

--- src/mesa/drivers/dri/i965/brw_blorp.c | 43 --- src/mesa/drivers/dri/i965/brw_blorp.h | 4 2 files changed, 29 insertions(+), 18 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index

[Mesa-dev] [PATCH v2 14/27] i965/blorp: Make the guts of brw_blorp_blit_miptrees miptree-unaware

Now that we have the brw_blorp_surf struct, we can start to make bits of blorp completely miptree-unaware. To start things off, we split the guts of brw_blorp_blit_miptrees into a brw_blorp_blit function which knows nothing about miptrees. --- src/mesa/drivers/dri/i965/brw_blorp.h| 14

[Mesa-dev] [PATCH v2 01/27] i965/miptree: Support depth in get_isl_clear_color

--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index ba06ac9..8c63aa6 100644 ---

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