Re: [Mesa-dev] [PATCH 13/18] anv/pipeline: Compile to NIR in compile_graphics

[Jason Ekstrand]

On Wed, Jul 25, 2018 at 5:19 PM Timothy Arceri 
wrote:

> On 12/07/18 07:18, Jason Ekstrand wrote:
> > This pulls the SPIR-V to NIR step out into common code.
> > ---
> >   src/intel/vulkan/anv_pipeline.c | 278 +---
> >   1 file changed, 116 insertions(+), 162 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_pipeline.c
> b/src/intel/vulkan/anv_pipeline.c
> > index bc268b87e55..50d6ab358d2 100644
> > --- a/src/intel/vulkan/anv_pipeline.c
> > +++ b/src/intel/vulkan/anv_pipeline.c
> > @@ -404,6 +404,14 @@ struct anv_pipeline_stage {
> > gl_shader_stage stage;
> > unsigned char sha1[20];
> >  } cache_key;
> > +
> > +   nir_shader *nir;
> > +
> > +   struct anv_pipeline_binding surface_to_descriptor[256];
> > +   struct anv_pipeline_binding sampler_to_descriptor[256];
> > +   struct anv_pipeline_bind_map bind_map;
> > +
> > +   union brw_any_prog_data prog_data;
> >   };
> >
> >   static void
> > @@ -547,58 +555,40 @@ anv_fill_binding_table(struct brw_stage_prog_data
> *prog_data, unsigned bias)
> >   static VkResult
> >   anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
> >   struct anv_pipeline_cache *cache,
> > -const VkGraphicsPipelineCreateInfo *info,
> >   struct anv_pipeline_stage *stage)
> >   {
> >  const struct brw_compiler *compiler =
> > pipeline->device->instance->physicalDevice.compiler;
> >  struct anv_shader_bin *bin = NULL;
> >
> > -   ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
> > -
> >  if (bin == NULL) {
> > -  struct brw_vs_prog_data prog_data = {};
> > -  struct anv_pipeline_binding surface_to_descriptor[256];
> > -  struct anv_pipeline_binding sampler_to_descriptor[256];
> > -
> > -  struct anv_pipeline_bind_map map = {
> > - .surface_to_descriptor = surface_to_descriptor,
> > - .sampler_to_descriptor = sampler_to_descriptor
> > -  };
> > -
> > void *mem_ctx = ralloc_context(NULL);
> >
> > -  nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
> stage,
> > - _data.base.base,
> );
> > -  if (nir == NULL) {
> > - ralloc_free(mem_ctx);
> > - return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
> > -  }
> > -
> > -  anv_fill_binding_table(_data.base.base, 0);
> > +  anv_fill_binding_table(>prog_data.vs.base.base, 0);
> >
> > brw_compute_vue_map(>device->info,
> > -  _data.base.vue_map,
> > -  nir->info.outputs_written,
> > -  nir->info.separate_shader);
> > +  >prog_data.vs.base.vue_map,
> > +  stage->nir->info.outputs_written,
> > +  stage->nir->info.separate_shader);
> >
> > const unsigned *shader_code =
> >brw_compile_vs(compiler, NULL, mem_ctx, >key.vs,
> > -_data, nir, -1, NULL);
> > +>prog_data.vs, stage->nir, -1, NULL);
> > if (shader_code == NULL) {
> >ralloc_free(mem_ctx);
> >return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
> > }
> >
> > -  unsigned code_size = prog_data.base.base.program_size;
> > +  unsigned code_size = stage->prog_data.vs.base.base.program_size;
> > bin = anv_device_upload_kernel(pipeline->device, cache,
> >>cache_key,
> >sizeof(stage->cache_key),
> >shader_code, code_size,
> > - nir->constant_data,
> > - nir->constant_data_size,
> > - _data.base.base,
> sizeof(prog_data),
> > - );
> > + stage->nir->constant_data,
> > + stage->nir->constant_data_size,
> > + >prog_data.base,
> > + sizeof(stage->prog_data.vs),
> > + >bind_map);
> > if (!bin) {
> >ralloc_free(mem_ctx);
> >return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
> > @@ -654,7 +644,6 @@ merge_tess_info(struct shader_info *tes_info,
> >   static VkResult
> >   anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
> >struct anv_pipeline_cache *cache,
> > - const VkGraphicsPipelineCreateInfo *info,
> >struct anv_pipeline_stage *tcs_stage,
> >struct anv_pipeline_stage *tes_stage)
> >   {
> > @@ -664,85 +653,60 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline
> *pipeline,
> >  struct anv_shader_bin *tcs_bin = NULL;
> >  struct anv_shader_bin *tes_bin 

Re: [Mesa-dev] [PATCH v2 1/8] nir: evaluate if condition uses inside the if branches

[Timothy Arceri]

On 23/07/18 18:02, Timothy Arceri wrote:

Since we know what side of the branch we ended up on we can just
replace the use with a constant.

All the spill changes in shader-db are from Dolphin uber shaders,
despite some small regressions the change is clearly positive.

shader-db results IVB:

total instructions in shared programs: 201 -> 9993483 (-0.06%)
instructions in affected programs: 163235 -> 157517 (-3.50%)
helped: 132
HURT: 2

total cycles in shared programs: 231670754 -> 219476091 (-5.26%)
cycles in affected programs: 143424120 -> 131229457 (-8.50%)
helped: 115
HURT: 24

total spills in shared programs: 4383 -> 4370 (-0.30%)
spills in affected programs: 1656 -> 1643 (-0.79%)
helped: 9
HURT: 18

total fills in shared programs: 4610 -> 4581 (-0.63%)
fills in affected programs: 374 -> 345 (-7.75%)
helped: 6
HURT: 0
---
  src/compiler/nir/nir_opt_if.c | 124 ++
  1 file changed, 124 insertions(+)

diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index b3d0bf1decb..b3d5046a76e 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -369,6 +369,87 @@ opt_if_loop_terminator(nir_if *nif)
 return true;
  }
  
+static void

+replace_if_condition_use_with_const(nir_src *use, unsigned nir_boolean,
+void *mem_ctx, bool if_condition)
+{
+   /* Create const */
+   nir_load_const_instr *load = nir_load_const_instr_create(mem_ctx, 1, 32);
+   load->value.u32[0] = nir_boolean;
+
+   if (if_condition) {
+  nir_instr_insert_before_cf(>parent_if->cf_node,  >instr);
+   } else if (use->parent_instr->type == nir_instr_type_phi) {
+  nir_phi_instr *cond_phi = nir_instr_as_phi(use->parent_instr);
+
+  bool UNUSED found = false;
+  nir_foreach_phi_src(phi_src, cond_phi) {
+ if (phi_src->src.ssa == use->ssa) {
+nir_instr_insert_before_block(phi_src->pred, >instr);


I've just noticed this needs to be nir_instr_insert_after_block() 
otherwise we can end up inserting the const before so other phi which 
trips up validation.


I've fixed this locally.

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[Mesa-dev] [Bug 107224] Incorrect Rendering in Deus Ex: Mankind Divided in-game menu

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107224

--- Comment #3 from Timothy Arceri  ---
I also gave the Mesa 13.0-branchpoint with ca76e6b5213c92432b applied a try and
still see the issue there.

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Re: [Mesa-dev] [PATCH 17/18] anv/pipeline: Do cross-stage linking optimizations

[Timothy Arceri]

It would be good if you could reply to my comment in patch 13 otherwise 
1-17 are:


Reviewed-by: Timothy Arceri 

As mentioned before you really need the varying vector and array 
splitting passes to get the most from these linking opts.


Patch 18 seems ok but you might want to get someone else to look over it.

On 12/07/18 07:18, Jason Ekstrand wrote:

This appears to help the Aztec Ruins benchmark by about 2% on my Kaby
Lake gt2 laptop.
---
  src/intel/vulkan/anv_pipeline.c | 11 +++
  1 file changed, 11 insertions(+)

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 080a78e1cee..ab3b95e78ef 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -558,6 +558,9 @@ anv_pipeline_link_vs(const struct brw_compiler *compiler,
   struct anv_pipeline_stage *next_stage)
  {
 anv_fill_binding_table(_stage->prog_data.vs.base.base, 0);
+
+   if (next_stage)
+  brw_nir_link_shaders(compiler, _stage->nir, _stage->nir);
  }
  
  static const unsigned *

@@ -622,6 +625,8 @@ anv_pipeline_link_tcs(const struct brw_compiler *compiler,
  
 anv_fill_binding_table(_stage->prog_data.tcs.base.base, 0);
  
+   brw_nir_link_shaders(compiler, _stage->nir, _stage->nir);

+
 nir_lower_tes_patch_vertices(tes_stage->nir,
  tcs_stage->nir->info.tess.tcs_vertices_out);
  
@@ -666,6 +671,9 @@ anv_pipeline_link_tes(const struct brw_compiler *compiler,

struct anv_pipeline_stage *next_stage)
  {
 anv_fill_binding_table(_stage->prog_data.tes.base.base, 0);
+
+   if (next_stage)
+  brw_nir_link_shaders(compiler, _stage->nir, _stage->nir);
  }
  
  static const unsigned *

@@ -686,6 +694,9 @@ anv_pipeline_link_gs(const struct brw_compiler *compiler,
   struct anv_pipeline_stage *next_stage)
  {
 anv_fill_binding_table(_stage->prog_data.gs.base.base, 0);
+
+   if (next_stage)
+  brw_nir_link_shaders(compiler, _stage->nir, _stage->nir);
  }
  
  static const unsigned *



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Re: [Mesa-dev] [PATCH 13/18] anv/pipeline: Compile to NIR in compile_graphics

[Timothy Arceri]

On 12/07/18 07:18, Jason Ekstrand wrote:

This pulls the SPIR-V to NIR step out into common code.
---
  src/intel/vulkan/anv_pipeline.c | 278 +---
  1 file changed, 116 insertions(+), 162 deletions(-)

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index bc268b87e55..50d6ab358d2 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -404,6 +404,14 @@ struct anv_pipeline_stage {
gl_shader_stage stage;
unsigned char sha1[20];
 } cache_key;
+
+   nir_shader *nir;
+
+   struct anv_pipeline_binding surface_to_descriptor[256];
+   struct anv_pipeline_binding sampler_to_descriptor[256];
+   struct anv_pipeline_bind_map bind_map;
+
+   union brw_any_prog_data prog_data;
  };
  
  static void

@@ -547,58 +555,40 @@ anv_fill_binding_table(struct brw_stage_prog_data 
*prog_data, unsigned bias)
  static VkResult
  anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
  struct anv_pipeline_cache *cache,
-const VkGraphicsPipelineCreateInfo *info,
  struct anv_pipeline_stage *stage)
  {
 const struct brw_compiler *compiler =
pipeline->device->instance->physicalDevice.compiler;
 struct anv_shader_bin *bin = NULL;
  
-   ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);

-
 if (bin == NULL) {
-  struct brw_vs_prog_data prog_data = {};
-  struct anv_pipeline_binding surface_to_descriptor[256];
-  struct anv_pipeline_binding sampler_to_descriptor[256];
-
-  struct anv_pipeline_bind_map map = {
- .surface_to_descriptor = surface_to_descriptor,
- .sampler_to_descriptor = sampler_to_descriptor
-  };
-
void *mem_ctx = ralloc_context(NULL);
  
-  nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout, stage,

- _data.base.base, );
-  if (nir == NULL) {
- ralloc_free(mem_ctx);
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
-  }
-
-  anv_fill_binding_table(_data.base.base, 0);
+  anv_fill_binding_table(>prog_data.vs.base.base, 0);
  
brw_compute_vue_map(>device->info,

-  _data.base.vue_map,
-  nir->info.outputs_written,
-  nir->info.separate_shader);
+  >prog_data.vs.base.vue_map,
+  stage->nir->info.outputs_written,
+  stage->nir->info.separate_shader);
  
const unsigned *shader_code =

   brw_compile_vs(compiler, NULL, mem_ctx, >key.vs,
-_data, nir, -1, NULL);
+>prog_data.vs, stage->nir, -1, NULL);
if (shader_code == NULL) {
   ralloc_free(mem_ctx);
   return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
}
  
-  unsigned code_size = prog_data.base.base.program_size;

+  unsigned code_size = stage->prog_data.vs.base.base.program_size;
bin = anv_device_upload_kernel(pipeline->device, cache,
   >cache_key,
   sizeof(stage->cache_key),
   shader_code, code_size,
- nir->constant_data,
- nir->constant_data_size,
- _data.base.base, sizeof(prog_data),
- );
+ stage->nir->constant_data,
+ stage->nir->constant_data_size,
+ >prog_data.base,
+ sizeof(stage->prog_data.vs),
+ >bind_map);
if (!bin) {
   ralloc_free(mem_ctx);
   return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
@@ -654,7 +644,6 @@ merge_tess_info(struct shader_info *tes_info,
  static VkResult
  anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
   struct anv_pipeline_cache *cache,
- const VkGraphicsPipelineCreateInfo *info,
   struct anv_pipeline_stage *tcs_stage,
   struct anv_pipeline_stage *tes_stage)
  {
@@ -664,85 +653,60 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline 
*pipeline,
 struct anv_shader_bin *tcs_bin = NULL;
 struct anv_shader_bin *tes_bin = NULL;
  
-   ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);

-
 if (tcs_bin == NULL || tes_bin == NULL) {
-  struct brw_tcs_prog_data tcs_prog_data = {};
-  struct brw_tes_prog_data tes_prog_data = {};
-  struct anv_pipeline_binding tcs_surface_to_descriptor[256];
-  struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
-  struct anv_pipeline_binding tes_surface_to_descriptor[256];
-  struct 

[Mesa-dev] [PATCH 2/2] intel/compiler: Add brw_get_compiler_config_value for disk cache

[Jordan Justen]

During code review, Jason pointed out that:

2b3064c0731 "i965, anv: Use INTEL_DEBUG for disk_cache driver flags"

Didn't account for INTEL_SCALER_* environment variables.

To fix this, let the compiler return the disk_cache driver flags.

Another possible fix would be to pull the INTEL_SCALER_* into
INTEL_DEBUG bits, but as we are currently using 41 of 64 bits, I
didn't think it was a good use of 4 more of these bits. (5 since
INTEL_PRECISE_TRIG needs to be accounted for as well.)

Cc: Jason Ekstrand 
Signed-off-by: Jordan Justen 
---
 src/intel/compiler/brw_compiler.c  | 26 ++
 src/intel/compiler/brw_compiler.h  | 11 +
 src/intel/vulkan/anv_device.c  |  3 ++-
 src/mesa/drivers/dri/i965/brw_disk_cache.c |  3 ++-
 4 files changed, 41 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c
index 6480dbefbf6..ba6b8e0cbbe 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -180,6 +180,32 @@ brw_compiler_create(void *mem_ctx, const struct 
gen_device_info *devinfo)
 
return compiler;
 }
+static void
+insert_u64_bit(uint64_t *val, bool add)
+{
+   *val = (*val << 1) | !!add;
+}
+
+const uint64_t
+brw_get_compiler_config_value(const struct brw_compiler *compiler)
+{
+   uint64_t config = 0;
+   insert_u64_bit(, compiler->precise_trig);
+   if (compiler->devinfo->gen >= 8 && compiler->devinfo->gen < 10) {
+  insert_u64_bit(, compiler->scalar_stage[MESA_SHADER_VERTEX]);
+  insert_u64_bit(, compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
+  insert_u64_bit(, compiler->scalar_stage[MESA_SHADER_TESS_EVAL]);
+  insert_u64_bit(, compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
+   }
+   uint64_t debug_bits = INTEL_DEBUG;
+   uint64_t mask = DEBUG_DISK_CACHE_MASK;
+   while (mask != 0) {
+  const uint64_t bit = 1ULL << (ffsll(mask) - 1);
+  insert_u64_bit(, (debug_bits & bit) != 0);
+  mask &= ~bit;
+   }
+   return config;
+}
 
 unsigned
 brw_prog_data_size(gl_shader_stage stage)
diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h
index 9dfcfcc0115..efefbbca64b 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1212,6 +1212,17 @@ DEFINE_PROG_DATA_DOWNCAST(sf)
 
 struct brw_compiler *
 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo);
+/**
+ * Returns a compiler configuration for use with shader_config
+ *
+ * This value only needs to change for settings that can cause different
+ * program generation between two runs on the same hardware.
+ *
+ * For example, it doesn't need to be different for gen 8 and gen 9 hardware,
+ * but it does need to be different if INTEL_DEBUG=nocompact is or isn't used.
+ */
+const uint64_t
+brw_get_compiler_config_value(const struct brw_compiler *compiler);
 
 unsigned
 brw_prog_data_size(gl_shader_stage stage);
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 6b72a79a914..c40b94d69f3 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -286,7 +286,8 @@ anv_physical_device_init_disk_cache(struct 
anv_physical_device *device)
char timestamp[41];
_mesa_sha1_format(timestamp, device->driver_build_sha1);
 
-   const uint64_t driver_flags = INTEL_DEBUG & DEBUG_DISK_CACHE_MASK;
+   const uint64_t driver_flags =
+  brw_get_compiler_config_value(device->compiler);
device->disk_cache = disk_cache_create(renderer, timestamp, driver_flags);
 #else
device->disk_cache = NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index 0797e6eac44..9a6f2ff570c 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -396,7 +396,8 @@ brw_disk_cache_init(struct intel_screen *screen)
char timestamp[41];
_mesa_sha1_format(timestamp, id_sha1);
 
-   const uint64_t driver_flags = INTEL_DEBUG & DEBUG_DISK_CACHE_MASK;
+   const uint64_t driver_flags =
+  brw_get_compiler_config_value(screen->compiler);
screen->disk_cache = disk_cache_create(renderer, timestamp, driver_flags);
 #endif
 }
-- 
2.18.0

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[Mesa-dev] [PATCH 1/2] i965: Disable shader cache with INTEL_DEBUG=shader_time

[Jordan Justen]

Shader time hard codes an index of the shader time buffer within the
gen program.

In order to support shader time in the disk shader cache, we'd need to
add the shader time index into the program key. This should work, but
probably is not worth it for this particular debug feature.

Therefore, let's just disable the disk shader cache if the shader time
debug feature is used.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106382
Fixes: 96fe36f7acc "i965: Enable disk shader cache by default"
Cc: Eero Tamminen 
Cc: Kenneth Graunke 
Signed-off-by: Jordan Justen 
---
 src/intel/common/gen_debug.h   | 7 +--
 src/mesa/drivers/dri/i965/brw_disk_cache.c | 3 +++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h
index aa9f3cf80d7..72d7ca20a39 100644
--- a/src/intel/common/gen_debug.h
+++ b/src/intel/common/gen_debug.h
@@ -84,10 +84,13 @@ extern uint64_t INTEL_DEBUG;
 #define DEBUG_COLOR   (1ull << 40)
 #define DEBUG_REEMIT  (1ull << 41)
 
+/* These flags are not compatible with the disk shader cache */
+#define DEBUG_DISK_CACHE_DISABLE_MASK DEBUG_SHADER_TIME
+
 /* These flags may affect program generation */
 #define DEBUG_DISK_CACHE_MASK \
-   (DEBUG_SHADER_TIME | DEBUG_NO16 | DEBUG_NO_DUAL_OBJECT_GS | DEBUG_NO8 | \
-   DEBUG_SPILL_FS | DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32)
+   (DEBUG_NO16 | DEBUG_NO_DUAL_OBJECT_GS | DEBUG_NO8 |  DEBUG_SPILL_FS | \
+   DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32)
 
 #ifdef HAVE_ANDROID_PLATFORM
 #define LOG_TAG "INTEL-MESA"
diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index 8f1b064fd61..0797e6eac44 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -377,6 +377,9 @@ void
 brw_disk_cache_init(struct intel_screen *screen)
 {
 #ifdef ENABLE_SHADER_CACHE
+   if (INTEL_DEBUG & DEBUG_DISK_CACHE_DISABLE_MASK)
+  return;
+
/* array length: print length + null char + 1 extra to verify it is unused 
*/
char renderer[11];
MAYBE_UNUSED int len = snprintf(renderer, sizeof(renderer), "i965_%04x",
-- 
2.18.0

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Re: [Mesa-dev] [PATCH mesa] docs: trivial html fix

[Jordan Justen]

You might as well add something like ">" => "" to the subject.

Reviewed-by: Jordan Justen 

On 2018-07-25 12:18:34, Eric Engestrom wrote:
> Signed-off-by: Eric Engestrom 
> ---
>  docs/releasing.html | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/docs/releasing.html b/docs/releasing.html
> index a022d0c484bc0f635b61..69d8656e59d567033087 100644
> --- a/docs/releasing.html
> +++ b/docs/releasing.html
> @@ -492,10 +492,10 @@ Perform basic testing
> # Drop LLVM_CONFIG, if applicable:
> # unset LLVM_CONFIG
>  
> -   __glxinfo_cmd='glxinfo 2>1 | egrep -o 
> "Mesa.*|Gallium.*|.*dri\.so"'
> -   __glxgears_cmd='glxgears 2>1 | grep -v "configuration file"'
> -   __es2info_cmd='es2_info 2>1 | egrep 
> "GL_VERSION|GL_RENDERER|.*dri\.so"'
> -   __es2gears_cmd='es2gears_x11 2>1 | grep -v "configuration file"'
> +   __glxinfo_cmd='glxinfo 21 | egrep -o 
> "Mesa.*|Gallium.*|.*dri\.so"'
> +   __glxgears_cmd='glxgears 21 | grep -v "configuration file"'
> +   __es2info_cmd='es2_info 21 | egrep 
> "GL_VERSION|GL_RENDERER|.*dri\.so"'
> +   __es2gears_cmd='es2gears_x11 21 | grep -v "configuration 
> file"'
> test "x$LD_LIBRARY_PATH" != 'x'  __old_ld="$LD_LIBRARY_PATH"
> export LD_LIBRARY_PATH=`pwd`/test/usr/local/lib/:"${__old_ld}"
> export LIBGL_DRIVERS_PATH=`pwd`/test/usr/local/lib/dri/
> -- 
> Cheers,
>   Eric
> 
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Re: [Mesa-dev] [PATCH] gallium/auxiliary: Fix Autotools on Android

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Tue, Jul 24, 2018 at 8:54 PM, Chad Versace  wrote:
> u_debug_stack_android.cpp transitively included "pipe/p_compiler.h", but
> src/gallium/include was missing from the C++ include path.
>
> Cc: Gurchetan Singh 
> Cc: Eric Engestrom 
> ---
>  src/gallium/auxiliary/Makefile.am | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/Makefile.am 
> b/src/gallium/auxiliary/Makefile.am
> index 03908198772..81dfc331df1 100644
> --- a/src/gallium/auxiliary/Makefile.am
> +++ b/src/gallium/auxiliary/Makefile.am
> @@ -13,6 +13,7 @@ AM_CFLAGS = \
> $(MSVC2013_COMPAT_CFLAGS)
>
>  AM_CXXFLAGS = \
> +   $(GALLIUM_CFLAGS) \
> $(VISIBILITY_CXXFLAGS) \
> $(MSVC2013_COMPAT_CXXFLAGS)
>
> @@ -41,7 +42,6 @@ AM_CFLAGS += \
> $(LLVM_CFLAGS)
>
>  AM_CXXFLAGS += \
> -   $(GALLIUM_CFLAGS) \
> $(LLVM_CXXFLAGS)
>
>  libgallium_la_SOURCES += \
> --
> 2.18.0.233.g985f88cf7e-goog
>
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Re: [Mesa-dev] [PATCH v2] docs: fix incorrect placement of the ARB_sample_locations release notes

[Marek Olšák]

Reviewed-by: Marek OIšák 

Marek

On Wed, Jul 25, 2018 at 9:18 AM, Rhys Perry  wrote:
> Seems something went wrong somehow when it was pushed.
>
> v2: combine into one list
>
> Signed-off-by: Rhys Perry 
> ---
>  docs/relnotes/18.2.0.html | 5 +
>  1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html
> index f757f4148a..8cdf6ac7d7 100644
> --- a/docs/relnotes/18.2.0.html
> +++ b/docs/relnotes/18.2.0.html
> @@ -52,14 +52,11 @@ Note: some of the new features are only available with 
> certain drivers.
>
>  
>  GL_ARB_fragment_shader_interlock on i965
> +GL_ARB_sample_locations and GL_NV_sample_locations on nvc0 (GM200+)
>  
>
>  Bug fixes
>
> -
> -GL_ARB_sample_locations and GL_NV_sample_locations on nvc0 (GM200+)
> -
> -
>  Changes
>
>  
> --
> 2.14.4
>
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Re: [Mesa-dev] [PATCH] i965: Expose ARB_base_instance extension

[Anuj Phogat]

On Wed, Jul 25, 2018 at 10:49 AM Sagar Ghuge  wrote:
>
> The extension requires at least OpenGL 3.0 and
> OpenGL ES 3.0.
>
> Fixes two ext_base_instance tests:
>
> arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3
> arb_base_instance-drawarrays_gles3
>
> Signed-off-by: Sagar Ghuge 
> ---
>  src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index f837356478..9d119d0b4c 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -315,7 +315,7 @@ intelInitExtensions(struct gl_context *ctx)
> if (devinfo->gen >= 6)
>ctx->Extensions.INTEL_performance_query = true;
>
> -   if (ctx->API == API_OPENGL_CORE)
> +   if (ctx->API != API_OPENGL_COMPAT)
>ctx->Extensions.ARB_base_instance = true;
> if (ctx->API != API_OPENGL_CORE)
>ctx->Extensions.ARB_color_buffer_float = true;
> --
> 2.17.1
>
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It's EXT_base_instance for gles.
With suggested changes to Subject:
Reviewed-by: Anuj Phogat 
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Re: [Mesa-dev] [PATCH 0/7] ASTC texture compression for all Gallium drivers

[Gert Wollny]

Am Montag, den 23.07.2018, 19:52 -0400 schrieb Marek Olšák:
> Hi,
> 
> This series enables ASTC texture compression for all Gallium drivers
> that don't support it in hardware. The works the same as the ETC2
> fallback, i.e. it decompresses ASTC inside glCompressedTexImage to
> a supported uncompressed format.

Tested on r600 (Barts), moves 2978 tests of 

  dEQP-
GLES31.functional.copy_image.mixed.viewclass_128_bits_mixed.*astc* 
  dEQP-GLES31.functional.copy_image.compressed.viewclass_astc.*astc* 

from NotSupported to Pass, 

Tested-By: Gert Wollny


> RadeonSI now finally supports the following:
> - GL_KHR_texture_compression_astc_ldr
> - GL_ANDROID_extension_pack_es31a
> - OpenGL ES 3.2 !!!
> 
> All ASTC dEQP tests pass.
> 
> Please review.
> 
> Thanks,
> Marek
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Re: [Mesa-dev] [PATCH v2 0/2] Add DRMless surfaceless fallback path.

[David Riley]

Ping for this patch set.

On Tue, Jul 17, 2018 at 5:12 PM David Riley  wrote:

> Allow platform_surfaceless to use swrast even if DRM is not available.
> To be used to allow a fuzzer for virgl to be run on a jailed VM without
> hardware GL or DRM support.
>
> v2: Comment style fixes and remove redundant assignment.
>
> David Riley (2):
>   egl/surfaceless: Define DRI_SWRastLoader extension when using swrast.
>   egl/surfaceless: Allow DRMless fallback.
>
>  src/egl/drivers/dri2/platform_surfaceless.c | 47 ++---
>  1 file changed, 42 insertions(+), 5 deletions(-)
>
> --
> 2.18.0.203.gfac676dfb9-goog
>
>
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[Mesa-dev] [PATCH 2/2] intel/fs: Write multiple 8/16-bit components with byte_scattered_write

[Jose Maria Casanova Crespo]

We also pack in the same byte_scattered_write message the maximum
number of 8/16-bit components.

Comments have been rewritten to adapt them to the 8-bit case.
---
 src/intel/compiler/brw_fs_nir.cpp | 66 ++-
 1 file changed, 38 insertions(+), 28 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index a1f946708ed..7259acb862e 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4263,6 +4263,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
  fs_reg write_src = offset(val_reg, bld, first_component);
 
  nir_const_value *const_offset = nir_src_as_const_value(instr->src[2]);
+ bool use_scattered_write = false;
 
  if (type_size > 4) {
 /* We can't write more than 2 64-bit components at once. Limit
@@ -4273,29 +4274,38 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
 write_src = shuffle_for_32bit_write(bld, write_src, 0,
 num_components);
  } else if (type_size < 4) {
-/* For 16-bit types we pack two consecutive values into a 32-bit
- * word and use an untyped write message. For single values or not
- * 32-bit-aligned we need to use byte-scattered writes because
- * untyped writes works with 32-bit components with 32-bit
- * alignment. byte_scattered_write messages only support one
- * 16-bit component at a time. As VK_KHR_relaxed_block_layout
- * could be enabled we can not guarantee that not constant offsets
- * to be 32-bit aligned for 16-bit types. For example an array, of
- * 16-bit vec3 with array element stride of 6.
+/* For 8/16-bit types we pack consecutive values into a 32-bit
+ * type and use an untyped write message. When size is not
+ * multiple of 4-bytes or offset is not 32-bit-aligned we need to
+ * use byte-scattered writes because they didn't require 32-bit
+ * components or 32-bit offset alignment. We can pack multiple
+ * 8/16-bit components on one 8/16/32-bit component used by the
+ * byte_scattered_write message.
+ *
+ * As VK_KHR_relaxed_block_layout could be requested and it is
+ * core in VK 1.1 we can not guarantee not constant offsets to be
+ * 32-bit aligned for 8/16-bit types. For example a 16-bit vec3
+ * begin with at offset 2 in a structure.
  *
  * In the case of 32-bit aligned constant offsets if there is
- * a 3-components vector we submit one untyped-write message
+ * a 16-bit vec3 we submit one untyped-write message
  * of 32-bit (first two components), and one byte-scattered
  * write message (the last component).
  */
-
-if ( !const_offset || ((const_offset->u32[0] +
-   type_size * first_component) % 4)) {
-   /* If we use a .yz writemask we also need to emit 2
-* byte-scattered write messages because of y-component not
-* being aligned to 32-bit.
+if (!const_offset || ((const_offset->u32[0] +
+   type_size * first_component) % 4) ||
+num_components * type_size < 4) {
+   /* If we don't have a constant offset or a constant offset
+* not 32-bit aligned or we are reading less than 32-bits then
+* we use byte_scattered_write with the maximum number of
+* components we can pack exactly into one 8/16/32-bit 
component.
+* So for a int8 vec3 we have to split into two one 16-bit and
+* another 8-bit writtings.
 */
-   num_components = 1;
+   use_scattered_write = true;
+   num_components = MIN2(4 / type_size, num_components);
+   if (num_components == 3)
+  num_components = 2;
 } else if (num_components * type_size > 4 &&
(num_components * type_size % 4)) {
/* If the pending components size is not a multiple of 4 bytes
@@ -4303,13 +4313,10 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
 * length == 1 with byte_scattered_write.
 */
num_components -= (num_components * type_size % 4) / type_size;
-} else if (num_components * type_size < 4) {
-   num_components = 1;
 }
 /* For num_components == 1 we are also shuffling the component
- * because byte scattered writes of 16-bit need values to be dword
- * aligned. Shuffling only one component would be 

[Mesa-dev] [PATCH 1/2] intel/fs: Read multiple 8/16-bit components with byte_scattered_read

[Jose Maria Casanova Crespo]

We used the byte_scattered_read message because it allows to read from
non aligned 32-bit offsets. We were reading one component for each
message.

Using a 32-bit bitsize read at byte_scattered_read we can read up to two
16-bit components or four 8-bit components with only one message per
iteration.

The same applies for 16-bit bitsize for two 8-bit components read. In
the case of int8 vec3, we read them as 32-bit and we ignore the padding.

Cc: Jason Ekstrand 
---
 src/intel/compiler/brw_fs_nir.cpp | 28 +++-
 1 file changed, 19 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 9b11b5fbd01..a1f946708ed 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -2415,24 +2415,34 @@ do_untyped_vector_read(const fs_builder ,
  num_components);
   } else {
  fs_reg read_offset = bld.vgrf(BRW_REGISTER_TYPE_UD);
- for (unsigned i = 0; i < num_components; i++) {
-if (i == 0) {
+ unsigned iters = DIV_ROUND_UP(type_sz(dest.type) * num_components, 4);
+ for (unsigned it = 0; it < iters; it++) {
+if (it == 0) {
bld.MOV(read_offset, offset_reg);
 } else {
-   bld.ADD(read_offset, offset_reg,
-   brw_imm_ud(i * type_sz(dest.type)));
+   bld.ADD(read_offset, offset_reg, brw_imm_ud(4 * it));
 }
+unsigned iter_components = MIN2(4 / type_sz(dest.type),
+num_components);
+num_components -= iter_components;
+/* We adjust the bitsize_read to hold as many components we can in
+ * the same read message. We use 32-bit to read 8-bit vec3 but we
+ * ignore last padding.component.
+ */
+unsigned bitsize_read = util_next_power_of_two(8 * iter_components 
*
+   type_sz(dest.type));
 /* Non constant offsets are not guaranteed to be aligned 32-bits
- * so they are read using one byte_scattered_read message
- * for each component.
+ * for 8/16 bit componentes. We use byte_scattered_read for
+ * one or multiple components up to 4-bytes for iteration.
  */
 fs_reg read_result =
emit_byte_scattered_read(bld, surf_index, read_offset,
 1 /* dims */, 1,
-type_sz(dest.type) * 8 /* bit_size */,
+bitsize_read,
 BRW_PREDICATE_NONE);
-bld.MOV(offset(dest, bld, i),
-subscript (read_result, dest.type, 0));
+shuffle_from_32bit_read(bld, offset(dest, bld,
+it * 4 / type_sz(dest.type)),
+read_result, 0, iter_components);
  }
   }
} else if (type_sz(dest.type) == 4) {
-- 
2.17.1

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Re: [Mesa-dev] [PATCH mesa] anv: don't crash on vkDestroyDevice(NULL)

[Dylan Baker]

Quoting Eric Engestrom (2018-07-25 11:45:56)
> CovID: 1438132
> Signed-off-by: Eric Engestrom 
> ---
>  src/intel/vulkan/anv_device.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 04fd6a829ed60081abc4..3664f80c24dc34955196 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -1832,11 +1832,13 @@ void anv_DestroyDevice(
>  const VkAllocationCallbacks*pAllocator)
>  {
> ANV_FROM_HANDLE(anv_device, device, _device);
> -   struct anv_physical_device *physical_device = 
> >instance->physicalDevice;
> +   struct anv_physical_device *physical_device;

Is there a particular reason to create the pointer her but assign it after the
null check rather than just move the null check between the ANV_FROM_HANDLE and
the anv_pysical_device?

>  
> if (!device)
>return;
>  
> +   physical_device = >instance->physicalDevice;
> +
> anv_device_finish_blorp(device);
>  
> anv_pipeline_cache_finish(>default_pipeline_cache);
> -- 
> Cheers,
>   Eric
> 
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Re: [Mesa-dev] [PATCH mesa] anv: remove incorrect `UNUSED` flag

[Dylan Baker]

Reviewed-by: Dylan Baker 

Quoting Eric Engestrom (2018-07-25 12:11:44)
> Signed-off-by: Eric Engestrom 
> ---
>  src/intel/vulkan/anv_image.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
> index 5d9becf51723b8a4ca47..36d4ac13c75d8a22e7ee 100644
> --- a/src/intel/vulkan/anv_image.c
> +++ b/src/intel/vulkan/anv_image.c
> @@ -303,7 +303,7 @@ make_surface(const struct anv_device *dev,
>   VkImageAspectFlagBits aspect)
>  {
> const VkImageCreateInfo *vk_info = anv_info->vk_info;
> -   bool ok UNUSED;
> +   bool ok;
>  
> static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
>[VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
> -- 
> Cheers,
>   Eric
> 
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Re: [Mesa-dev] [RFC][PATCH 5/5] Android.mk: Fix checkbuild on Mac builders.

[John Stultz]

On Wed, Jul 25, 2018 at 12:33 PM, Alistair Strachan
 wrote:
> On Wed, Jul 25, 2018 at 5:48 AM Emil Velikov  wrote:
>>
>> On 25 July 2018 at 00:21, John Stultz  wrote:
>> > From: Alistair Strachan 
>> >
>> > This is a forward port of a patch in the AOSP/master tree:
>> > https://android.googlesource.com/platform/external/mesa3d/+/d7f894a7d39e66ca5a832c19edaf175400041aff%5E%21/
>> >
>> > The libmesa_dri_common target depends on xgettext unconditionally, but
>> > this is not a documented dependency of AOSP and is not installed on the
>> > Mac builders, so we must not build any part of mesa3d on these
>> > platforms.
>> >
>> > Cc: Rob Herring 
>> > Cc: Alistair Strachan 
>> > Cc: Marissa Wall 
>> > Cc: Sumit Semwal 
>> > Cc: Emil Velikov 
>> > Cc: Rob Clark 
>> > Signed-off-by: Alistair Strachan 
>> > Signed-off-by: John Stultz 
>> > ---
>> >  Android.mk | 5 -
>> >  1 file changed, 4 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/Android.mk b/Android.mk
>> > index 494b4b9..128db4d 100644
>> > --- a/Android.mk
>> > +++ b/Android.mk
>> > @@ -30,6 +30,8 @@
>> >  # module will also be built.  DRI modules will be loaded by libGLES_mesa.
>> >
>> >  ifneq ($(BOARD_USE_CUSTOMIZED_MESA), true)
>> > +ifneq ($(BOARD_GPU_DRIVERS),)
>> > +
>>
>> Something looks fairly weird here. Commit message talks about Mac and
>> xgettext while this here checks for BOARD_GPU_DRIVERS.
>
> This change is actually papering over another bug in the makefiles: if
> BOARD_GPU_DRIVERS is the empty string, bits of mesa (I think the Intel
> drivers IIRC) will still be built due to some makefile logic that I
> didn't track down yet. This can be reproduced with "mmma
> external/mesa3d" for a device that does not specify
> BOARD_GPU_DRIVERS).

Ok. Sounds like I should drop this and we'll see about reworking a
better solution.

>> Or looking it from another angle - if the Mac builder is missing
>> xgettext one could add it, becoming in sync with other builders.
>> Quick search shows that it's available in brew (brew install gettext)
>> and one can build it locally.
>
> AFAICT this won't happen. The dependencies for AOSP are documented on
> https://source.android.com/setup/build/initializing, and this list
> does not include xgettext. It's just that Linux distros tend to
> include xgettext in even the most minimal installation. On Mac, such a
> list (other than the one documented by that page) does not exist. To
> me, this seems like a porting issue that should be resolved
> appropriately for AOSP.
>
> (IOW: ideally the dependencies on xgettext and python-maco should be
> removed so that these tools are not required to build Mesa for
> Android. The python-maco dependency has been worked around on the AOSP
> fork of mesa by directing the makefiles to a set of pregenerated files
> but this change, along with the hack discussed here, is not a
> good/sustainable solution.)

Agreed, we'll have to sort out something else then.

Thanks so much for the feedback/explaination here!

-john
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Re: [Mesa-dev] [RFC][PATCH 3/5] CleanSpec.mk: Remove HOST_OUT_release

[Dan Willemsen]

On Wed, Jul 25, 2018 at 12:35 PM John Stultz  wrote:
>
> On Wed, Jul 25, 2018 at 5:36 AM, Emil Velikov  
> wrote:
> > On 25 July 2018 at 00:21, John Stultz  wrote:
> >> From: Dan Willemsen 
> >>
> >> This is a forward port of a patch from the AOSP/master tree:
> >> https://android.googlesource.com/platform/external/mesa3d/+/bd633f11de0c6ac1ed333a28344c74fd9898df9e%5E%21/
> >>
> >> Which replaces HOST_OUT_release with HOST_OUT
> >>
> > What's wrong with HOST_OUT_release? If it is something that got
> > deprecated, we could:
> >  a) add a comment above it (deprecated since Android ...)
> >  b) add the HOST_OUT alongside the existing HOST_OUT_release
>
> Seems to be the case since:
> https://android.googlesource.com/platform/build/+/d6ed368fde0609742540b5da6d2e8a2a19b2c0eb%5E%21/
>
> Dan/Alistair: Any objections to option b?

You can't add side-by-side, since new lines must be added at the end of the
file (the makefiles keep track of which lines were run by index, not their
contents). But when that variable isn't set, it would try to remove
"/*/EXECUTABLES/...
You could do something like:

ifdef HOST_OUT_release
...
else
...
endif

But it was already incorrect to use $(HOST_OUT_release) here, $(HOST_OUT) will
be set properly for whether the current build that's being cleaned during
incrementals is using host debug or release builds (it was incredibly uncommon
to use a debug host build, there was never a shortcut to use that, you had to
set an environment variable manually, and it was rarely if ever tested).

I'll also note that the Android.mk files are not guaranteed to be compatible
between releases, even more so as we're switching away from Make.

- Dan
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Re: [Mesa-dev] [RFC][PATCH 5/5] Android.mk: Fix checkbuild on Mac builders.

[Alistair Strachan]

On Wed, Jul 25, 2018 at 5:48 AM Emil Velikov  wrote:
>
> On 25 July 2018 at 00:21, John Stultz  wrote:
> > From: Alistair Strachan 
> >
> > This is a forward port of a patch in the AOSP/master tree:
> > https://android.googlesource.com/platform/external/mesa3d/+/d7f894a7d39e66ca5a832c19edaf175400041aff%5E%21/
> >
> > The libmesa_dri_common target depends on xgettext unconditionally, but
> > this is not a documented dependency of AOSP and is not installed on the
> > Mac builders, so we must not build any part of mesa3d on these
> > platforms.
> >
> > Cc: Rob Herring 
> > Cc: Alistair Strachan 
> > Cc: Marissa Wall 
> > Cc: Sumit Semwal 
> > Cc: Emil Velikov 
> > Cc: Rob Clark 
> > Signed-off-by: Alistair Strachan 
> > Signed-off-by: John Stultz 
> > ---
> >  Android.mk | 5 -
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/Android.mk b/Android.mk
> > index 494b4b9..128db4d 100644
> > --- a/Android.mk
> > +++ b/Android.mk
> > @@ -30,6 +30,8 @@
> >  # module will also be built.  DRI modules will be loaded by libGLES_mesa.
> >
> >  ifneq ($(BOARD_USE_CUSTOMIZED_MESA), true)
> > +ifneq ($(BOARD_GPU_DRIVERS),)
> > +
>
> Something looks fairly weird here. Commit message talks about Mac and
> xgettext while this here checks for BOARD_GPU_DRIVERS.

This change is actually papering over another bug in the makefiles: if
BOARD_GPU_DRIVERS is the empty string, bits of mesa (I think the Intel
drivers IIRC) will still be built due to some makefile logic that I
didn't track down yet. This can be reproduced with "mmma
external/mesa3d" for a device that does not specify
BOARD_GPU_DRIVERS).

As part of 'checkbuild', all reachable modules will be built for a
given lunch target, this means all modules *must build* or the modules
should not be emitted in the first place. If that bug was tracked down
and fixed, we wouldn't need to mask the parsing of the mesa
makefile/directory because BOARD_GPU_DRIVERS being the empty string
would be enough to suppress these driver module definitions.

> IIRC, libGLES_mesa must be explicitly pulled in the device
> manifest/project in order to for Mesa be built. The exact same one
> tends to set BOARD_GPU_DRIVERS.

external/mesa3d is part of the upstream manifest. We are therefore
holding this project to the highest standard: all modules must build
on all targets, or be appropriately suppressed. All modules reachable
with "mmm" must build for every target.

> Or looking it from another angle - if the Mac builder is missing
> xgettext one could add it, becoming in sync with other builders.
> Quick search shows that it's available in brew (brew install gettext)
> and one can build it locally.

AFAICT this won't happen. The dependencies for AOSP are documented on
https://source.android.com/setup/build/initializing, and this list
does not include xgettext. It's just that Linux distros tend to
include xgettext in even the most minimal installation. On Mac, such a
list (other than the one documented by that page) does not exist. To
me, this seems like a porting issue that should be resolved
appropriately for AOSP.

(IOW: ideally the dependencies on xgettext and python-maco should be
removed so that these tools are not required to build Mesa for
Android. The python-maco dependency has been worked around on the AOSP
fork of mesa by directing the makefiles to a set of pregenerated files
but this change, along with the hack discussed here, is not a
good/sustainable solution.)

> -Emil
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Re: [Mesa-dev] [PATCH mesa 1/3] anv: remove unnecessary semicolons in python

[Dylan Baker]

for the series:
Reviewed-by: Dylan Baker 

Quoting Eric Engestrom (2018-07-25 12:14:50)
> Signed-off-by: Eric Engestrom 
> ---
>  src/intel/vulkan/anv_extensions.py | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_extensions.py 
> b/src/intel/vulkan/anv_extensions.py
> index ea837744b4352845b0d5..cffc3e700cb0ccb7fa8f 100644
> --- a/src/intel/vulkan/anv_extensions.py
> +++ b/src/intel/vulkan/anv_extensions.py
> @@ -31,11 +31,11 @@
>  
>  def _bool_to_c_expr(b):
>  if b is True:
> -return 'true';
> +return 'true'
>  elif b is False:
> -return 'false';
> +return 'false'
>  else:
> -return b;
> +return b
>  
>  class Extension:
>  def __init__(self, name, ext_version, enable):
> -- 
> Cheers,
>   Eric
> 
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Re: [Mesa-dev] [ANNOUNCE] Mesa 18.1.5 Candidate

[Dylan Baker]

Quoting Nanley Chery (2018-07-25 13:17:47)
> On Wed, Jul 25, 2018 at 11:47:59AM -0700, Dylan Baker wrote:
> > Greetings,
> > 
> > Mesa the staging/18.1 branch is currently slushed for 18.1.5, and assuming 
> > that
> > there are no regressions or patches critically necessary this will be 
> > merged to
> > the 18.1 branch for a release Friday morning, July 27th around 10 AM PDT.
> > 
> > Currently the branch has the following changes since 18.1.4:
> >  - 45 queued
> >  - 0 nominated (outstanding)
> >  - and 1 rejected patch
> > 
> > The one rejected patch was de-nominated by the author.
> > 
> > Note: there are 4 cherry-ignore patches, but 3 are for patches that required
> > manual backport, and thus the cherry-picked from line does not match the 
> > commit
> > in master.
> > 
> > All merge conflicts that I resolved have already been verified by the 
> > original
> > patch authors.
> > 
> > Dylan
> > 
> > Shortlog of changes:
> > 
> > Alex Smith (1):
> >   anv: Pay attention to VK_ACCESS_MEMORY_(READ|WRITE)_BIT
> > 
> > Bas Nieuwenhuizen (7):
> >   radv: Select correct entries for binning.
> >   radv: Fix number of samples used for binning.
> >   radv: Disable disabled color buffers in rbplus opts.
> >   nir: Do not use continue block after removing it.
> >   util/disk_cache: Fix disk_cache_get_function_timestamp with disabled 
> > cache.
> >   nir: Fix end of function without return warning/error.
> >   radv: Still enable inmemory & API level caching if disk cache is not 
> > enabled.
> > 
> > Chad Versace (2):
> >   anv/android: Fix type error in call to vk_errorf()
> >   anv/android: Fix Autotools build for VK_ANDROID_native_buffer
> > 
> > Chih-Wei Huang (1):
> >   Android: fix a missing nir_intrinsics.h error
> > 
> > Danylo Piliaiev (1):
> >   i965: Sweep NIR after linking phase to free held memory
> > 
> > Dave Airlie (1):
> >   r600: enable tess_input_info for TES
> > 
> > Dylan Baker (5):
> >   docs: Add sha256 sums for 18.1.4 tarballs
> >   cherry-ignore: add 4a67ce886a7b3def5f66c1aedf9e5436d157a03c
> >   cherry-ignore: Add 1f616a840eac02241c585d28e9dac8f19a297f39
> >   cherry-ignore: add 11712b9ca17e4e1a819dcb7d020e19c6da77bc90
> >   cherry-ignore: Add 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
> > 
> > Eric Anholt (2):
> >   vc4: Don't automatically reallocate a PERSISTENT-mapped buffer.
> >   meson: Move xvmc test tools from unit tests to installed tools.
> > 
> > Harish Krupo (1):
> >   egl: Fix missing clamping in eglSetDamageRegionKHR
> > 
> > Jan Vesely (3):
> >   radeonsi: Refuse to accept code with unhandled relocations
> >   clover: Report error when pipe driver fails to create compute state
> >   clover: Catch errors from executing event action
> > 
> > Jason Ekstrand (6):
> >   anv: Stop setting 3DSTATE_PS_EXTRA::PixelShaderHasUAV
> >   nir/serialize: Alloc constants off the variable
> >   blorp: Handle the RGB workaround more like other workarounds
> >   intel/blorp: Handle 3-component formats in clears
> >   intel/compiler: Account for built-in uniforms in analyze_ubo_ranges
> >   spirv: Fix a couple of image atomic load/store bugs
> > 
> > José Fonseca (1):
> >   gallium/tests: Don't ignore S3TC errors.
> > 
> > Karol Herbst (1):
> >   nir: fix printing of vec16 type
> > 
> > Lepton Wu (1):
> >   virgl: Fix flush in virgl_encoder_inline_write.
> > 
> > Lucas Stach (1):
> >   st/mesa: call resource_changed when binding a EGLImage to a texture
> > 
> > Mauro Rossi (2):
> >   radv: winsys/amdgpu: include missing pthread.h header
> >   android: util/disk_cache: fix building errors in gallium drivers
> > 
> > Michel Dänzer (1):
> >   gallium: Check pipe_screen::resource_changed before dereferencing it
> > 
> > Nanley Chery (3):
> >   i965: Make blt_pitch public
> >   i965/miptree: Drop an if case from retile_as_linear
> >   i965/miptree: Fix can_blit_slice()
> 
> Hi Dylan,
> 
> I noticed that the patch, "i965/miptree: Use the correct BLT pitch,"
> isn't included here. Without it, none of these patches change Mesa's
> behavior.
> 
> Since the "Fix can_blit_slice()" patch hasn't been reviewed yet, I'm
> fine with none of these patches going in.
> 
> -Nanley

Okay, I'll drop all of these for now then.

> 
> > 
> > Roland Scheidegger (1):
> >   draw: force draw pipeline if there's more than 65535 vertices
> > 
> > Samuel Iglesias Gonsálvez (1):
> >   anv: fix assert in anv_CmdBindDescriptorSets()
> > 
> > Samuel Pitoiset (3):
> >   radv: make sure to wait for CP DMA when needed
> >   radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9
> >   radv: fix a memleak for merged shaders on GFX9
> 
> 
> 
> > ___
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 


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Re: [Mesa-dev] [RFC][PATCH 3/5] CleanSpec.mk: Remove HOST_OUT_release

[John Stultz]

On Wed, Jul 25, 2018 at 1:06 PM, Dan Willemsen  wrote:
> On Wed, Jul 25, 2018 at 12:35 PM John Stultz  wrote:
>>
>> On Wed, Jul 25, 2018 at 5:36 AM, Emil Velikov  
>> wrote:
>> > On 25 July 2018 at 00:21, John Stultz  wrote:
>> >> From: Dan Willemsen 
>> >>
>> >> This is a forward port of a patch from the AOSP/master tree:
>> >> https://android.googlesource.com/platform/external/mesa3d/+/bd633f11de0c6ac1ed333a28344c74fd9898df9e%5E%21/
>> >>
>> >> Which replaces HOST_OUT_release with HOST_OUT
>> >>
>> > What's wrong with HOST_OUT_release? If it is something that got
>> > deprecated, we could:
>> >  a) add a comment above it (deprecated since Android ...)
>> >  b) add the HOST_OUT alongside the existing HOST_OUT_release
>>
>> Seems to be the case since:
>> https://android.googlesource.com/platform/build/+/d6ed368fde0609742540b5da6d2e8a2a19b2c0eb%5E%21/
>>
>> Dan/Alistair: Any objections to option b?
>
> You can't add side-by-side, since new lines must be added at the end of the
> file (the makefiles keep track of which lines were run by index, not their
> contents). But when that variable isn't set, it would try to remove
> "/*/EXECUTABLES/...
> You could do something like:
>
> ifdef HOST_OUT_release
> ...
> else
> ...
> endif
>
> But it was already incorrect to use $(HOST_OUT_release) here, $(HOST_OUT) will
> be set properly for whether the current build that's being cleaned during
> incrementals is using host debug or release builds (it was incredibly uncommon
> to use a debug host build, there was never a shortcut to use that, you had to
> set an environment variable manually, and it was rarely if ever tested).

Emil: Is this sufficient justification to drop HOST_OUT_release then?

> I'll also note that the Android.mk files are not guaranteed to be compatible
> between releases, even more so as we're switching away from Make.

To this point, this policy (and the switching from make to blueprints)
does create a bit of turmoil for external projects that want to
preserve compatibility with older Android releases. Particularly as
there doesn't seem to be an obvious way to support both makefiles and
blueprints in parallel.

Obviously at some point external projects need to move drop support
for older versions of Android, and options like having separate
branches for older-android support seems like a reasonable compromise
when there are major conflicts (upstreams don't want to break existing
users, but prioritizing keeping latest AOSP working with upstream
master branches seems most important to me, as it has a higher
potential for improving long term collaboration between the projects).

But as we are trying to get upstream projects to pick up changes that
make it easier to work with AOSP,  AOSP needs to take consideration
how to best work with upstream projects as well.

thanks
-john
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Re: [Mesa-dev] [ANNOUNCE] Mesa 18.1.5 Candidate

[Nanley Chery]

On Wed, Jul 25, 2018 at 11:47:59AM -0700, Dylan Baker wrote:
> Greetings,
> 
> Mesa the staging/18.1 branch is currently slushed for 18.1.5, and assuming 
> that
> there are no regressions or patches critically necessary this will be merged 
> to
> the 18.1 branch for a release Friday morning, July 27th around 10 AM PDT.
> 
> Currently the branch has the following changes since 18.1.4:
>  - 45 queued
>  - 0 nominated (outstanding)
>  - and 1 rejected patch
> 
> The one rejected patch was de-nominated by the author.
> 
> Note: there are 4 cherry-ignore patches, but 3 are for patches that required
> manual backport, and thus the cherry-picked from line does not match the 
> commit
> in master.
> 
> All merge conflicts that I resolved have already been verified by the original
> patch authors.
> 
> Dylan
> 
> Shortlog of changes:
> 
> Alex Smith (1):
>   anv: Pay attention to VK_ACCESS_MEMORY_(READ|WRITE)_BIT
> 
> Bas Nieuwenhuizen (7):
>   radv: Select correct entries for binning.
>   radv: Fix number of samples used for binning.
>   radv: Disable disabled color buffers in rbplus opts.
>   nir: Do not use continue block after removing it.
>   util/disk_cache: Fix disk_cache_get_function_timestamp with disabled 
> cache.
>   nir: Fix end of function without return warning/error.
>   radv: Still enable inmemory & API level caching if disk cache is not 
> enabled.
> 
> Chad Versace (2):
>   anv/android: Fix type error in call to vk_errorf()
>   anv/android: Fix Autotools build for VK_ANDROID_native_buffer
> 
> Chih-Wei Huang (1):
>   Android: fix a missing nir_intrinsics.h error
> 
> Danylo Piliaiev (1):
>   i965: Sweep NIR after linking phase to free held memory
> 
> Dave Airlie (1):
>   r600: enable tess_input_info for TES
> 
> Dylan Baker (5):
>   docs: Add sha256 sums for 18.1.4 tarballs
>   cherry-ignore: add 4a67ce886a7b3def5f66c1aedf9e5436d157a03c
>   cherry-ignore: Add 1f616a840eac02241c585d28e9dac8f19a297f39
>   cherry-ignore: add 11712b9ca17e4e1a819dcb7d020e19c6da77bc90
>   cherry-ignore: Add 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
> 
> Eric Anholt (2):
>   vc4: Don't automatically reallocate a PERSISTENT-mapped buffer.
>   meson: Move xvmc test tools from unit tests to installed tools.
> 
> Harish Krupo (1):
>   egl: Fix missing clamping in eglSetDamageRegionKHR
> 
> Jan Vesely (3):
>   radeonsi: Refuse to accept code with unhandled relocations
>   clover: Report error when pipe driver fails to create compute state
>   clover: Catch errors from executing event action
> 
> Jason Ekstrand (6):
>   anv: Stop setting 3DSTATE_PS_EXTRA::PixelShaderHasUAV
>   nir/serialize: Alloc constants off the variable
>   blorp: Handle the RGB workaround more like other workarounds
>   intel/blorp: Handle 3-component formats in clears
>   intel/compiler: Account for built-in uniforms in analyze_ubo_ranges
>   spirv: Fix a couple of image atomic load/store bugs
> 
> José Fonseca (1):
>   gallium/tests: Don't ignore S3TC errors.
> 
> Karol Herbst (1):
>   nir: fix printing of vec16 type
> 
> Lepton Wu (1):
>   virgl: Fix flush in virgl_encoder_inline_write.
> 
> Lucas Stach (1):
>   st/mesa: call resource_changed when binding a EGLImage to a texture
> 
> Mauro Rossi (2):
>   radv: winsys/amdgpu: include missing pthread.h header
>   android: util/disk_cache: fix building errors in gallium drivers
> 
> Michel Dänzer (1):
>   gallium: Check pipe_screen::resource_changed before dereferencing it
> 
> Nanley Chery (3):
>   i965: Make blt_pitch public
>   i965/miptree: Drop an if case from retile_as_linear
>   i965/miptree: Fix can_blit_slice()

Hi Dylan,

I noticed that the patch, "i965/miptree: Use the correct BLT pitch,"
isn't included here. Without it, none of these patches change Mesa's
behavior.

Since the "Fix can_blit_slice()" patch hasn't been reviewed yet, I'm
fine with none of these patches going in.

-Nanley

> 
> Roland Scheidegger (1):
>   draw: force draw pipeline if there's more than 65535 vertices
> 
> Samuel Iglesias Gonsálvez (1):
>   anv: fix assert in anv_CmdBindDescriptorSets()
> 
> Samuel Pitoiset (3):
>   radv: make sure to wait for CP DMA when needed
>   radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9
>   radv: fix a memleak for merged shaders on GFX9



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Re: [Mesa-dev] [RFC][PATCH 4/5] Android.mk: Add option to use vendor version of mesa

[John Stultz]

On Wed, Jul 25, 2018 at 6:50 AM, Rob Herring  wrote:
> On Tue, Jul 24, 2018 at 5:21 PM John Stultz  wrote:
>>
>> From: Yong Yao 
>>
>> This is a forward port of a patch from the AOSP/master branch:
>> https://android.googlesource.com/platform/external/mesa3d/+/b1e5fad1db4c1d51c7ae3a033b100a8429ae5415%5E%21/
>>
>> Which allows boards to provide their own custom copy of mesa.
>
> IMO, if AOSP wants/needs to have multiple forks of mesa, then they
> should carry this patch.

I'd turn this around and ask if there is any sense in having the
default mesa in AOSP be anything but (possibly a stable snapshot) of
the upstream mesa tree?

Obviously, shipping boards/devices will need their own device specific
hacks and patches until those go upstream, so this provides a
mechanism for that.

But if vendors can't easily test upstream mesa (hopefully updated with
their refined patches finally merged) with AOSP, that just creates an
extra barrier, and dis-incentivises folks from bothering to work with
upstream.

thanks
-john
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Re: [Mesa-dev] [PATCH mesa] anv: don't crash on vkDestroyDevice(NULL)

[Chema Casanova]

Reviewed-by: Jose Maria Casanova Crespo 

El 25/07/18 a las 21:25, Eric Engestrom escribió:
> On Wednesday, 2018-07-25 19:45:56 +0100, Eric Engestrom wrote:
>> CovID: 1438132
>> Signed-off-by: Eric Engestrom 
> 
> Forgot to check before sending:
> 
> Fixes: a99c9e63a07477634ab73 "anv: finish the binding_table_pool on
>   destroyDevice when use_softpin"
> Cc: Jose Maria Casanova Crespo 
> 
>> ---
>>  src/intel/vulkan/anv_device.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
>> index 04fd6a829ed60081abc4..3664f80c24dc34955196 100644
>> --- a/src/intel/vulkan/anv_device.c
>> +++ b/src/intel/vulkan/anv_device.c
>> @@ -1832,11 +1832,13 @@ void anv_DestroyDevice(
>>  const VkAllocationCallbacks*pAllocator)
>>  {
>> ANV_FROM_HANDLE(anv_device, device, _device);
>> -   struct anv_physical_device *physical_device = 
>> >instance->physicalDevice;
>> +   struct anv_physical_device *physical_device;
>>  
>> if (!device)
>>return;
>>  
>> +   physical_device = >instance->physicalDevice;>> 
>> anv_device_finish_blorp(device);
>>  
>> anv_pipeline_cache_finish(>default_pipeline_cache);
>> -- 
>> Cheers,
>>   Eric
>>
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Re: [Mesa-dev] [RFC][PATCH 4/5] Android.mk: Add option to use vendor version of mesa

[John Stultz]

On Wed, Jul 25, 2018 at 5:42 AM, Emil Velikov  wrote:
> On 25 July 2018 at 00:21, John Stultz  wrote:
>> From: Yong Yao 
>>
>> This is a forward port of a patch from the AOSP/master branch:
>> https://android.googlesource.com/platform/external/mesa3d/+/b1e5fad1db4c1d51c7ae3a033b100a8429ae5415%5E%21/
>>
>> Which allows boards to provide their own custom copy of mesa.
>>
> Thanks for sorting these out John.
>
> My understanding was that when a custom project repo is used one
> handles that in the device manifest. Roughly as:
>  - foo.xml -> contains vast majority of the git repos with associated tags/etc
>  - local.xml -> removes any repo/project from ^^, adds new one
>
> Is that no longer the case, or I simply misremember how Android does things?

So, I'm not aware of the specific history behind this patch. And I
can't speak for Google, there has been a general push via the Treble
efforts to standardize the Android system image, and to push vendors
to keep any device specific bits into their own device directory.  So
there is a strong disincentive to modify projects in AOSP and in order
to include things like devboards into AOSP, the push has been to limit
any device specific changes to only the device directory git tree.

So while one can technically still replace projects with local repos
(and this is very useful for development!), I think they do not want
folks doing this for shipping devices.

We are trying to make sure device support is pushed upstream to fdo,
and then align AOSP's mesa to that, but one could imagine a board that
doesn't have support upstream in mesa, and provides its own copy of
mesa in the device directory. This patch allows the build to override
the default mesa project with the vendor provided mesa.

One concrete example here, which unfortunately I've not had time to
work on, might be if we try to integrate the revived lima work to
support HiKey's mali utgard gpu. That would require a local mesa tree
along with the developmental kernel driver.

thanks
-john
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[Mesa-dev] [Bug 107369] "volatile" in OpenCL code not recognized by POLARIS10 and KABINI

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107369

--- Comment #3 from Gian-Carlo Pascutto  ---
You can see in my original comment that there are passes with LLVM 6.0.0 and
failures for LLVM 6.0.1. So indeed, it can't be LLVM either.

I'm not sure if it's possible for libclc to be different between those, but it
looks like it must be?

I asked one of the people suffering from this bug if he could provide the
requested output. The affected distro appears to be Debian, so maybe we're
looking at the version of this: https://packages.debian.org/sid/libclc-amdgcn

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Re: [Mesa-dev] [RFC][PATCH 3/5] CleanSpec.mk: Remove HOST_OUT_release

[John Stultz]

On Wed, Jul 25, 2018 at 5:36 AM, Emil Velikov  wrote:
> On 25 July 2018 at 00:21, John Stultz  wrote:
>> From: Dan Willemsen 
>>
>> This is a forward port of a patch from the AOSP/master tree:
>> https://android.googlesource.com/platform/external/mesa3d/+/bd633f11de0c6ac1ed333a28344c74fd9898df9e%5E%21/
>>
>> Which replaces HOST_OUT_release with HOST_OUT
>>
> What's wrong with HOST_OUT_release? If it is something that got
> deprecated, we could:
>  a) add a comment above it (deprecated since Android ...)
>  b) add the HOST_OUT alongside the existing HOST_OUT_release

Seems to be the case since:
https://android.googlesource.com/platform/build/+/d6ed368fde0609742540b5da6d2e8a2a19b2c0eb%5E%21/

Dan/Alistair: Any objections to option b?

thanks
-john
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[Mesa-dev] [Bug 107369] "volatile" in OpenCL code not recognized by POLARIS10 and KABINI

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107369

--- Comment #2 from Aaron Watry  ---
My home system has an RX580 (Polaris10).

I just cloned/built CLBlast and it appears to be running ./clblast_tuner_xgemm
(mentioned as the specific failing case in
https://github.com/CNugteren/CLBlast/issues/298) successfully, so I don't know
that the issue is polaris10 specific.

In my case, I've got Mesa 18.2.0-b21b38c46cd61d9 (latest upstream as of the
last hour or so), libclc r335280 (latest revision since late June), and llvm
7.0.0-svn as of r337934 (a few minutes ago).

I did notice that the LLVM version for both failing cases is different than the
passing ones, so I went and downgraded to llvm 6.0.1... but it still works.

w/ LLVM 6.0.1 (first section of 578 tests):
  Found best result 1.43 ms: 1505.0 GFLOPS

w/ LLVM 7.0.0svn:
  Found best result 1.50 ms: 1428.2 GFLOPS

I'd agree with Jan that a dump of the dumped llvm bitcode would be useful.
Also, it may be interesting to try to upgrade libclc or mesa to the latest
upstream code to see if one of those has an effect.

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Re: [Mesa-dev] [RFC][PATCH 2/5] Android.common.mk: define HAVE_TIMESPEC_GET

[John Stultz]

On Wed, Jul 25, 2018 at 5:34 AM, Emil Velikov  wrote:
> On 25 July 2018 at 00:21, John Stultz  wrote:
>> From: Sumit Semwal 
>>
>> This is a forward port of a patch from the AOSP/master tree:
>> https://android.googlesource.com/platform/external/mesa3d/+/bd30b663f55f8af73a0be4446349c5a2d4c641b0%5E%21/
>>
>> Since https://android-review.googlesource.com/c/718518 added
>> timespec_get() to bionic, mesa3d doesn't build due to redefinition
>> of timespec_get().
>>
> Is this bionic commit available all the way back to Android 5?
> If not, you should conditionally add the define where needed - see
> Android.mk for examples.

Ack. Just added that. Thanks for the review/feedback!
-john
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Re: [Mesa-dev] [PATCH] i965: Expose ARB_base_instance extension

[Ilia Mirkin]

Presumably EXT_base_instance (or OES_? I forget, definitely not ARB though)

On Wed, Jul 25, 2018 at 3:24 PM, Jordan Justen
 wrote:
> I think the subject should include gles3:
>
> i965: Expose ARB_base_instance extension in OpenGL ES 3.0
>
> Reviewed-by: Jordan Justen 
>
> On 2018-07-25 10:48:31, Sagar Ghuge wrote:
>> The extension requires at least OpenGL 3.0 and
>> OpenGL ES 3.0.
>>
>> Fixes two ext_base_instance tests:
>>
>> arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3
>> arb_base_instance-drawarrays_gles3
>>
>> Signed-off-by: Sagar Ghuge 
>> ---
>>  src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
>> b/src/mesa/drivers/dri/i965/intel_extensions.c
>> index f837356478..9d119d0b4c 100644
>> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
>> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
>> @@ -315,7 +315,7 @@ intelInitExtensions(struct gl_context *ctx)
>> if (devinfo->gen >= 6)
>>ctx->Extensions.INTEL_performance_query = true;
>>
>> -   if (ctx->API == API_OPENGL_CORE)
>> +   if (ctx->API != API_OPENGL_COMPAT)
>>ctx->Extensions.ARB_base_instance = true;
>> if (ctx->API != API_OPENGL_CORE)
>>ctx->Extensions.ARB_color_buffer_float = true;
>> --
>> 2.17.1
>>
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Re: [Mesa-dev] [PATCH mesa] anv: don't crash on vkDestroyDevice(NULL)

[Eric Engestrom]

On Wednesday, 2018-07-25 19:45:56 +0100, Eric Engestrom wrote:
> CovID: 1438132
> Signed-off-by: Eric Engestrom 

Forgot to check before sending:

Fixes: a99c9e63a07477634ab73 "anv: finish the binding_table_pool on
  destroyDevice when use_softpin"
Cc: Jose Maria Casanova Crespo 

> ---
>  src/intel/vulkan/anv_device.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
> index 04fd6a829ed60081abc4..3664f80c24dc34955196 100644
> --- a/src/intel/vulkan/anv_device.c
> +++ b/src/intel/vulkan/anv_device.c
> @@ -1832,11 +1832,13 @@ void anv_DestroyDevice(
>  const VkAllocationCallbacks*pAllocator)
>  {
> ANV_FROM_HANDLE(anv_device, device, _device);
> -   struct anv_physical_device *physical_device = 
> >instance->physicalDevice;
> +   struct anv_physical_device *physical_device;
>  
> if (!device)
>return;
>  
> +   physical_device = >instance->physicalDevice;
> +
> anv_device_finish_blorp(device);
>  
> anv_pipeline_cache_finish(>default_pipeline_cache);
> -- 
> Cheers,
>   Eric
> 
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Re: [Mesa-dev] [PATCH] i965: Expose ARB_base_instance extension

[Jordan Justen]

I think the subject should include gles3:

i965: Expose ARB_base_instance extension in OpenGL ES 3.0

Reviewed-by: Jordan Justen 

On 2018-07-25 10:48:31, Sagar Ghuge wrote:
> The extension requires at least OpenGL 3.0 and
> OpenGL ES 3.0.
> 
> Fixes two ext_base_instance tests:
> 
> arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3
> arb_base_instance-drawarrays_gles3
> 
> Signed-off-by: Sagar Ghuge 
> ---
>  src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index f837356478..9d119d0b4c 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -315,7 +315,7 @@ intelInitExtensions(struct gl_context *ctx)
> if (devinfo->gen >= 6)
>ctx->Extensions.INTEL_performance_query = true;
>  
> -   if (ctx->API == API_OPENGL_CORE)
> +   if (ctx->API != API_OPENGL_COMPAT)
>ctx->Extensions.ARB_base_instance = true;
> if (ctx->API != API_OPENGL_CORE)
>ctx->Extensions.ARB_color_buffer_float = true;
> -- 
> 2.17.1
> 
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Re: [Mesa-dev] [PATCH mesa v2] vulkan/wsi: fix assignment in assert()

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Wed, Jul 25, 2018 at 12:04 PM Eric Engestrom 
wrote:

> CovID: 1438113, 1438118, 1438119, 1438121
> Fixes: dc1d10b396179766227df "anv,radv: Add support for
> VK_KHR_get_display_properties2"
> Cc: Jason Ekstrand 
> Signed-off-by: Eric Engestrom 
> ---
>  src/vulkan/wsi/wsi_common_display.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/vulkan/wsi/wsi_common_display.c
> b/src/vulkan/wsi/wsi_common_display.c
> index ac932d4368a0293fe97e..e6cba188dfaf8d790415 100644
> --- a/src/vulkan/wsi/wsi_common_display.c
> +++ b/src/vulkan/wsi/wsi_common_display.c
> @@ -619,7 +619,7 @@ wsi_display_fill_in_display_mode_properties(
> struct wsi_display_mode *display_mode,
> VkDisplayModeProperties2KHR *properties)
>  {
> -   assert(properties->sType =
> VK_STRUCTURE_TYPE_DISPLAY_MODE_PROPERTIES_2_KHR);
> +   assert(properties->sType ==
> VK_STRUCTURE_TYPE_DISPLAY_MODE_PROPERTIES_2_KHR);
> VkDisplayModePropertiesKHR *prop = >displayModeProperties;
>
> prop->displayMode = wsi_display_mode_to_handle(display_mode);
> @@ -763,7 +763,7 @@ wsi_get_display_plane_capabilities2(
> const VkDisplayPlaneInfo2KHR *pDisplayPlaneInfo,
> VkDisplayPlaneCapabilities2KHR *capabilities)
>  {
> -   assert(capabilities->sType =
> +   assert(capabilities->sType ==
>VK_STRUCTURE_TYPE_DISPLAY_PLANE_CAPABILITIES_2_KHR);
>
> return wsi_get_display_plane_capabilities(physical_device, wsi_device,
> --
> Cheers,
>   Eric
>
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[Mesa-dev] [PATCH mesa] docs: trivial html fix

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 docs/releasing.html | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/docs/releasing.html b/docs/releasing.html
index a022d0c484bc0f635b61..69d8656e59d567033087 100644
--- a/docs/releasing.html
+++ b/docs/releasing.html
@@ -492,10 +492,10 @@ Perform basic testing
# Drop LLVM_CONFIG, if applicable:
# unset LLVM_CONFIG
 
-   __glxinfo_cmd='glxinfo 2>1 | egrep -o "Mesa.*|Gallium.*|.*dri\.so"'
-   __glxgears_cmd='glxgears 2>1 | grep -v "configuration file"'
-   __es2info_cmd='es2_info 2>1 | egrep 
"GL_VERSION|GL_RENDERER|.*dri\.so"'
-   __es2gears_cmd='es2gears_x11 2>1 | grep -v "configuration file"'
+   __glxinfo_cmd='glxinfo 21 | egrep -o 
"Mesa.*|Gallium.*|.*dri\.so"'
+   __glxgears_cmd='glxgears 21 | grep -v "configuration file"'
+   __es2info_cmd='es2_info 21 | egrep 
"GL_VERSION|GL_RENDERER|.*dri\.so"'
+   __es2gears_cmd='es2gears_x11 21 | grep -v "configuration file"'
test "x$LD_LIBRARY_PATH" != 'x'  __old_ld="$LD_LIBRARY_PATH"
export LD_LIBRARY_PATH=`pwd`/test/usr/local/lib/:"${__old_ld}"
export LIBGL_DRIVERS_PATH=`pwd`/test/usr/local/lib/dri/
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 2/3] anv: cleanup python imports

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/intel/vulkan/anv_entrypoints_gen.py | 3 +--
 src/intel/vulkan/anv_icd.py | 3 ++-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index db35069850160f105e94..a37643ef62a62ec99a9c 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -23,7 +23,6 @@
 #
 
 import argparse
-import functools
 import math
 import os
 import xml.etree.cElementTree as et
@@ -31,7 +30,7 @@
 from collections import OrderedDict, namedtuple
 from mako.template import Template
 
-from anv_extensions import *
+from anv_extensions import VkVersion, MAX_API_VERSION, EXTENSIONS
 
 # We generate a static hash table for entry point lookup
 # (vkGetProcAddress). We use a linear congruential generator for our hash
diff --git a/src/intel/vulkan/anv_icd.py b/src/intel/vulkan/anv_icd.py
index 36c2882f7d634de18752..fafec34f677e4572 100644
--- a/src/intel/vulkan/anv_icd.py
+++ b/src/intel/vulkan/anv_icd.py
@@ -22,8 +22,9 @@
 
 import json
 import os.path
+import argparse
 
-from anv_extensions import *
+from anv_extensions import MAX_API_VERSION
 
 if __name__ == '__main__':
 parser = argparse.ArgumentParser()
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 3/3] anv: fix python whitespace warning

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/intel/vulkan/anv_icd.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_icd.py b/src/intel/vulkan/anv_icd.py
index fafec34f677e4572..73cc6453d51d0fbc2eec 100644
--- a/src/intel/vulkan/anv_icd.py
+++ b/src/intel/vulkan/anv_icd.py
@@ -45,4 +45,4 @@
 }
 
 with open(args.out, 'w') as f:
-json.dump(json_data, f, indent = 4, sort_keys=True, separators=(',', 
': '))
+json.dump(json_data, f, indent=4, sort_keys=True, separators=(',', ': 
'))
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa 1/3] anv: remove unnecessary semicolons in python

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/intel/vulkan/anv_extensions.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/anv_extensions.py 
b/src/intel/vulkan/anv_extensions.py
index ea837744b4352845b0d5..cffc3e700cb0ccb7fa8f 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -31,11 +31,11 @@
 
 def _bool_to_c_expr(b):
 if b is True:
-return 'true';
+return 'true'
 elif b is False:
-return 'false';
+return 'false'
 else:
-return b;
+return b
 
 class Extension:
 def __init__(self, name, ext_version, enable):
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] anv: drop unused local vars

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/intel/vulkan/anv_descriptor_set.c | 6 --
 1 file changed, 6 deletions(-)

diff --git a/src/intel/vulkan/anv_descriptor_set.c 
b/src/intel/vulkan/anv_descriptor_set.c
index 8f7f1f3ba386de438887..66ed28292b01897fc1d1 100644
--- a/src/intel/vulkan/anv_descriptor_set.c
+++ b/src/intel/vulkan/anv_descriptor_set.c
@@ -902,15 +902,9 @@ anv_descriptor_set_write_template(struct 
anv_descriptor_set *set,
   const struct anv_descriptor_update_template 
*template,
   const void *data)
 {
-   const struct anv_descriptor_set_layout *layout = set->layout;
-
for (uint32_t i = 0; i < template->entry_count; i++) {
   const struct anv_descriptor_template_entry *entry =
  >entries[i];
-  const struct anv_descriptor_set_binding_layout *bind_layout =
- >binding[entry->binding];
-  struct anv_descriptor *desc = 
>descriptors[bind_layout->descriptor_index];
-  desc += entry->array_element;
 
   switch (entry->type) {
   case VK_DESCRIPTOR_TYPE_SAMPLER:
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] anv: remove incorrect `UNUSED` flag

[Eric Engestrom]

Signed-off-by: Eric Engestrom 
---
 src/intel/vulkan/anv_image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 5d9becf51723b8a4ca47..36d4ac13c75d8a22e7ee 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -303,7 +303,7 @@ make_surface(const struct anv_device *dev,
  VkImageAspectFlagBits aspect)
 {
const VkImageCreateInfo *vk_info = anv_info->vk_info;
-   bool ok UNUSED;
+   bool ok;
 
static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
   [VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa v2] vulkan/wsi: fix assignment in assert()

[Eric Engestrom]

CovID: 1438113, 1438118, 1438119, 1438121
Fixes: dc1d10b396179766227df "anv,radv: Add support for 
VK_KHR_get_display_properties2"
Cc: Jason Ekstrand 
Signed-off-by: Eric Engestrom 
---
 src/vulkan/wsi/wsi_common_display.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index ac932d4368a0293fe97e..e6cba188dfaf8d790415 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -619,7 +619,7 @@ wsi_display_fill_in_display_mode_properties(
struct wsi_display_mode *display_mode,
VkDisplayModeProperties2KHR *properties)
 {
-   assert(properties->sType = VK_STRUCTURE_TYPE_DISPLAY_MODE_PROPERTIES_2_KHR);
+   assert(properties->sType == 
VK_STRUCTURE_TYPE_DISPLAY_MODE_PROPERTIES_2_KHR);
VkDisplayModePropertiesKHR *prop = >displayModeProperties;
 
prop->displayMode = wsi_display_mode_to_handle(display_mode);
@@ -763,7 +763,7 @@ wsi_get_display_plane_capabilities2(
const VkDisplayPlaneInfo2KHR *pDisplayPlaneInfo,
VkDisplayPlaneCapabilities2KHR *capabilities)
 {
-   assert(capabilities->sType =
+   assert(capabilities->sType ==
   VK_STRUCTURE_TYPE_DISPLAY_PLANE_CAPABILITIES_2_KHR);
 
return wsi_get_display_plane_capabilities(physical_device, wsi_device,
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH mesa] vulkan/wsi: fix assignment in assert()

[Eric Engestrom]

CovID: 1438121
Fixes: dc1d10b396179766227df "anv,radv: Add support for 
VK_KHR_get_display_properties2"
Cc: Jason Ekstrand 
Signed-off-by: Eric Engestrom 
---
 src/vulkan/wsi/wsi_common_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/vulkan/wsi/wsi_common_display.c 
b/src/vulkan/wsi/wsi_common_display.c
index ac932d4368a0293fe97e..7cabb7780db29c8a44d7 100644
--- a/src/vulkan/wsi/wsi_common_display.c
+++ b/src/vulkan/wsi/wsi_common_display.c
@@ -763,7 +763,7 @@ wsi_get_display_plane_capabilities2(
const VkDisplayPlaneInfo2KHR *pDisplayPlaneInfo,
VkDisplayPlaneCapabilities2KHR *capabilities)
 {
-   assert(capabilities->sType =
+   assert(capabilities->sType ==
   VK_STRUCTURE_TYPE_DISPLAY_PLANE_CAPABILITIES_2_KHR);
 
return wsi_get_display_plane_capabilities(physical_device, wsi_device,
-- 
Cheers,
  Eric

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[Mesa-dev] [ANNOUNCE] Mesa 18.1.5 Candidate

[Dylan Baker]

Greetings,

Mesa the staging/18.1 branch is currently slushed for 18.1.5, and assuming that
there are no regressions or patches critically necessary this will be merged to
the 18.1 branch for a release Friday morning, July 27th around 10 AM PDT.

Currently the branch has the following changes since 18.1.4:
 - 45 queued
 - 0 nominated (outstanding)
 - and 1 rejected patch

The one rejected patch was de-nominated by the author.

Note: there are 4 cherry-ignore patches, but 3 are for patches that required
manual backport, and thus the cherry-picked from line does not match the commit
in master.

All merge conflicts that I resolved have already been verified by the original
patch authors.

Dylan

Shortlog of changes:

Alex Smith (1):
  anv: Pay attention to VK_ACCESS_MEMORY_(READ|WRITE)_BIT

Bas Nieuwenhuizen (7):
  radv: Select correct entries for binning.
  radv: Fix number of samples used for binning.
  radv: Disable disabled color buffers in rbplus opts.
  nir: Do not use continue block after removing it.
  util/disk_cache: Fix disk_cache_get_function_timestamp with disabled 
cache.
  nir: Fix end of function without return warning/error.
  radv: Still enable inmemory & API level caching if disk cache is not 
enabled.

Chad Versace (2):
  anv/android: Fix type error in call to vk_errorf()
  anv/android: Fix Autotools build for VK_ANDROID_native_buffer

Chih-Wei Huang (1):
  Android: fix a missing nir_intrinsics.h error

Danylo Piliaiev (1):
  i965: Sweep NIR after linking phase to free held memory

Dave Airlie (1):
  r600: enable tess_input_info for TES

Dylan Baker (5):
  docs: Add sha256 sums for 18.1.4 tarballs
  cherry-ignore: add 4a67ce886a7b3def5f66c1aedf9e5436d157a03c
  cherry-ignore: Add 1f616a840eac02241c585d28e9dac8f19a297f39
  cherry-ignore: add 11712b9ca17e4e1a819dcb7d020e19c6da77bc90
  cherry-ignore: Add 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3

Eric Anholt (2):
  vc4: Don't automatically reallocate a PERSISTENT-mapped buffer.
  meson: Move xvmc test tools from unit tests to installed tools.

Harish Krupo (1):
  egl: Fix missing clamping in eglSetDamageRegionKHR

Jan Vesely (3):
  radeonsi: Refuse to accept code with unhandled relocations
  clover: Report error when pipe driver fails to create compute state
  clover: Catch errors from executing event action

Jason Ekstrand (6):
  anv: Stop setting 3DSTATE_PS_EXTRA::PixelShaderHasUAV
  nir/serialize: Alloc constants off the variable
  blorp: Handle the RGB workaround more like other workarounds
  intel/blorp: Handle 3-component formats in clears
  intel/compiler: Account for built-in uniforms in analyze_ubo_ranges
  spirv: Fix a couple of image atomic load/store bugs

José Fonseca (1):
  gallium/tests: Don't ignore S3TC errors.

Karol Herbst (1):
  nir: fix printing of vec16 type

Lepton Wu (1):
  virgl: Fix flush in virgl_encoder_inline_write.

Lucas Stach (1):
  st/mesa: call resource_changed when binding a EGLImage to a texture

Mauro Rossi (2):
  radv: winsys/amdgpu: include missing pthread.h header
  android: util/disk_cache: fix building errors in gallium drivers

Michel Dänzer (1):
  gallium: Check pipe_screen::resource_changed before dereferencing it

Nanley Chery (3):
  i965: Make blt_pitch public
  i965/miptree: Drop an if case from retile_as_linear
  i965/miptree: Fix can_blit_slice()

Roland Scheidegger (1):
  draw: force draw pipeline if there's more than 65535 vertices

Samuel Iglesias Gonsálvez (1):
  anv: fix assert in anv_CmdBindDescriptorSets()

Samuel Pitoiset (3):
  radv: make sure to wait for CP DMA when needed
  radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9
  radv: fix a memleak for merged shaders on GFX9


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[Mesa-dev] [PATCH mesa] anv: don't crash on vkDestroyDevice(NULL)

[Eric Engestrom]

CovID: 1438132
Signed-off-by: Eric Engestrom 
---
 src/intel/vulkan/anv_device.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 04fd6a829ed60081abc4..3664f80c24dc34955196 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1832,11 +1832,13 @@ void anv_DestroyDevice(
 const VkAllocationCallbacks*pAllocator)
 {
ANV_FROM_HANDLE(anv_device, device, _device);
-   struct anv_physical_device *physical_device = 
>instance->physicalDevice;
+   struct anv_physical_device *physical_device;
 
if (!device)
   return;
 
+   physical_device = >instance->physicalDevice;
+
anv_device_finish_blorp(device);
 
anv_pipeline_cache_finish(>default_pipeline_cache);
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH] i965: Expose ARB_base_instance extension

[Sagar Ghuge]

The extension requires at least OpenGL 3.0 and
OpenGL ES 3.0.

Fixes two ext_base_instance tests:

arb_base_instance-baseinstance-doesnt-affect-gl-instance-id_gles3
arb_base_instance-drawarrays_gles3

Signed-off-by: Sagar Ghuge 
---
 src/mesa/drivers/dri/i965/intel_extensions.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index f837356478..9d119d0b4c 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -315,7 +315,7 @@ intelInitExtensions(struct gl_context *ctx)
if (devinfo->gen >= 6)
   ctx->Extensions.INTEL_performance_query = true;
 
-   if (ctx->API == API_OPENGL_CORE)
+   if (ctx->API != API_OPENGL_COMPAT)
   ctx->Extensions.ARB_base_instance = true;
if (ctx->API != API_OPENGL_CORE)
   ctx->Extensions.ARB_color_buffer_float = true;
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] dri3: Do not get supported modifiers on pixmaps

[Eric Anholt]

Olivier Fourdan  writes:

> get_supported_modifiers() expects a window as drawable, passing a pixmap
> will fail as the Xserver will fail to match the id to a window.
>
> That leads to dri3_alloc_render_buffer() to return NULL and breaks
> rendering when using GLX_DOUBLEBUFFER.
>
> Check if dealing with pixmap in dri3_alloc_render_buffer() in which case
> avoid using get_supported_modifiers() and fallback to the good old
> pixmap_from_buffer() method as before.

It seems like we should ask for the modifiers on the root window in that
case, and use something good from the screen_modifiers list.


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Re: [Mesa-dev] [PATCH] gallium: initialize ureg_dst::Invariant bit

[Emil Velikov]

On 25 July 2018 at 16:28, Erik Faye-Lund  wrote:
> When this bit was added, it seems the some initialization code
> was omitted by mistake.
>
> Since stack-variables have kinda random contents, and we don't
> zero initialize the whole struct in these code-paths, we end up
> getting random-ish values for this bit.
>
As a follow-up it'll be a good idea to zero init. the whole stack
variable, removing duplicate zero assignments.
Shorter code, while avoiding similar bugs in the future.

> Fixes: 70425bcfe63c4e9191809659d019ec4af923595d ("gallium: plumb
> invariant output attrib thru TGSI")
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH v2] clover: Reduce wait_count in abort path.

[Aaron Watry]

I can confirm that all 28 CTS 'events' tests pass now on my BARTS
(6850) instead of hanging after an intentionally failing event.

I'll let Francisco give his say to whether it looks correct, but for
this version you can have:

Tested-By: Aaron Watry 

--Aaron



On Tue, Jul 24, 2018 at 10:28 PM, Jan Vesely  wrote:
> Trigger waiter condition variable.
> Passes 'events' CTS on carrizo and turks.
> v2: reduce to 0
>
> Signed-off-by: Jan Vesely 
> ---
>  src/gallium/state_trackers/clover/core/event.cpp | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/state_trackers/clover/core/event.cpp 
> b/src/gallium/state_trackers/clover/core/event.cpp
> index b7eb33dbfc..3d313ce896 100644
> --- a/src/gallium/state_trackers/clover/core/event.cpp
> +++ b/src/gallium/state_trackers/clover/core/event.cpp
> @@ -41,7 +41,7 @@ event::trigger_self() {
> std::lock_guard lock(mutex);
> std::vector> evs;
>
> -   if (!--_wait_count)
> +   if (_wait_count && !--_wait_count)
>std::swap(_chain, evs);
>
> cv.notify_all();
> @@ -65,8 +65,10 @@ event::abort_self(cl_int status) {
> std::vector> evs;
>
> _status = status;
> +   _wait_count = 0;
> std::swap(_chain, evs);
>
> +   cv.notify_all();
> return evs;
>  }
>
> --
> 2.17.1
>
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Re: [Mesa-dev] [Mesa-stable] [PATCH] intel/compiler: Account for built-in uniforms in analyze_ubo_ranges

[Dylan Baker]

Quoting Jason Ekstrand (2018-07-25 09:38:15)
> On Wed, Jul 25, 2018 at 9:30 AM Dylan Baker  wrote:
> 
> Quoting Jason Ekstrand (2018-07-24 16:51:26)
> > On July 24, 2018 09:05:05 Dylan Baker  wrote:
> >
> > > Quoting Jason Ekstrand (2018-07-23 10:46:31)
> > >> The original pass only looked for load_uniform intrinsics but there
> are
> > >> a number of other places that could end up loading a push constant. 
> One
> > >> obvious omission was images which always implicitly use a push
> constant.
> > >> Legacy VS clip planes also get pushed into the shader.
> > >>
> > >> Cc: mesa-sta...@lists.freedesktop.org
> > >> Cc: Kenneth Graunke 
> > >> ---
> > >> src/intel/compiler/brw_nir.h                  |  1 +
> > >> .../compiler/brw_nir_analyze_ubo_ranges.c     | 41 
> +--
> > >> src/intel/vulkan/anv_pipeline.c               |  2 +-
> > >> src/mesa/drivers/dri/i965/brw_gs.c            |  2 +-
> > >> src/mesa/drivers/dri/i965/brw_tcs.c           |  2 +-
> > >> src/mesa/drivers/dri/i965/brw_tes.c           |  2 +-
> > >> src/mesa/drivers/dri/i965/brw_vs.c            |  2 +-
> > >> src/mesa/drivers/dri/i965/brw_wm.c            |  2 +-
> > >> 8 files changed, 45 insertions(+), 9 deletions(-)
> > >>
> > >> diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/
> brw_nir.h
> > >> index 19442b47eae..7d82edafe46 100644
> > >> --- a/src/intel/compiler/brw_nir.h
> > >> +++ b/src/intel/compiler/brw_nir.h
> > >> @@ -148,6 +148,7 @@ void
> > >> brw_nir_lower_patch_vertices_in_to_uniform(nir_shader *nir);
> > >>
> > >> void brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
> > >>                         nir_shader *nir,
> > >> +                                const struct brw_vs_prog_key 
> *vs_key,
> > >>                         struct brw_ubo_range out_ranges[4]);
> > >>
> > >> bool brw_nir_opt_peephole_ffma(nir_shader *shader);
> > >> diff --git a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> > >> b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> > >> index cd5137da06e..cfa531675fc 100644
> > >> --- a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> > >> +++ b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> > >> @@ -124,12 +124,29 @@ analyze_ubos_block(struct ubo_analysis_state
> *state,
> > >> nir_block *block)
> > >>  continue;
> > >>
> > >> nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
> > >> -      if (intrin->intrinsic == nir_intrinsic_load_uniform)
> > >> +      switch (intrin->intrinsic) {
> > >> +      case nir_intrinsic_load_uniform:
> > >> +      case nir_intrinsic_image_deref_load:
> > >> +      case nir_intrinsic_image_deref_store:
> > >> +      case nir_intrinsic_image_deref_atomic_add:
> > >> +      case nir_intrinsic_image_deref_atomic_min:
> > >> +      case nir_intrinsic_image_deref_atomic_max:
> > >> +      case nir_intrinsic_image_deref_atomic_and:
> > >> +      case nir_intrinsic_image_deref_atomic_or:
> > >> +      case nir_intrinsic_image_deref_atomic_xor:
> > >> +      case nir_intrinsic_image_deref_atomic_exchange:
> > >> +      case nir_intrinsic_image_deref_atomic_comp_swap:
> > >> +      case nir_intrinsic_image_deref_size:
> > >>  state->uses_regular_uniforms = true;
> > >> -
> > >> -      if (intrin->intrinsic != nir_intrinsic_load_ubo)
> > >>  continue;
> > >>
> > >> +      case nir_intrinsic_load_ubo:
> > >> +         break; /* Fall through to the analysis below */
> > >> +
> > >> +      default:
> > >> +         continue; /* Not a uniform or UBO intrinsic */
> > >> +      }
> > >> +
> > >> nir_const_value *block_const = 
> nir_src_as_const_value(intrin->src[0]);
> > >> nir_const_value *offset_const = nir_src_as_const_value(intrin->src
> [1]);
> > >>
> > >> @@ -179,6 +196,7 @@ print_ubo_entry(FILE *file,
> > >> void
> > >> brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
> > >>                    nir_shader *nir,
> > >> +                           const struct brw_vs_prog_key *vs_key,
> > >>                    struct brw_ubo_range out_ranges[4])
> > >> {
> > >> const struct gen_device_info *devinfo = compiler->devinfo;
> > >> @@ -197,6 +215,23 @@ brw_nir_analyze_ubo_ranges(const struct
> brw_compiler
> > >> *compiler,
> > >>  _mesa_hash_table_create(mem_ctx, NULL, _mesa_key_pointer_equal),
> > >> };
> > >>
> > >> +   switch (nir->info.stage) {
> > >> +   case MESA_SHADER_VERTEX:
> > >> +      if (vs_key && vs_key->nr_userclip_plane_consts > 0)
> > >> +         state.uses_regular_uniforms = true;
> > >> +      break;
> > >> +
> > >> +   case MESA_SHADER_COMPUTE:
> > >> +      /* Compute shaders use push constants to 

Re: [Mesa-dev] [Mesa-stable] [PATCH] intel/compiler: Account for built-in uniforms in analyze_ubo_ranges

[Jason Ekstrand]

On Wed, Jul 25, 2018 at 9:30 AM Dylan Baker  wrote:

> Quoting Jason Ekstrand (2018-07-24 16:51:26)
> > On July 24, 2018 09:05:05 Dylan Baker  wrote:
> >
> > > Quoting Jason Ekstrand (2018-07-23 10:46:31)
> > >> The original pass only looked for load_uniform intrinsics but there
> are
> > >> a number of other places that could end up loading a push constant.
> One
> > >> obvious omission was images which always implicitly use a push
> constant.
> > >> Legacy VS clip planes also get pushed into the shader.
> > >>
> > >> Cc: mesa-sta...@lists.freedesktop.org
> > >> Cc: Kenneth Graunke 
> > >> ---
> > >> src/intel/compiler/brw_nir.h  |  1 +
> > >> .../compiler/brw_nir_analyze_ubo_ranges.c | 41 +--
> > >> src/intel/vulkan/anv_pipeline.c   |  2 +-
> > >> src/mesa/drivers/dri/i965/brw_gs.c|  2 +-
> > >> src/mesa/drivers/dri/i965/brw_tcs.c   |  2 +-
> > >> src/mesa/drivers/dri/i965/brw_tes.c   |  2 +-
> > >> src/mesa/drivers/dri/i965/brw_vs.c|  2 +-
> > >> src/mesa/drivers/dri/i965/brw_wm.c|  2 +-
> > >> 8 files changed, 45 insertions(+), 9 deletions(-)
> > >>
> > >> diff --git a/src/intel/compiler/brw_nir.h
> b/src/intel/compiler/brw_nir.h
> > >> index 19442b47eae..7d82edafe46 100644
> > >> --- a/src/intel/compiler/brw_nir.h
> > >> +++ b/src/intel/compiler/brw_nir.h
> > >> @@ -148,6 +148,7 @@ void
> > >> brw_nir_lower_patch_vertices_in_to_uniform(nir_shader *nir);
> > >>
> > >> void brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
> > >> nir_shader *nir,
> > >> +const struct brw_vs_prog_key *vs_key,
> > >> struct brw_ubo_range out_ranges[4]);
> > >>
> > >> bool brw_nir_opt_peephole_ffma(nir_shader *shader);
> > >> diff --git a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> > >> b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> > >> index cd5137da06e..cfa531675fc 100644
> > >> --- a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> > >> +++ b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> > >> @@ -124,12 +124,29 @@ analyze_ubos_block(struct ubo_analysis_state
> *state,
> > >> nir_block *block)
> > >>  continue;
> > >>
> > >> nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
> > >> -  if (intrin->intrinsic == nir_intrinsic_load_uniform)
> > >> +  switch (intrin->intrinsic) {
> > >> +  case nir_intrinsic_load_uniform:
> > >> +  case nir_intrinsic_image_deref_load:
> > >> +  case nir_intrinsic_image_deref_store:
> > >> +  case nir_intrinsic_image_deref_atomic_add:
> > >> +  case nir_intrinsic_image_deref_atomic_min:
> > >> +  case nir_intrinsic_image_deref_atomic_max:
> > >> +  case nir_intrinsic_image_deref_atomic_and:
> > >> +  case nir_intrinsic_image_deref_atomic_or:
> > >> +  case nir_intrinsic_image_deref_atomic_xor:
> > >> +  case nir_intrinsic_image_deref_atomic_exchange:
> > >> +  case nir_intrinsic_image_deref_atomic_comp_swap:
> > >> +  case nir_intrinsic_image_deref_size:
> > >>  state->uses_regular_uniforms = true;
> > >> -
> > >> -  if (intrin->intrinsic != nir_intrinsic_load_ubo)
> > >>  continue;
> > >>
> > >> +  case nir_intrinsic_load_ubo:
> > >> + break; /* Fall through to the analysis below */
> > >> +
> > >> +  default:
> > >> + continue; /* Not a uniform or UBO intrinsic */
> > >> +  }
> > >> +
> > >> nir_const_value *block_const = nir_src_as_const_value(intrin->src[0]);
> > >> nir_const_value *offset_const =
> nir_src_as_const_value(intrin->src[1]);
> > >>
> > >> @@ -179,6 +196,7 @@ print_ubo_entry(FILE *file,
> > >> void
> > >> brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
> > >>nir_shader *nir,
> > >> +   const struct brw_vs_prog_key *vs_key,
> > >>struct brw_ubo_range out_ranges[4])
> > >> {
> > >> const struct gen_device_info *devinfo = compiler->devinfo;
> > >> @@ -197,6 +215,23 @@ brw_nir_analyze_ubo_ranges(const struct
> brw_compiler
> > >> *compiler,
> > >>  _mesa_hash_table_create(mem_ctx, NULL, _mesa_key_pointer_equal),
> > >> };
> > >>
> > >> +   switch (nir->info.stage) {
> > >> +   case MESA_SHADER_VERTEX:
> > >> +  if (vs_key && vs_key->nr_userclip_plane_consts > 0)
> > >> + state.uses_regular_uniforms = true;
> > >> +  break;
> > >> +
> > >> +   case MESA_SHADER_COMPUTE:
> > >> +  /* Compute shaders use push constants to get the subgroup ID
> so it's
> > >> +   * best to just assume some system values are pushed.
> > >> +   */
> > >> +  state.uses_regular_uniforms = true;
> > >> +  break;
> > >> +
> > >> +   default:
> > >> +  break;
> > >> +   }
> > >> +
> > >> /* Walk the IR, recording how many times each UBO block/offset is
> used. */
> > >> nir_foreach_function(function, nir) {
> > >> if (function->impl) {
> > >> diff --git a/src/intel/vulkan/anv_pipeline.c

Re: [Mesa-dev] [Mesa-stable] [PATCH] intel/compiler: Account for built-in uniforms in analyze_ubo_ranges

[Dylan Baker]

Quoting Jason Ekstrand (2018-07-24 16:51:26)
> On July 24, 2018 09:05:05 Dylan Baker  wrote:
> 
> > Quoting Jason Ekstrand (2018-07-23 10:46:31)
> >> The original pass only looked for load_uniform intrinsics but there are
> >> a number of other places that could end up loading a push constant.  One
> >> obvious omission was images which always implicitly use a push constant.
> >> Legacy VS clip planes also get pushed into the shader.
> >>
> >> Cc: mesa-sta...@lists.freedesktop.org
> >> Cc: Kenneth Graunke 
> >> ---
> >> src/intel/compiler/brw_nir.h  |  1 +
> >> .../compiler/brw_nir_analyze_ubo_ranges.c | 41 +--
> >> src/intel/vulkan/anv_pipeline.c   |  2 +-
> >> src/mesa/drivers/dri/i965/brw_gs.c|  2 +-
> >> src/mesa/drivers/dri/i965/brw_tcs.c   |  2 +-
> >> src/mesa/drivers/dri/i965/brw_tes.c   |  2 +-
> >> src/mesa/drivers/dri/i965/brw_vs.c|  2 +-
> >> src/mesa/drivers/dri/i965/brw_wm.c|  2 +-
> >> 8 files changed, 45 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h
> >> index 19442b47eae..7d82edafe46 100644
> >> --- a/src/intel/compiler/brw_nir.h
> >> +++ b/src/intel/compiler/brw_nir.h
> >> @@ -148,6 +148,7 @@ void 
> >> brw_nir_lower_patch_vertices_in_to_uniform(nir_shader *nir);
> >>
> >> void brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
> >> nir_shader *nir,
> >> +const struct brw_vs_prog_key *vs_key,
> >> struct brw_ubo_range out_ranges[4]);
> >>
> >> bool brw_nir_opt_peephole_ffma(nir_shader *shader);
> >> diff --git a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c 
> >> b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> >> index cd5137da06e..cfa531675fc 100644
> >> --- a/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> >> +++ b/src/intel/compiler/brw_nir_analyze_ubo_ranges.c
> >> @@ -124,12 +124,29 @@ analyze_ubos_block(struct ubo_analysis_state *state, 
> >> nir_block *block)
> >>  continue;
> >>
> >> nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
> >> -  if (intrin->intrinsic == nir_intrinsic_load_uniform)
> >> +  switch (intrin->intrinsic) {
> >> +  case nir_intrinsic_load_uniform:
> >> +  case nir_intrinsic_image_deref_load:
> >> +  case nir_intrinsic_image_deref_store:
> >> +  case nir_intrinsic_image_deref_atomic_add:
> >> +  case nir_intrinsic_image_deref_atomic_min:
> >> +  case nir_intrinsic_image_deref_atomic_max:
> >> +  case nir_intrinsic_image_deref_atomic_and:
> >> +  case nir_intrinsic_image_deref_atomic_or:
> >> +  case nir_intrinsic_image_deref_atomic_xor:
> >> +  case nir_intrinsic_image_deref_atomic_exchange:
> >> +  case nir_intrinsic_image_deref_atomic_comp_swap:
> >> +  case nir_intrinsic_image_deref_size:
> >>  state->uses_regular_uniforms = true;
> >> -
> >> -  if (intrin->intrinsic != nir_intrinsic_load_ubo)
> >>  continue;
> >>
> >> +  case nir_intrinsic_load_ubo:
> >> + break; /* Fall through to the analysis below */
> >> +
> >> +  default:
> >> + continue; /* Not a uniform or UBO intrinsic */
> >> +  }
> >> +
> >> nir_const_value *block_const = nir_src_as_const_value(intrin->src[0]);
> >> nir_const_value *offset_const = nir_src_as_const_value(intrin->src[1]);
> >>
> >> @@ -179,6 +196,7 @@ print_ubo_entry(FILE *file,
> >> void
> >> brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
> >>nir_shader *nir,
> >> +   const struct brw_vs_prog_key *vs_key,
> >>struct brw_ubo_range out_ranges[4])
> >> {
> >> const struct gen_device_info *devinfo = compiler->devinfo;
> >> @@ -197,6 +215,23 @@ brw_nir_analyze_ubo_ranges(const struct brw_compiler 
> >> *compiler,
> >>  _mesa_hash_table_create(mem_ctx, NULL, _mesa_key_pointer_equal),
> >> };
> >>
> >> +   switch (nir->info.stage) {
> >> +   case MESA_SHADER_VERTEX:
> >> +  if (vs_key && vs_key->nr_userclip_plane_consts > 0)
> >> + state.uses_regular_uniforms = true;
> >> +  break;
> >> +
> >> +   case MESA_SHADER_COMPUTE:
> >> +  /* Compute shaders use push constants to get the subgroup ID so it's
> >> +   * best to just assume some system values are pushed.
> >> +   */
> >> +  state.uses_regular_uniforms = true;
> >> +  break;
> >> +
> >> +   default:
> >> +  break;
> >> +   }
> >> +
> >> /* Walk the IR, recording how many times each UBO block/offset is used. */
> >> nir_foreach_function(function, nir) {
> >> if (function->impl) {
> >> diff --git a/src/intel/vulkan/anv_pipeline.c 
> >> b/src/intel/vulkan/anv_pipeline.c
> >> index 211cee788b8..1e6bd12b87d 100644
> >> --- a/src/intel/vulkan/anv_pipeline.c
> >> +++ b/src/intel/vulkan/anv_pipeline.c
> >> @@ -472,7 +472,7 @@ anv_pipeline_compile(struct anv_pipeline *pipeline,
> >> 

Re: [Mesa-dev] [Mesa-stable] [PATCH] gallium/tests: Don't ignore S3TC errors.

[Dylan Baker]

Quoting Emil Velikov (2018-07-24 09:52:13)
> On 24 July 2018 at 13:58, Jose Fonseca  wrote:
> > Now we do full S3TC decompression they should no longer fail.
> > ---
> >  src/gallium/tests/unit/u_format_test.c | 5 -
> >  1 file changed, 5 deletions(-)
> >
> > diff --git a/src/gallium/tests/unit/u_format_test.c 
> > b/src/gallium/tests/unit/u_format_test.c
> > index 6de581fd049..437cc94b757 100644
> > --- a/src/gallium/tests/unit/u_format_test.c
> > +++ b/src/gallium/tests/unit/u_format_test.c
> > @@ -380,11 +380,6 @@ test_format_unpack_rgba_8unorm(const struct 
> > util_format_description *format_desc
> > if (util_is_double_nan(test->unpacked[0][0][0]))
> >success = TRUE;
> >
> > -   /* Ignore S3TC errors */
> > -   if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
> > -  success = TRUE;
> > -   }
> > -
> We normally want this in stable as well. The following provide a rough
> relation to the commit effectively enabling the built-in S3TC.
> Feel free to add it
> 
> Fixes: 34cf3c43bee ("mesa: Call DXTn functions directly")
> 
> -Emil

I've pulled this into the staging/18.1 branch.

Dylan


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Re: [Mesa-dev] [PATCH v2] intel: Make the decoder handle STATE_BASE_ADDRESS not being a buffer.

[Lionel Landwerlin]

Hey Ken,

Looks all good to me.

Just one suggestion which I think might matter in your prototype :

The handle_state_base_address() function tries to get BOs when the 
instruction is parsed.
But as you seem to imply those base addresses might not be backed by 
actual buffers.

I would turn the gen_batch_decode_bo in gen_batch_decode_ctx into uint64_t.
We always seem to use bo.addr but not the map, so no need to bother 
getting those.


With or without that changed :

Reviewed-by: Lionel Landwerlin 

Thanks!

On 24/07/18 22:55, Kenneth Graunke wrote:

Normally, i965 programs STATE_BASE_ADDRESS every batch, and puts all
state for a given base in a single buffer.

I'm working on a prototype which emits STATE_BASE_ADDRESS only once at
startup, where each base address is a fixed 4GB region of the PPGTT.
State may live in many buffers in that 4GB region, even if there isn't
a buffer located at the actual base address itself.

To handle this, we need to save the STATE_BASE_ADDRESS values across
multiple batches, rather than assuming we'll see the command each time.
Then, each time we see a pointer, we need to ask the driver for the BO
map for that data.  (We can't just use the map for the base address, as
state may be in multiple buffers, and there may not even be a buffer
at the base address to map.)

v2: Fix things caught in review by Lionel:
  - Drop bogus bind_bo.size check.
  - Drop "get the BOs again" code - we just get the BOs as needed
  - Add a message about interface descriptor data being unavailable
---
  src/intel/common/gen_batch_decoder.c | 75 +++-
  src/intel/common/gen_decoder.h   |  9 +++-
  2 files changed, 46 insertions(+), 38 deletions(-)

diff --git a/src/intel/common/gen_batch_decoder.c 
b/src/intel/common/gen_batch_decoder.c
index 727cbb80cfb..c6967ebc053 100644
--- a/src/intel/common/gen_batch_decoder.c
+++ b/src/intel/common/gen_batch_decoder.c
@@ -128,13 +128,13 @@ static void
  ctx_disassemble_program(struct gen_batch_decode_ctx *ctx,
  uint32_t ksp, const char *type)
  {
-   if (!ctx->instruction_base.map)
+   uint64_t addr = ctx->instruction_base.addr + ksp;
+   struct gen_batch_decode_bo bo = ctx_get_bo(ctx, addr);
+   if (!bo.map)
return;
  
-   printf("\nReferenced %s:\n", type);

-   gen_disasm_disassemble(ctx->disasm,
-  (void *)ctx->instruction_base.map, ksp,
-  ctx->fp);
+   fprintf(ctx->fp, "\nReferenced %s:\n", type);
+   gen_disasm_disassemble(ctx->disasm, bo.map, 0, ctx->fp);
  }
  
  /* Heuristic to determine whether a uint32_t is probably actually a float

@@ -225,35 +225,30 @@ dump_binding_table(struct gen_batch_decode_ctx *ctx, 
uint32_t offset, int count)
 if (count < 0)
count = update_count(ctx, offset, 1, 8);
  
-   if (ctx->surface_base.map == NULL) {

-  fprintf(ctx->fp, "  binding table unavailable\n");
+   if (offset % 32 != 0 || offset >= UINT16_MAX) {
+  fprintf(ctx->fp, "  invalid binding table pointer\n");
return;
 }
  
-   if (offset % 32 != 0 || offset >= UINT16_MAX ||

-   offset >= ctx->surface_base.size) {
-  fprintf(ctx->fp, "  invalid binding table pointer\n");
+   struct gen_batch_decode_bo bind_bo =
+  ctx_get_bo(ctx, ctx->surface_base.addr + offset);
+
+   if (bind_bo.map == NULL) {
+  fprintf(ctx->fp, "  binding table unavailable\n");
return;
 }
  
-   struct gen_batch_decode_bo bo = ctx->surface_base;

-   const uint32_t *pointers = ctx->surface_base.map + offset;
+   const uint32_t *pointers = bind_bo.map;
 for (int i = 0; i < count; i++) {
if (pointers[i] == 0)
   continue;
  
-  if (pointers[i] % 32 != 0) {

- fprintf(ctx->fp, "pointer %u: %08x \n", i, pointers[i]);
- continue;
-  }
-
uint64_t addr = ctx->surface_base.addr + pointers[i];
+  struct gen_batch_decode_bo bo = ctx_get_bo(ctx, addr);
uint32_t size = strct->dw_length * 4;
  
-  if (addr < bo.addr || addr + size >= bo.addr + bo.size)

- bo = ctx->get_bo(ctx->user_data, addr);
-
-  if (addr < bo.addr || addr + size >= bo.addr + bo.size) {
+  if (pointers[i] % 32 != 0 ||
+  addr < bo.addr || addr + size >= bo.addr + bo.size) {
   fprintf(ctx->fp, "pointer %u: %08x \n", i, pointers[i]);
   continue;
}
@@ -271,18 +266,20 @@ dump_samplers(struct gen_batch_decode_ctx *ctx, uint32_t 
offset, int count)
 if (count < 0)
count = update_count(ctx, offset, strct->dw_length, 4);
  
-   if (ctx->dynamic_base.map == NULL) {

+   uint64_t state_addr = ctx->dynamic_base.addr + offset;
+   struct gen_batch_decode_bo bo = ctx_get_bo(ctx, state_addr);
+   const void *state_map = bo.map;
+
+   if (state_map == NULL) {
fprintf(ctx->fp, "  samplers unavailable\n");
return;
 }
  
-   if (offset % 32 != 0 || offset >= ctx->dynamic_base.size) {

+   if (offset % 32 != 0 || state_addr - bo.addr >= 

Re: [Mesa-dev] [PATCH] nir: remove wrong assertion in print_var_decl()

[Bas Nieuwenhuizen]

On Wed, Jul 25, 2018 at 3:38 PM, Samuel Pitoiset
 wrote:
>
>
> On 07/25/2018 03:28 PM, Bas Nieuwenhuizen wrote:
>>
>> On Wed, Jul 25, 2018 at 2:30 PM, Samuel Pitoiset
>>  wrote:
>>>
>>> This breaks printing input/output variables with more than
>>> 4 components like mat4.
>>>
>>> Fixes: 1beef89ad8 ("nir: prepare for bumping up max components to 16")
>>> Signed-off-by: Samuel Pitoiset 
>>> ---
>>>   src/compiler/nir/nir_print.c | 1 -
>>>   1 file changed, 1 deletion(-)
>>>
>>> diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
>>> index 93d1c02f23..7cb16abd14 100644
>>> --- a/src/compiler/nir/nir_print.c
>>> +++ b/src/compiler/nir/nir_print.c
>>> @@ -491,7 +491,6 @@ print_var_decl(nir_variable *var, print_state *state)
>>> switch (var->data.mode) {
>>> case nir_var_shader_in:
>>> case nir_var_shader_out:
>>> - assert(num_components <= 4);
>>>if (num_components < 4 && num_components != 0) {
>>>   const char *xyzw = "xyzw";
>>
>>
>> won't you go out of bounds on this array/string if num_components > 4?
>
>
> What? The above condition already prevents that?
True, I'm blind apparently.

Reviewed-by: Bas Nieuwenhuizen 

>
>
>>>   for (int i = 0; i < num_components; i++)
>>> --
>>> 2.18.0
>>>
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>>> mesa-dev@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [PATCH] gallium: initialize ureg_dst::Invariant bit

[Erik Faye-Lund]

When this bit was added, it seems the some initialization code
was omitted by mistake.

Since stack-variables have kinda random contents, and we don't
zero initialize the whole struct in these code-paths, we end up
getting random-ish values for this bit.

Spotted by Coverity in the following CIDs:
- 1438115
- 1438123
- 1438130

Fixes: 70425bcfe63c4e9191809659d019ec4af923595d ("gallium: plumb
invariant output attrib thru TGSI")
---
 src/gallium/auxiliary/tgsi/tgsi_ureg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.h 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
index 4d4a954529..c974ed0206 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
@@ -1019,6 +1019,7 @@ ureg_dst_array_register(unsigned file,
dst.DimIndIndex = 0;
dst.DimIndSwizzle = 0;
dst.ArrayID = array_id;
+   dst.Invariant = 0;
 
return dst;
 }
@@ -1050,6 +1051,7 @@ ureg_dst( struct ureg_src src )
dst.DimIndIndex = src.DimIndIndex;
dst.DimIndSwizzle = src.DimIndSwizzle;
dst.ArrayID = src.ArrayID;
+   dst.Invariant = 0;
 
return dst;
 }
@@ -1141,6 +1143,7 @@ ureg_dst_undef( void )
dst.DimIndIndex = 0;
dst.DimIndSwizzle = 0;
dst.ArrayID = 0;
+   dst.Invariant = 0;
 
return dst;
 }
-- 
2.18.0

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[Mesa-dev] [Bug 107369] "volatile" in OpenCL code not recognized by POLARIS10 and KABINI

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=107369

Jan Vesely  changed:

   What|Removed |Added

 Blocks||99553

--- Comment #1 from Jan Vesely  ---
mesa/clover does not touch the clc code. that is processed by clang/llvm.
can you run with CLOVER_DEBUG=llvm,native CLOVER_DEBUG_FILE=dump-file and post
the files?


Referenced Bugs:

https://bugs.freedesktop.org/show_bug.cgi?id=99553
[Bug 99553] Tracker bug for runnning OpenCL applications on Clover
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[Mesa-dev] [PATCH] dri3: Do not get supported modifiers on pixmaps

[Olivier Fourdan]

get_supported_modifiers() expects a window as drawable, passing a pixmap
will fail as the Xserver will fail to match the id to a window.

That leads to dri3_alloc_render_buffer() to return NULL and breaks
rendering when using GLX_DOUBLEBUFFER.

Check if dealing with pixmap in dri3_alloc_render_buffer() in which case
avoid using get_supported_modifiers() and fallback to the good old
pixmap_from_buffer() method as before.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107117
Fixes: 069fdd5 ("egl/x11: Support DRI3 v1.1")
Signed-off-by: Olivier Fourdan 
---
 src/loader/loader_dri3_helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/loader/loader_dri3_helper.c b/src/loader/loader_dri3_helper.c
index f0ff2f07bd..83b7c66a44 100644
--- a/src/loader/loader_dri3_helper.c
+++ b/src/loader/loader_dri3_helper.c
@@ -1139,6 +1139,7 @@ dri3_alloc_render_buffer(struct loader_dri3_drawable 
*draw, unsigned int format,
if (!draw->is_different_gpu) {
 #ifdef HAVE_DRI3_MODIFIERS
   if (draw->multiplanes_available &&
+  !draw->is_pixmap &&
   draw->ext->image->base.version >= 15 &&
   draw->ext->image->queryDmaBufModifiers &&
   draw->ext->image->createImageWithModifiers) {
@@ -1278,6 +1279,7 @@ dri3_alloc_render_buffer(struct loader_dri3_drawable 
*draw, unsigned int format,
pixmap = xcb_generate_id(draw->conn);
 #ifdef HAVE_DRI3_MODIFIERS
if (draw->multiplanes_available &&
+   !draw->is_pixmap &&
buffer->modifier != DRM_FORMAT_MOD_INVALID) {
   xcb_dri3_pixmap_from_buffers(draw->conn,
pixmap,
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] nvc0: serialize before updating some constant buffer bindings

[Ilia Mirkin]

On Wed, Jul 25, 2018 at 9:13 AM, Rhys Perry  wrote:
> To avoid serializing, this has the user constant buffer always be 65536
> bytes and enabled unless it's required that something else is used for
> constant buffer 0.
>
> Fixes artifacts with at least XCOM: Enemy Within, 0 A.D. and Unigine
> Valley, Heaven and Superposition.
>
> v2: changed uniform_buffer_bound to be bool instead of a uint32_t
>
> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=100177
> Signed-off-by: Rhys Perry 
> ---
>  src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 13 +++---
>  src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 46 
> +++---
>  src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 13 +-
>  .../drivers/nouveau/nvc0/nvc0_state_validate.c | 40 +--
>  4 files changed, 76 insertions(+), 36 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c 
> b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
> index 11635c9465..578bf11d70 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
> @@ -181,7 +181,7 @@ nvc0_compute_invalidate_constbufs(struct nvc0_context 
> *nvc0)
> /* Invalidate all 3D constbufs because they are aliased with COMPUTE. */
> for (s = 0; s < 5; s++) {
>nvc0->constbuf_dirty[s] |= nvc0->constbuf_valid[s];
> -  nvc0->state.uniform_buffer_bound[s] = 0;
> +  nvc0->state.uniform_buffer_bound[s] = false;
> }
> nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
>  }
> @@ -203,19 +203,18 @@ nvc0_compute_validate_constbufs(struct nvc0_context 
> *nvc0)
>   assert(i == 0); /* we really only want OpenGL uniforms here */
>   assert(nvc0->constbuf[s][0].u.data);
>
> - if (nvc0->state.uniform_buffer_bound[s] < size) {
> -nvc0->state.uniform_buffer_bound[s] = align(size, 0x100);
> + if (!nvc0->state.uniform_buffer_bound[s]) {

Above:

   const int s = 5;

That won't end well. Bump the allocation to 6?

> +nvc0->state.uniform_buffer_bound[s] = true;
>
>  BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
> -PUSH_DATA (push, nvc0->state.uniform_buffer_bound[s]);
> +PUSH_DATA (push, 65536);

Please add a #define NVC0_MAX_CONSTBUF_SIZE 65536 and usage thereof
instead of the magic constant, and use here and below.

>  PUSH_DATAh(push, bo->offset + base);
>  PUSH_DATA (push, bo->offset + base);
>  BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
>  PUSH_DATA (push, (0 << 8) | 1);
>   }
>   nvc0_cb_bo_push(>base, bo, 
> NV_VRAM_DOMAIN(>screen->base),
> - base, nvc0->state.uniform_buffer_bound[s],
> - 0, (size + 3) / 4,
> + base, 65536, 0, (size + 3) / 4,
>   nvc0->constbuf[s][0].u.data);
>} else {
>   struct nv04_resource *res =
> @@ -236,7 +235,7 @@ nvc0_compute_validate_constbufs(struct nvc0_context *nvc0)
>  PUSH_DATA (push, (i << 8) | 0);
>   }
>   if (i == 0)
> -nvc0->state.uniform_buffer_bound[s] = 0;
> +nvc0->state.uniform_buffer_bound[s] = false;
>}
> }
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index 37e10dcd07..197b0c1911 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -829,6 +829,40 @@ nvc0_screen_resize_text_area(struct nvc0_screen *screen, 
> uint64_t size)
> return 0;
>  }
>
> +void
> +nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
> +   int stage, int index, int size, uint64_t addr)
> +{
> +   assert(stage != 5);
> +
> +   struct nouveau_pushbuf *push = screen->base.pushbuf;
> +
> +   if (screen->base.class_3d >= GM107_3D_CLASS) {
> +  struct nvc0_cb_binding *binding = >cb_bindings[stage][index];
> +
> +  // TODO: Better figure out the conditions in which this is needed
> +  bool serialize = binding->addr == addr && binding->size != size;
> +  if (can_serialize)
> + serialize = serialize && *can_serialize;
> +  if (serialize) {
> + IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
> + if (can_serialize)
> +*can_serialize = false;
> +  }
> +
> +  binding->addr = addr;
> +  binding->size = size;
> +   }
> +
> +   if (size >= 0) {
> +  BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
> +  PUSH_DATA (push, size);
> +  PUSH_DATAh(push, addr);
> +  PUSH_DATA (push, addr);
> +   }
> +   IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
> +}
> +
>  #define FAIL_SCREEN_INIT(str, err)\
> do {   \
>NOUVEAU_ERR(str, err);  \
> @@ -1272,14 +1306,14 @@ nvc0_screen_create(struct nouveau_device 

[Mesa-dev] [Bug 106411] Invalid gl_InstanceID value with combination of gl_DrawIDARB under OpenGL

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106411

--- Comment #2 from Alexander  ---
I'm still on Ubuntu 16.04 and the latest available Mesa version is 18.0.5 (from
x-swat). I have main_instance_draw.png without dependency on gl_VertexID. With
artificial dependency rendering is correct (main_instance_draw_vertex.png). I
will try to upgrade Mesa on 18.1.* branch in few days.

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Re: [Mesa-dev] [RFC][PATCH 4/5] Android.mk: Add option to use vendor version of mesa

[Rob Herring]

On Tue, Jul 24, 2018 at 5:21 PM John Stultz  wrote:
>
> From: Yong Yao 
>
> This is a forward port of a patch from the AOSP/master branch:
> https://android.googlesource.com/platform/external/mesa3d/+/b1e5fad1db4c1d51c7ae3a033b100a8429ae5415%5E%21/
>
> Which allows boards to provide their own custom copy of mesa.

IMO, if AOSP wants/needs to have multiple forks of mesa, then they
should carry this patch.

Rob
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Re: [Mesa-dev] [PATCH] nir: remove wrong assertion in print_var_decl()

[Samuel Pitoiset]

On 07/25/2018 03:28 PM, Bas Nieuwenhuizen wrote:

On Wed, Jul 25, 2018 at 2:30 PM, Samuel Pitoiset
 wrote:

This breaks printing input/output variables with more than
4 components like mat4.

Fixes: 1beef89ad8 ("nir: prepare for bumping up max components to 16")
Signed-off-by: Samuel Pitoiset 
---
  src/compiler/nir/nir_print.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index 93d1c02f23..7cb16abd14 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -491,7 +491,6 @@ print_var_decl(nir_variable *var, print_state *state)
switch (var->data.mode) {
case nir_var_shader_in:
case nir_var_shader_out:
- assert(num_components <= 4);
   if (num_components < 4 && num_components != 0) {
  const char *xyzw = "xyzw";


won't you go out of bounds on this array/string if num_components > 4?


What? The above condition already prevents that?


  for (int i = 0; i < num_components; i++)
--
2.18.0

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Re: [Mesa-dev] [PATCH] radv: fix adjusting vertex fetches since 16bit support

[Bas Nieuwenhuizen]

On Wed, Jul 25, 2018 at 3:28 PM, Samuel Pitoiset
 wrote:
>
>
> On 07/25/2018 03:26 PM, Bas Nieuwenhuizen wrote:
>>
>> On Wed, Jul 25, 2018 at 3:25 PM, Samuel Pitoiset
>>  wrote:
>>>
>>>
>>>
>>> On 07/25/2018 02:55 PM, Bas Nieuwenhuizen wrote:


 hmm, not sure why that did not fail on my CTS runs ...
>>>
>>>
>>>
>>> Because 16bit is only enabled on Polaris?
>>
>> Wait what, it should be enabled on Vega too right?
>
>
> It should but it's broken currently. Daniel will fix it later.
hmm?

Also the integer conversion should still kick in on vega right? Your
failed test is not a 16-bit test.

>
>
>>
>>>
>>>

 Reviewed-by: Bas Nieuwenhuizen 

 On Wed, Jul 25, 2018 at 2:55 PM, Samuel Pitoiset
  wrote:
>
>
> Move the integer conversion after the fixup.
>
> This fixes some regressions with
> dEQP-VK.pipeline.vertex_input.single_attribute.mat4.as_a2r10g10b10*
>
> Fixes: b722b29f10 ("radv: add support for 16bit input/output")
> Signed-off-by: Samuel Pitoiset 
> ---
>src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
>1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index 9f9dc0d4fe..64b6522cd9 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -2030,15 +2030,16 @@ handle_vs_input_decl(struct radv_shader_context
> *ctx,
>   output[chan] =
> LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
>   output[chan] =
> LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
>   }
> -   output[chan] = ac_to_integer(>ac,
> output[chan]);
> -   if (type == GLSL_TYPE_UINT16 || type ==
> GLSL_TYPE_INT16)
> -   output[chan] =
> LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
>   }
>
>   unsigned alpha_adjust =
> (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
>   output[3] = adjust_vertex_fetch_alpha(ctx,
> alpha_adjust,
> output[3]);
>
>   for (unsigned chan = 0; chan < 4; chan++) {
> +   output[chan] = ac_to_integer(>ac,
> output[chan]);
> +   if (type == GLSL_TYPE_UINT16 || type ==
> GLSL_TYPE_INT16)
> +   output[chan] =
> LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
> +
>
> ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] =
> output[chan];
>   }
>   }
> --
> 2.18.0
>
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Re: [Mesa-dev] [PATCH] nir: remove wrong assertion in print_var_decl()

[Bas Nieuwenhuizen]

On Wed, Jul 25, 2018 at 2:30 PM, Samuel Pitoiset
 wrote:
> This breaks printing input/output variables with more than
> 4 components like mat4.
>
> Fixes: 1beef89ad8 ("nir: prepare for bumping up max components to 16")
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/compiler/nir/nir_print.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
> index 93d1c02f23..7cb16abd14 100644
> --- a/src/compiler/nir/nir_print.c
> +++ b/src/compiler/nir/nir_print.c
> @@ -491,7 +491,6 @@ print_var_decl(nir_variable *var, print_state *state)
>switch (var->data.mode) {
>case nir_var_shader_in:
>case nir_var_shader_out:
> - assert(num_components <= 4);
>   if (num_components < 4 && num_components != 0) {
>  const char *xyzw = "xyzw";

won't you go out of bounds on this array/string if num_components > 4?
>  for (int i = 0; i < num_components; i++)
> --
> 2.18.0
>
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Re: [Mesa-dev] [PATCH] radv: fix adjusting vertex fetches since 16bit support

[Samuel Pitoiset]

On 07/25/2018 03:26 PM, Bas Nieuwenhuizen wrote:

On Wed, Jul 25, 2018 at 3:25 PM, Samuel Pitoiset
 wrote:



On 07/25/2018 02:55 PM, Bas Nieuwenhuizen wrote:


hmm, not sure why that did not fail on my CTS runs ...



Because 16bit is only enabled on Polaris?

Wait what, it should be enabled on Vega too right?


It should but it's broken currently. Daniel will fix it later.








Reviewed-by: Bas Nieuwenhuizen 

On Wed, Jul 25, 2018 at 2:55 PM, Samuel Pitoiset
 wrote:


Move the integer conversion after the fixup.

This fixes some regressions with
dEQP-VK.pipeline.vertex_input.single_attribute.mat4.as_a2r10g10b10*

Fixes: b722b29f10 ("radv: add support for 16bit input/output")
Signed-off-by: Samuel Pitoiset 
---
   src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
   1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 9f9dc0d4fe..64b6522cd9 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2030,15 +2030,16 @@ handle_vs_input_decl(struct radv_shader_context
*ctx,
  output[chan] =
LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
  output[chan] =
LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
  }
-   output[chan] = ac_to_integer(>ac,
output[chan]);
-   if (type == GLSL_TYPE_UINT16 || type ==
GLSL_TYPE_INT16)
-   output[chan] =
LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
  }

  unsigned alpha_adjust =
(ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
  output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust,
output[3]);

  for (unsigned chan = 0; chan < 4; chan++) {
+   output[chan] = ac_to_integer(>ac,
output[chan]);
+   if (type == GLSL_TYPE_UINT16 || type ==
GLSL_TYPE_INT16)
+   output[chan] =
LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
+

ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] =
output[chan];
  }
  }
--
2.18.0

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Re: [Mesa-dev] [PATCH] radv: fix adjusting vertex fetches since 16bit support

[Bas Nieuwenhuizen]

On Wed, Jul 25, 2018 at 3:25 PM, Samuel Pitoiset
 wrote:
>
>
> On 07/25/2018 02:55 PM, Bas Nieuwenhuizen wrote:
>>
>> hmm, not sure why that did not fail on my CTS runs ...
>
>
> Because 16bit is only enabled on Polaris?
Wait what, it should be enabled on Vega too right?

>
>
>>
>> Reviewed-by: Bas Nieuwenhuizen 
>>
>> On Wed, Jul 25, 2018 at 2:55 PM, Samuel Pitoiset
>>  wrote:
>>>
>>> Move the integer conversion after the fixup.
>>>
>>> This fixes some regressions with
>>> dEQP-VK.pipeline.vertex_input.single_attribute.mat4.as_a2r10g10b10*
>>>
>>> Fixes: b722b29f10 ("radv: add support for 16bit input/output")
>>> Signed-off-by: Samuel Pitoiset 
>>> ---
>>>   src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
>>>   1 file changed, 4 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
>>> b/src/amd/vulkan/radv_nir_to_llvm.c
>>> index 9f9dc0d4fe..64b6522cd9 100644
>>> --- a/src/amd/vulkan/radv_nir_to_llvm.c
>>> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
>>> @@ -2030,15 +2030,16 @@ handle_vs_input_decl(struct radv_shader_context
>>> *ctx,
>>>  output[chan] =
>>> LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
>>>  output[chan] =
>>> LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
>>>  }
>>> -   output[chan] = ac_to_integer(>ac,
>>> output[chan]);
>>> -   if (type == GLSL_TYPE_UINT16 || type ==
>>> GLSL_TYPE_INT16)
>>> -   output[chan] =
>>> LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
>>>  }
>>>
>>>  unsigned alpha_adjust =
>>> (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
>>>  output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust,
>>> output[3]);
>>>
>>>  for (unsigned chan = 0; chan < 4; chan++) {
>>> +   output[chan] = ac_to_integer(>ac,
>>> output[chan]);
>>> +   if (type == GLSL_TYPE_UINT16 || type ==
>>> GLSL_TYPE_INT16)
>>> +   output[chan] =
>>> LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
>>> +
>>>
>>> ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] =
>>> output[chan];
>>>  }
>>>  }
>>> --
>>> 2.18.0
>>>
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Re: [Mesa-dev] [PATCH v3] intel/ppgtt: memory address alignment

[Sergii Romantsov]

Sorry,
do we have any objections about PAGE_SIZE usage instead of 4096?

And what do you think if, maybe, some auto Intel-internal tests to run with
that patch?


On Wed, Jul 25, 2018 at 1:21 PM, Sergii Romantsov <
sergii.romant...@gmail.com> wrote:

> Kernel (for ppgtt) requires memory address to be
> aligned to page size (4096).
>
> -v2: added marking that also fixes initial commit 01058a552294.
> -v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
> instead of alignment of offsets (Chris Wilson).
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
> Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT
> systems.)
> Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to
> brw_bufmgr.)
> Signed-off-by: Sergii Romantsov 
> ---
>  src/mesa/drivers/dri/i965/brw_bufmgr.c | 19 +--
>  1 file changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> index 09d45e3..66d7751 100644
> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> @@ -195,7 +195,7 @@ bo_tile_size(struct brw_bufmgr *bufmgr, uint64_t size,
> uint32_t tiling)
>return size;
>
> /* 965+ just need multiples of page size for tiling */
> -   return ALIGN(size, 4096);
> +   return ALIGN(size, PAGE_SIZE);
>  }
>
>  /*
> @@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
>uint32_t stride)
>  {
> struct brw_bo *bo;
> -   unsigned int page_size = getpagesize();
> int ret;
> struct bo_cache_bucket *bucket;
> bool alloc_from_cache;
> @@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
>  * allocation up.
>  */
> if (bucket == NULL) {
> -  bo_size = size;
> -  if (bo_size < page_size)
> - bo_size = page_size;
> +  unsigned int page_size = getpagesize();
> +  bo_size = ALIGN(size, page_size);
> } else {
>bo_size = bucket->size;
> }
> +   assert(bo_size);
>
> mtx_lock(>lock);
> /* Get a buffer out of the cache if available */
> @@ -1578,12 +1577,12 @@ init_cache_buckets(struct brw_bufmgr *bufmgr)
>  * width/height alignment and rounding of sizes to pages will
>  * get us useful cache hit rates anyway)
>  */
> -   add_bucket(bufmgr, 4096);
> -   add_bucket(bufmgr, 4096 * 2);
> -   add_bucket(bufmgr, 4096 * 3);
> +   add_bucket(bufmgr, PAGE_SIZE);
> +   add_bucket(bufmgr, PAGE_SIZE * 2);
> +   add_bucket(bufmgr, PAGE_SIZE * 3);
>
> /* Initialize the linked lists for BO reuse cache. */
> -   for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
> +   for (size = 4 * PAGE_SIZE; size <= cache_max_size; size *= 2) {
>add_bucket(bufmgr, size);
>
>add_bucket(bufmgr, size + size * 1 / 4);
> @@ -1729,7 +1728,7 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int
> fd)
>   bufmgr->initial_kflags |= EXEC_OBJECT_PINNED;
>
>   util_vma_heap_init(>vma_allocator[BRW_MEMZONE_LOW_4G],
> -4096, _4GB);
> +PAGE_SIZE, _4GB);
>   util_vma_heap_init(>vma_allocator[BRW_MEMZONE_OTHER],
>  1 * _4GB, gtt_size - 1 * _4GB);
>} else if (devinfo->gen >= 10) {
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] radv: fix adjusting vertex fetches since 16bit support

[Samuel Pitoiset]

On 07/25/2018 02:55 PM, Bas Nieuwenhuizen wrote:

hmm, not sure why that did not fail on my CTS runs ...


Because 16bit is only enabled on Polaris?



Reviewed-by: Bas Nieuwenhuizen 

On Wed, Jul 25, 2018 at 2:55 PM, Samuel Pitoiset
 wrote:

Move the integer conversion after the fixup.

This fixes some regressions with
dEQP-VK.pipeline.vertex_input.single_attribute.mat4.as_a2r10g10b10*

Fixes: b722b29f10 ("radv: add support for 16bit input/output")
Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
  1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 9f9dc0d4fe..64b6522cd9 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2030,15 +2030,16 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
 output[chan] = LLVMBuildBitCast(ctx->ac.builder, 
output[chan], ctx->ac.f32, "");
 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, 
output[chan], ctx->ac.f16, "");
 }
-   output[chan] = ac_to_integer(>ac, output[chan]);
-   if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
-   output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], 
ctx->ac.i16, "");
 }

 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> 
(attrib_index * 2)) & 3;
 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, 
output[3]);

 for (unsigned chan = 0; chan < 4; chan++) {
+   output[chan] = ac_to_integer(>ac, output[chan]);
+   if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
+   output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], 
ctx->ac.i16, "");
+
 
ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = 
output[chan];
 }
 }
--
2.18.0

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[Mesa-dev] [PATCH v2] docs: fix incorrect placement of the ARB_sample_locations release notes

[Rhys Perry]

Seems something went wrong somehow when it was pushed.

v2: combine into one list

Signed-off-by: Rhys Perry 
---
 docs/relnotes/18.2.0.html | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html
index f757f4148a..8cdf6ac7d7 100644
--- a/docs/relnotes/18.2.0.html
+++ b/docs/relnotes/18.2.0.html
@@ -52,14 +52,11 @@ Note: some of the new features are only available with 
certain drivers.
 
 
 GL_ARB_fragment_shader_interlock on i965
+GL_ARB_sample_locations and GL_NV_sample_locations on nvc0 (GM200+)
 
 
 Bug fixes
 
-
-GL_ARB_sample_locations and GL_NV_sample_locations on nvc0 (GM200+)
-
-
 Changes
 
 
-- 
2.14.4

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[Mesa-dev] [PATCH] nvc0: serialize before updating some constant buffer bindings

[Rhys Perry]

To avoid serializing, this has the user constant buffer always be 65536
bytes and enabled unless it's required that something else is used for
constant buffer 0.

Fixes artifacts with at least XCOM: Enemy Within, 0 A.D. and Unigine
Valley, Heaven and Superposition.

v2: changed uniform_buffer_bound to be bool instead of a uint32_t

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=100177
Signed-off-by: Rhys Perry 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 13 +++---
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 46 +++---
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 13 +-
 .../drivers/nouveau/nvc0/nvc0_state_validate.c | 40 +--
 4 files changed, 76 insertions(+), 36 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index 11635c9465..578bf11d70 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -181,7 +181,7 @@ nvc0_compute_invalidate_constbufs(struct nvc0_context *nvc0)
/* Invalidate all 3D constbufs because they are aliased with COMPUTE. */
for (s = 0; s < 5; s++) {
   nvc0->constbuf_dirty[s] |= nvc0->constbuf_valid[s];
-  nvc0->state.uniform_buffer_bound[s] = 0;
+  nvc0->state.uniform_buffer_bound[s] = false;
}
nvc0->dirty_3d |= NVC0_NEW_3D_CONSTBUF;
 }
@@ -203,19 +203,18 @@ nvc0_compute_validate_constbufs(struct nvc0_context *nvc0)
  assert(i == 0); /* we really only want OpenGL uniforms here */
  assert(nvc0->constbuf[s][0].u.data);
 
- if (nvc0->state.uniform_buffer_bound[s] < size) {
-nvc0->state.uniform_buffer_bound[s] = align(size, 0x100);
+ if (!nvc0->state.uniform_buffer_bound[s]) {
+nvc0->state.uniform_buffer_bound[s] = true;
 
 BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
-PUSH_DATA (push, nvc0->state.uniform_buffer_bound[s]);
+PUSH_DATA (push, 65536);
 PUSH_DATAh(push, bo->offset + base);
 PUSH_DATA (push, bo->offset + base);
 BEGIN_NVC0(push, NVC0_CP(CB_BIND), 1);
 PUSH_DATA (push, (0 << 8) | 1);
  }
  nvc0_cb_bo_push(>base, bo, NV_VRAM_DOMAIN(>screen->base),
- base, nvc0->state.uniform_buffer_bound[s],
- 0, (size + 3) / 4,
+ base, 65536, 0, (size + 3) / 4,
  nvc0->constbuf[s][0].u.data);
   } else {
  struct nv04_resource *res =
@@ -236,7 +235,7 @@ nvc0_compute_validate_constbufs(struct nvc0_context *nvc0)
 PUSH_DATA (push, (i << 8) | 0);
  }
  if (i == 0)
-nvc0->state.uniform_buffer_bound[s] = 0;
+nvc0->state.uniform_buffer_bound[s] = false;
   }
}
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 37e10dcd07..197b0c1911 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -829,6 +829,40 @@ nvc0_screen_resize_text_area(struct nvc0_screen *screen, 
uint64_t size)
return 0;
 }
 
+void
+nvc0_screen_bind_cb_3d(struct nvc0_screen *screen, bool *can_serialize,
+   int stage, int index, int size, uint64_t addr)
+{
+   assert(stage != 5);
+
+   struct nouveau_pushbuf *push = screen->base.pushbuf;
+
+   if (screen->base.class_3d >= GM107_3D_CLASS) {
+  struct nvc0_cb_binding *binding = >cb_bindings[stage][index];
+
+  // TODO: Better figure out the conditions in which this is needed
+  bool serialize = binding->addr == addr && binding->size != size;
+  if (can_serialize)
+ serialize = serialize && *can_serialize;
+  if (serialize) {
+ IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
+ if (can_serialize)
+*can_serialize = false;
+  }
+
+  binding->addr = addr;
+  binding->size = size;
+   }
+
+   if (size >= 0) {
+  BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
+  PUSH_DATA (push, size);
+  PUSH_DATAh(push, addr);
+  PUSH_DATA (push, addr);
+   }
+   IMMED_NVC0(push, NVC0_3D(CB_BIND(stage)), (index << 4) | (size >= 0));
+}
+
 #define FAIL_SCREEN_INIT(str, err)\
do {   \
   NOUVEAU_ERR(str, err);  \
@@ -1272,14 +1306,14 @@ nvc0_screen_create(struct nouveau_device *dev)
 
/* XXX: Compute and 3D are somehow aliased on Fermi. */
for (i = 0; i < 5; ++i) {
+  unsigned j = 0;
+  for (j = 0; j < 16; j++)
+ screen->cb_bindings[i][j].size = -1;
+
   /* TIC and TSC entries for each unit (nve4+ only) */
   /* auxiliary constants (6 user clip planes, base instance id) */
-  BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
-  PUSH_DATA (push, NVC0_CB_AUX_SIZE);
-  PUSH_DATAh(push, screen->uniform_bo->offset + 

Re: [Mesa-dev] [PATCH] docs: fix incorrect placement of the ARB_sample_locations release notes

[Rhys Perry]

yeah, I think that's right.

On Wed, Jul 25, 2018 at 1:59 PM, Ilia Mirkin  wrote:
> On Wed, Jul 25, 2018 at 8:54 AM, Rhys Perry  wrote:
>> Seems something went wrong somehow when it was pushed.
>>
>> Signed-off-by: Rhys Perry 
>> ---
>>  docs/relnotes/18.2.0.html | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html
>> index f757f4148a..eeb0bbaf07 100644
>> --- a/docs/relnotes/18.2.0.html
>> +++ b/docs/relnotes/18.2.0.html
>> @@ -54,12 +54,12 @@ Note: some of the new features are only available with 
>> certain drivers.
>>  GL_ARB_fragment_shader_interlock on i965
>>  
>>
>> -Bug fixes
>> -
>>  
>>  GL_ARB_sample_locations and GL_NV_sample_locations on nvc0 (GM200+)
>>  
>
> Should probably combine it with the other list?
>
>>
>> +Bug fixes
>> +
>>  Changes
>>
>>  
>> --
>> 2.14.4
>>
>> ___
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Re: [Mesa-dev] [PATCH] docs: fix incorrect placement of the ARB_sample_locations release notes

[Ilia Mirkin]

On Wed, Jul 25, 2018 at 8:54 AM, Rhys Perry  wrote:
> Seems something went wrong somehow when it was pushed.
>
> Signed-off-by: Rhys Perry 
> ---
>  docs/relnotes/18.2.0.html | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html
> index f757f4148a..eeb0bbaf07 100644
> --- a/docs/relnotes/18.2.0.html
> +++ b/docs/relnotes/18.2.0.html
> @@ -54,12 +54,12 @@ Note: some of the new features are only available with 
> certain drivers.
>  GL_ARB_fragment_shader_interlock on i965
>  
>
> -Bug fixes
> -
>  
>  GL_ARB_sample_locations and GL_NV_sample_locations on nvc0 (GM200+)
>  

Should probably combine it with the other list?

>
> +Bug fixes
> +
>  Changes
>
>  
> --
> 2.14.4
>
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[Mesa-dev] [PATCH] docs: fix incorrect placement of the ARB_sample_locations release notes

[Rhys Perry]

Seems something went wrong somehow when it was pushed.

Signed-off-by: Rhys Perry 
---
 docs/relnotes/18.2.0.html | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html
index f757f4148a..eeb0bbaf07 100644
--- a/docs/relnotes/18.2.0.html
+++ b/docs/relnotes/18.2.0.html
@@ -54,12 +54,12 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_fragment_shader_interlock on i965
 
 
-Bug fixes
-
 
 GL_ARB_sample_locations and GL_NV_sample_locations on nvc0 (GM200+)
 
 
+Bug fixes
+
 Changes
 
 
-- 
2.14.4

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Re: [Mesa-dev] [PATCH] radv: fix adjusting vertex fetches since 16bit support

[Bas Nieuwenhuizen]

hmm, not sure why that did not fail on my CTS runs ...

Reviewed-by: Bas Nieuwenhuizen 

On Wed, Jul 25, 2018 at 2:55 PM, Samuel Pitoiset
 wrote:
> Move the integer conversion after the fixup.
>
> This fixes some regressions with
> dEQP-VK.pipeline.vertex_input.single_attribute.mat4.as_a2r10g10b10*
>
> Fixes: b722b29f10 ("radv: add support for 16bit input/output")
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
> b/src/amd/vulkan/radv_nir_to_llvm.c
> index 9f9dc0d4fe..64b6522cd9 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -2030,15 +2030,16 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
> output[chan] = 
> LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
> output[chan] = 
> LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
> }
> -   output[chan] = ac_to_integer(>ac, output[chan]);
> -   if (type == GLSL_TYPE_UINT16 || type == 
> GLSL_TYPE_INT16)
> -   output[chan] = 
> LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
> }
>
> unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> 
> (attrib_index * 2)) & 3;
> output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, 
> output[3]);
>
> for (unsigned chan = 0; chan < 4; chan++) {
> +   output[chan] = ac_to_integer(>ac, output[chan]);
> +   if (type == GLSL_TYPE_UINT16 || type == 
> GLSL_TYPE_INT16)
> +   output[chan] = 
> LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
> +
> 
> ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = 
> output[chan];
> }
> }
> --
> 2.18.0
>
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[Mesa-dev] [PATCH] radv: fix adjusting vertex fetches since 16bit support

[Samuel Pitoiset]

Move the integer conversion after the fixup.

This fixes some regressions with
dEQP-VK.pipeline.vertex_input.single_attribute.mat4.as_a2r10g10b10*

Fixes: b722b29f10 ("radv: add support for 16bit input/output")
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 9f9dc0d4fe..64b6522cd9 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2030,15 +2030,16 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
output[chan] = 
LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
output[chan] = 
LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
}
-   output[chan] = ac_to_integer(>ac, output[chan]);
-   if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
-   output[chan] = LLVMBuildTrunc(ctx->ac.builder, 
output[chan], ctx->ac.i16, "");
}
 
unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> 
(attrib_index * 2)) & 3;
output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, 
output[3]);
 
for (unsigned chan = 0; chan < 4; chan++) {
+   output[chan] = ac_to_integer(>ac, output[chan]);
+   if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
+   output[chan] = LLVMBuildTrunc(ctx->ac.builder, 
output[chan], ctx->ac.i16, "");
+

ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = 
output[chan];
}
}
-- 
2.18.0

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Re: [Mesa-dev] [RFC][PATCH 4/5] Android.mk: Add option to use vendor version of mesa

[Harish Krupo]

Emil,

Emil Velikov  writes:

> On 25 July 2018 at 00:21, John Stultz  wrote:
>> From: Yong Yao 
>>
>> This is a forward port of a patch from the AOSP/master branch:
>> https://android.googlesource.com/platform/external/mesa3d/+/b1e5fad1db4c1d51c7ae3a033b100a8429ae5415%5E%21/
>>
>> Which allows boards to provide their own custom copy of mesa.
>>
> Thanks for sorting these out John.
>
> My understanding was that when a custom project repo is used one
> handles that in the device manifest. Roughly as:
>  - foo.xml -> contains vast majority of the git repos with associated tags/etc
>  - local.xml -> removes any repo/project from ^^, adds new one
>
> Is that no longer the case, or I simply misremember how Android does things?
>

You do remember correctly. :)
Generally there is a default.xml which includes projects.xml and
remove.xml. Projects.xml contains all the  lines and the
remove.xml contains the  lines to remove those
repos for that particular project.


Reference: https://github.com/projectceladon/manifest

Thank you
Regards
Harish Krupo
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Re: [Mesa-dev] [RFC][PATCH 0/5] Trying to align mesa upstream w/ AOSP/master

[Emil Velikov]

Hi John,

On 25 July 2018 at 00:21, John Stultz  wrote:
> In trying to keep the upstream mesa aligned with AOSP, I wanted
> to submit a few changes that seemed reasonable to upstream.
>
> The first two are build fixes that are required to get mesa master
> building with AOSP. The last three are less critical, but seemed
> like things we might as well try to sync between the trees.
>
> Feedback and comments would be greatly appreciated!
>
Thanks again for sorting these out.

Patches 2&3 will need some minor tweaks. With that 1-3 are
Reviewed-by: Emil Velikov 

Patches 4&5 seem like fairly gross hacks, although I could be wrong.
If they indeed are hacks and proper solution is not possible, please
clearly document that. Be that in the commit message and/or inline
comment.

-Emil
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Re: [Mesa-dev] [RFC][PATCH 5/5] Android.mk: Fix checkbuild on Mac builders.

[Emil Velikov]

On 25 July 2018 at 00:21, John Stultz  wrote:
> From: Alistair Strachan 
>
> This is a forward port of a patch in the AOSP/master tree:
> https://android.googlesource.com/platform/external/mesa3d/+/d7f894a7d39e66ca5a832c19edaf175400041aff%5E%21/
>
> The libmesa_dri_common target depends on xgettext unconditionally, but
> this is not a documented dependency of AOSP and is not installed on the
> Mac builders, so we must not build any part of mesa3d on these
> platforms.
>
> Cc: Rob Herring 
> Cc: Alistair Strachan 
> Cc: Marissa Wall 
> Cc: Sumit Semwal 
> Cc: Emil Velikov 
> Cc: Rob Clark 
> Signed-off-by: Alistair Strachan 
> Signed-off-by: John Stultz 
> ---
>  Android.mk | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Android.mk b/Android.mk
> index 494b4b9..128db4d 100644
> --- a/Android.mk
> +++ b/Android.mk
> @@ -30,6 +30,8 @@
>  # module will also be built.  DRI modules will be loaded by libGLES_mesa.
>
>  ifneq ($(BOARD_USE_CUSTOMIZED_MESA), true)
> +ifneq ($(BOARD_GPU_DRIVERS),)
> +

Something looks fairly weird here. Commit message talks about Mac and
xgettext while this here checks for BOARD_GPU_DRIVERS.
IIRC, libGLES_mesa must be explicitly pulled in the device
manifest/project in order to for Mesa be built. The exact same one
tends to set BOARD_GPU_DRIVERS.

Or looking it from another angle - if the Mac builder is missing
xgettext one could add it, becoming in sync with other builders.
Quick search shows that it's available in brew (brew install gettext)
and one can build it locally.

-Emil
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Re: [Mesa-dev] [RFC][PATCH 4/5] Android.mk: Add option to use vendor version of mesa

[Emil Velikov]

On 25 July 2018 at 00:21, John Stultz  wrote:
> From: Yong Yao 
>
> This is a forward port of a patch from the AOSP/master branch:
> https://android.googlesource.com/platform/external/mesa3d/+/b1e5fad1db4c1d51c7ae3a033b100a8429ae5415%5E%21/
>
> Which allows boards to provide their own custom copy of mesa.
>
Thanks for sorting these out John.

My understanding was that when a custom project repo is used one
handles that in the device manifest. Roughly as:
 - foo.xml -> contains vast majority of the git repos with associated tags/etc
 - local.xml -> removes any repo/project from ^^, adds new one

Is that no longer the case, or I simply misremember how Android does things?

Thanks
Emil
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Re: [Mesa-dev] [RFC][PATCH 3/5] CleanSpec.mk: Remove HOST_OUT_release

[Emil Velikov]

On 25 July 2018 at 00:21, John Stultz  wrote:
> From: Dan Willemsen 
>
> This is a forward port of a patch from the AOSP/master tree:
> https://android.googlesource.com/platform/external/mesa3d/+/bd633f11de0c6ac1ed333a28344c74fd9898df9e%5E%21/
>
> Which replaces HOST_OUT_release with HOST_OUT
>
What's wrong with HOST_OUT_release? If it is something that got
deprecated, we could:
 a) add a comment above it (deprecated since Android ...)
 b) add the HOST_OUT alongside the existing HOST_OUT_release

-Emil
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Re: [Mesa-dev] [RFC][PATCH 2/5] Android.common.mk: define HAVE_TIMESPEC_GET

[Emil Velikov]

On 25 July 2018 at 00:21, John Stultz  wrote:
> From: Sumit Semwal 
>
> This is a forward port of a patch from the AOSP/master tree:
> https://android.googlesource.com/platform/external/mesa3d/+/bd30b663f55f8af73a0be4446349c5a2d4c641b0%5E%21/
>
> Since https://android-review.googlesource.com/c/718518 added
> timespec_get() to bionic, mesa3d doesn't build due to redefinition
> of timespec_get().
>
Is this bionic commit available all the way back to Android 5?
If not, you should conditionally add the define where needed - see
Android.mk for examples.

-Emil
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[Mesa-dev] [PATCH] nir: remove wrong assertion in print_var_decl()

[Samuel Pitoiset]

This breaks printing input/output variables with more than
4 components like mat4.

Fixes: 1beef89ad8 ("nir: prepare for bumping up max components to 16")
Signed-off-by: Samuel Pitoiset 
---
 src/compiler/nir/nir_print.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index 93d1c02f23..7cb16abd14 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -491,7 +491,6 @@ print_var_decl(nir_variable *var, print_state *state)
   switch (var->data.mode) {
   case nir_var_shader_in:
   case nir_var_shader_out:
- assert(num_components <= 4);
  if (num_components < 4 && num_components != 0) {
 const char *xyzw = "xyzw";
 for (int i = 0; i < num_components; i++)
-- 
2.18.0

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[Mesa-dev] Reminder, 18.2 branching on Wednesday, the 1st of August

[Andres Gomez]

I just wanted to remind everyone that the plan is to branch for 18.2 on
Wednesday, the 1st of August. I plan to take the head of master around
10:00 am EEST, and assuming that all of our CI testing is good that
will become the 18.2 branch point with RC1 to follow after that.

The status of the *features* to be finished before branching time can
be tracked at:
https://bugs.freedesktop.org/show_bug.cgi?id=106156

Oh, and I'll be managing the 18.2 release, so please bear with me :)

-- 
Br,

Andres
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Re: [Mesa-dev] [PATCH 0/7] ASTC texture compression for all Gallium drivers

[Mike Lothian]

Hi

Glxinfo reporting things correctly, as does es2info and my GLES apps
continue to work

Are there any apps that explicitly use GLES3.2 that I can test for you?

Extended renderer info (GLX_MESA_query_renderer):
Vendor: X.Org (0x1002)
Device: AMD Radeon R9 M295X (TONGA, DRM 3.27.0, 4.18.0-rc3-agd5f+, LLVM
7.0.0) (0x6921)
Version: 18.2.0
Accelerated: yes
Video memory: 4096MB
Unified memory: no
Preferred profile: core (0x1)
Max core profile version: 4.5
Max compat profile version: 4.4
Max GLES1 profile version: 1.1
Max GLES[23] profile version: 3.2

Feel free to add my tested by:

Tested-by: Mike Lothian 

Cheers

Mike

On Tue, 24 Jul 2018 at 00:52 Marek Olšák  wrote:

> Hi,
>
> This series enables ASTC texture compression for all Gallium drivers
> that don't support it in hardware. The works the same as the ETC2
> fallback, i.e. it decompresses ASTC inside glCompressedTexImage to
> a supported uncompressed format.
>
> RadeonSI now finally supports the following:
> - GL_KHR_texture_compression_astc_ldr
> - GL_ANDROID_extension_pack_es31a
> - OpenGL ES 3.2 !!!
>
> All ASTC dEQP tests pass.
>
> Please review.
>
> Thanks,
> Marek
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[Mesa-dev] [Bug 106922] Tangrams demo: LLVM ERROR: Cannot select: 0x7e8d8750: i16 = bitcast 0x7e8d8af8

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106922

--- Comment #5 from Samuel Pitoiset  ---
Missing 16-bit integer support.

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Re: [Mesa-dev] [PATCH] meson: enable -fmerge-all-constants by default

[Konstantin Kharlamov]

FWIW I just realized it also enables -fmerge-constants which is enabled 
at all optimize levels, and built/compared it with fmerge-all-constants. 
The difference is still noticeable. If anybody interested, I can 
pretty-format it, and send here.


On 25.07.2018 14:03, Konstantin Kharlamov wrote:

This is a standard non-conforming optimization, which, quoting,
"…considers e.g. even constant initialized arrays or initialized
constant variables with integral or floating-point types. Languages like
C or C++ require each variable, including multiple instances of the same
variable in recursive calls, to have distinct locations, so using this
option results in non-conforming behavior."

Having the same or distinct addresses of constants in recursive calls is
too obscure behavior to make any use of. More over, until 4 April 2018
clang have had this option enabled by default¹, and nobody ever noticed
until kernel build fail this year (having a low-level hackery in kernel
surprises no one), resulting in PR disabling the option by default.

As for Mesa: I personally have been using the option for release builds
since forever, never had any problems.

Real world significance, sizes of binaries in bytes:

default  | -fmerge-all-constants
| diff
-
  8048024 <-> bellagio/libomx_mesa.so |  7867800 <-> 
bellagio/libomx_mesa.so | -180224
10209120 <-> d3d/d3dadapter9.so.1.0.0| 10016608 <-> 
d3d/d3dadapter9.so.1.0.0| -192512
14464936 <-> dri/i915_dri.so | 14383016 <-> dri/i915_dri.so 
| -81920
16894344 <-> dri/kms_swrast_dri.so   | 16644488 <-> 
dri/kms_swrast_dri.so   | -249856
  8077560 <-> dri/nouveau_drv_video.so|  7893240 <-> 
dri/nouveau_drv_video.so| -184320
  3882872 <-> gallium-pipe/pipe_nouveau.so|  3870584 <-> 
gallium-pipe/pipe_nouveau.so| -12288
  2511160 <-> gallium-pipe/pipe_r300.so   |  2502968 <-> 
gallium-pipe/pipe_r300.so   | -8192
  2818520 <-> gallium-pipe/pipe_r600.so   |  2810328 <-> 
gallium-pipe/pipe_r600.so   | -8192
  4123056 <-> gallium-pipe/pipe_radeonsi.so   |  3955120 <-> 
gallium-pipe/pipe_radeonsi.so   | -167936
  2413936 <-> gallium-pipe/pipe_swrast.so |  2401648 <-> 
gallium-pipe/pipe_swrast.so | -12288
  2701360 <-> gallium-pipe/pipe_vmwgfx.so |  2689072 <-> 
gallium-pipe/pipe_vmwgfx.so | -12288
   582496 <-> libGLX_mesa.so.0.0.0|   578400 <-> 
libGLX_mesa.so.0.0.0| -4096
23451656 <-> libMesaOpenCL.so.1.0.0  | 23447560 <-> 
libMesaOpenCL.so.1.0.0  | -4096
10370344 <-> libOSMesa.so.8.0.0  | 10300712 <-> libOSMesa.so.8.0.0  
| -69632
  4766032 <-> libvulkan_intel.so  |  4745552 <-> libvulkan_intel.so 
 | -20480
  2761376 <-> libvulkan_radeon.so |  2753184 <-> 
libvulkan_radeon.so | -8192
  4703776 <-> libxatracker.so.2.4.0   |  4687392 <-> 
libxatracker.so.2.4.0   | -16384
  8510392 <-> vdpau/libvdpau_nouveau.so.1.0.0 |  8326072 <-> 
vdpau/libvdpau_nouveau.so.1.0.0 | -184320

For consistency it's enabled for both debug and release builds.

1: https://reviews.llvm.org/D45289

Signed-off-by: Konstantin Kharlamov 
---
  meson.build | 5 +
  1 file changed, 5 insertions(+)

diff --git a/meson.build b/meson.build
index e05645cbf3..36016cf959 100644
--- a/meson.build
+++ b/meson.build
@@ -794,6 +794,11 @@ foreach a : ['-Wall', '-fno-math-errno', 
'-fno-trapping-math',
endif
  endforeach
  
+if ['gcc', 'clang'].contains(cc.get_id())

+  c_args += '-fmerge-all-constants'
+  cpp_args += '-fmerge-all-constants'
+endif
+
  # For some reason, the test for -Wno-foo always succeeds with gcc, even if the
  # option is not supported. Hence, check for -Wfoo instead.
  


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Re: [Mesa-dev] [RFC 0/6] VK_ANDROID_external_memory_android_hardware_buffer

[Tapani Pälli]

Any comments? I'm planning to rebase this and try to investigate what is 
missing from CTS perspective.


On 05/29/2018 10:08 AM, Tapani Pälli wrote:

Hi;

Here's RFC for the extension. I've tested the import/export functionality
with RGBA images on Android Celadon with a custom NDK app that draws a
textured cube using AHardwareBuffer contents. Export feature I tested
by creating just a regular image (LunarG cube texture) and then exporting
that as AHardwareBuffer, modifying buffer and then rendering the
results.

I wanted to send this RFC to get some comments on what's missing and if
I have understood the specification correctly. If supporting only RGBA
for now is fine, I believe we could go forward with these bits.

Any comments appreciated!

Thanks;

// Tapani

Tapani Pälli (6):
   anv: make anv_get_image_format_features public
   anv: add from/to helpers with android and vulkan formats
   anv/android: add GetAndroidHardwareBufferPropertiesANDROID WIP
   anv/android: support import/export of AHardwareBuffer objects
   anv/android: support creating images from external format
   anv/android: turn on
 VK_ANDROID_external_memory_android_hardware_buffer

  src/intel/vulkan/anv_android.c | 228 +
  src/intel/vulkan/anv_device.c  |  48 +++-
  src/intel/vulkan/anv_extensions.py |   1 +
  src/intel/vulkan/anv_formats.c |  22 ++--
  src/intel/vulkan/anv_image.c   | 115 +++
  src/intel/vulkan/anv_private.h |  33 ++
  src/intel/vulkan/vk_format_info.h  |  43 +++
  7 files changed, 478 insertions(+), 12 deletions(-)


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[Mesa-dev] [PATCH] anv: add more swapchain formats

[Tapani Pälli]

This change helps with some of the dEQP-VK.wsi.android.* tests that
try to create swapchain with using such formats.

Signed-off-by: Tapani Pälli 
---
 src/intel/vulkan/anv_android.c | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/src/intel/vulkan/anv_android.c b/src/intel/vulkan/anv_android.c
index a3bab8087b..46c41d5786 100644
--- a/src/intel/vulkan/anv_android.c
+++ b/src/intel/vulkan/anv_android.c
@@ -300,11 +300,17 @@ VkResult anv_GetSwapchainGrallocUsageANDROID(
 *
 * FINISHME: Advertise all display-supported formats.
 */
-   if (format == VK_FORMAT_B8G8R8A8_UNORM ||
-   format == VK_FORMAT_B5G6R5_UNORM_PACK16) {
-  *grallocUsage |= GRALLOC_USAGE_HW_FB |
-   GRALLOC_USAGE_HW_COMPOSER |
-   GRALLOC_USAGE_EXTERNAL_DISP;
+   switch (format) {
+  case VK_FORMAT_B8G8R8A8_UNORM:
+  case VK_FORMAT_B5G6R5_UNORM_PACK16:
+  case VK_FORMAT_R8G8B8A8_UNORM:
+  case VK_FORMAT_R8G8B8A8_SRGB:
+ *grallocUsage |= GRALLOC_USAGE_HW_FB |
+  GRALLOC_USAGE_HW_COMPOSER |
+  GRALLOC_USAGE_EXTERNAL_DISP;
+ break;
+  default:
+ intel_logw("%s: unsupported format=%d", __func__, format);
}
 
if (*grallocUsage == 0)
-- 
2.14.4

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[Mesa-dev] [PATCH] meson: enable -fmerge-all-constants by default

[Konstantin Kharlamov]

This is a standard non-conforming optimization, which, quoting,
"…considers e.g. even constant initialized arrays or initialized
constant variables with integral or floating-point types. Languages like
C or C++ require each variable, including multiple instances of the same
variable in recursive calls, to have distinct locations, so using this
option results in non-conforming behavior."

Having the same or distinct addresses of constants in recursive calls is
too obscure behavior to make any use of. More over, until 4 April 2018
clang have had this option enabled by default¹, and nobody ever noticed
until kernel build fail this year (having a low-level hackery in kernel
surprises no one), resulting in PR disabling the option by default.

As for Mesa: I personally have been using the option for release builds
since forever, never had any problems.

Real world significance, sizes of binaries in bytes:

default  | -fmerge-all-constants
| diff
-
 8048024 <-> bellagio/libomx_mesa.so |  7867800 <-> 
bellagio/libomx_mesa.so | -180224
10209120 <-> d3d/d3dadapter9.so.1.0.0| 10016608 <-> 
d3d/d3dadapter9.so.1.0.0| -192512
14464936 <-> dri/i915_dri.so | 14383016 <-> dri/i915_dri.so 
| -81920
16894344 <-> dri/kms_swrast_dri.so   | 16644488 <-> 
dri/kms_swrast_dri.so   | -249856
 8077560 <-> dri/nouveau_drv_video.so|  7893240 <-> 
dri/nouveau_drv_video.so| -184320
 3882872 <-> gallium-pipe/pipe_nouveau.so|  3870584 <-> 
gallium-pipe/pipe_nouveau.so| -12288
 2511160 <-> gallium-pipe/pipe_r300.so   |  2502968 <-> 
gallium-pipe/pipe_r300.so   | -8192
 2818520 <-> gallium-pipe/pipe_r600.so   |  2810328 <-> 
gallium-pipe/pipe_r600.so   | -8192
 4123056 <-> gallium-pipe/pipe_radeonsi.so   |  3955120 <-> 
gallium-pipe/pipe_radeonsi.so   | -167936
 2413936 <-> gallium-pipe/pipe_swrast.so |  2401648 <-> 
gallium-pipe/pipe_swrast.so | -12288
 2701360 <-> gallium-pipe/pipe_vmwgfx.so |  2689072 <-> 
gallium-pipe/pipe_vmwgfx.so | -12288
  582496 <-> libGLX_mesa.so.0.0.0|   578400 <-> 
libGLX_mesa.so.0.0.0| -4096
23451656 <-> libMesaOpenCL.so.1.0.0  | 23447560 <-> 
libMesaOpenCL.so.1.0.0  | -4096
10370344 <-> libOSMesa.so.8.0.0  | 10300712 <-> libOSMesa.so.8.0.0  
| -69632
 4766032 <-> libvulkan_intel.so  |  4745552 <-> libvulkan_intel.so  
| -20480
 2761376 <-> libvulkan_radeon.so |  2753184 <-> libvulkan_radeon.so 
| -8192
 4703776 <-> libxatracker.so.2.4.0   |  4687392 <-> 
libxatracker.so.2.4.0   | -16384
 8510392 <-> vdpau/libvdpau_nouveau.so.1.0.0 |  8326072 <-> 
vdpau/libvdpau_nouveau.so.1.0.0 | -184320

For consistency it's enabled for both debug and release builds.

1: https://reviews.llvm.org/D45289

Signed-off-by: Konstantin Kharlamov 
---
 meson.build | 5 +
 1 file changed, 5 insertions(+)

diff --git a/meson.build b/meson.build
index e05645cbf3..36016cf959 100644
--- a/meson.build
+++ b/meson.build
@@ -794,6 +794,11 @@ foreach a : ['-Wall', '-fno-math-errno', 
'-fno-trapping-math',
   endif
 endforeach
 
+if ['gcc', 'clang'].contains(cc.get_id())
+  c_args += '-fmerge-all-constants'
+  cpp_args += '-fmerge-all-constants'
+endif
+
 # For some reason, the test for -Wno-foo always succeeds with gcc, even if the
 # option is not supported. Hence, check for -Wfoo instead.
 
-- 
2.18.0

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[Mesa-dev] [Bug 106411] Invalid gl_InstanceID value with combination of gl_DrawIDARB under OpenGL

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106411

--- Comment #1 from Tapani Pälli  ---
I've tried your example app with current Mesa (b3b170ade9) and for me the end
result visually is the same whether or not I comment out line that adds
gl_VertexID usage. Could you comment on what is the expected result
with/without the line and maybe also retry test with current Mesa?

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[Mesa-dev] [PATCH v3] intel/ppgtt: memory address alignment

[Sergii Romantsov]

Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).

-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris Wilson).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.)
Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to 
brw_bufmgr.)
Signed-off-by: Sergii Romantsov 
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 09d45e3..66d7751 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -195,7 +195,7 @@ bo_tile_size(struct brw_bufmgr *bufmgr, uint64_t size, 
uint32_t tiling)
   return size;
 
/* 965+ just need multiples of page size for tiling */
-   return ALIGN(size, 4096);
+   return ALIGN(size, PAGE_SIZE);
 }
 
 /*
@@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
   uint32_t stride)
 {
struct brw_bo *bo;
-   unsigned int page_size = getpagesize();
int ret;
struct bo_cache_bucket *bucket;
bool alloc_from_cache;
@@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
 * allocation up.
 */
if (bucket == NULL) {
-  bo_size = size;
-  if (bo_size < page_size)
- bo_size = page_size;
+  unsigned int page_size = getpagesize();
+  bo_size = ALIGN(size, page_size);
} else {
   bo_size = bucket->size;
}
+   assert(bo_size);
 
mtx_lock(>lock);
/* Get a buffer out of the cache if available */
@@ -1578,12 +1577,12 @@ init_cache_buckets(struct brw_bufmgr *bufmgr)
 * width/height alignment and rounding of sizes to pages will
 * get us useful cache hit rates anyway)
 */
-   add_bucket(bufmgr, 4096);
-   add_bucket(bufmgr, 4096 * 2);
-   add_bucket(bufmgr, 4096 * 3);
+   add_bucket(bufmgr, PAGE_SIZE);
+   add_bucket(bufmgr, PAGE_SIZE * 2);
+   add_bucket(bufmgr, PAGE_SIZE * 3);
 
/* Initialize the linked lists for BO reuse cache. */
-   for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
+   for (size = 4 * PAGE_SIZE; size <= cache_max_size; size *= 2) {
   add_bucket(bufmgr, size);
 
   add_bucket(bufmgr, size + size * 1 / 4);
@@ -1729,7 +1728,7 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd)
  bufmgr->initial_kflags |= EXEC_OBJECT_PINNED;
 
  util_vma_heap_init(>vma_allocator[BRW_MEMZONE_LOW_4G],
-4096, _4GB);
+PAGE_SIZE, _4GB);
  util_vma_heap_init(>vma_allocator[BRW_MEMZONE_OTHER],
 1 * _4GB, gtt_size - 1 * _4GB);
   } else if (devinfo->gen >= 10) {
-- 
2.7.4

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[Mesa-dev] [PATCH v3 10/26] python: Use explicit integer divisions

[Mathieu Bridon]

In Python 2, divisions of integers return an integer:

>>> 32 / 4
8

In Python 3 though, they return floats:

>>> 32 / 4
8.0

However, Python 3 has an explicit integer division operator:

>>> 32 // 4
8

That operator exists on Python >= 2.2, so let's use it everywhere to
make the scripts compatible with both Python 2 and 3.

In addition, using __future__.division tells Python 2 to behave the same
way as Python 3, which helps ensure the scripts produce the same output
in both versions of Python.

Signed-off-by: Mathieu Bridon 
Reviewed-by: Eric Engestrom  (v2)
---
 src/gallium/auxiliary/util/u_format_pack.py  | 4 ++--
 src/gallium/auxiliary/util/u_format_parse.py | 7 +--
 src/mapi/glapi/gen/glX_proto_send.py | 4 ++--
 src/mesa/main/format_info.py | 4 ++--
 src/mesa/main/format_pack.py | 8 
 src/mesa/main/format_unpack.py   | 8 
 6 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_format_pack.py 
b/src/gallium/auxiliary/util/u_format_pack.py
index 7a952a48b3..ad2e49281f 100644
--- a/src/gallium/auxiliary/util/u_format_pack.py
+++ b/src/gallium/auxiliary/util/u_format_pack.py
@@ -36,7 +36,7 @@
 '''
 
 
-from __future__ import print_function
+from __future__ import division, print_function
 
 from u_format_parse import *
 
@@ -240,7 +240,7 @@ def value_to_native(type, value):
 return truncate_mantissa(value, 23)
 return value
 if type.type == FIXED:
-return int(value * (1 << (type.size/2)))
+return int(value * (1 << (type.size // 2)))
 if not type.norm:
 return int(value)
 if type.type == UNSIGNED:
diff --git a/src/gallium/auxiliary/util/u_format_parse.py 
b/src/gallium/auxiliary/util/u_format_parse.py
index c0456f6d15..d3874cd895 100644
--- a/src/gallium/auxiliary/util/u_format_parse.py
+++ b/src/gallium/auxiliary/util/u_format_parse.py
@@ -29,6 +29,9 @@
 '''
 
 
+from __future__ import division
+
+
 VOID, UNSIGNED, SIGNED, FIXED, FLOAT = range(5)
 
 SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_0, SWIZZLE_1, 
SWIZZLE_NONE, = range(7)
@@ -76,7 +79,7 @@ class Channel:
 if self.type == FLOAT:
 return VERY_LARGE
 if self.type == FIXED:
-return (1 << (self.size/2)) - 1
+return (1 << (self.size // 2)) - 1
 if self.norm:
 return 1
 if self.type == UNSIGNED:
@@ -90,7 +93,7 @@ class Channel:
 if self.type == FLOAT:
 return -VERY_LARGE
 if self.type == FIXED:
-return -(1 << (self.size/2))
+return -(1 << (self.size // 2))
 if self.type == UNSIGNED:
 return 0
 if self.norm:
diff --git a/src/mapi/glapi/gen/glX_proto_send.py 
b/src/mapi/glapi/gen/glX_proto_send.py
index a920ecc012..03067d8a3c 100644
--- a/src/mapi/glapi/gen/glX_proto_send.py
+++ b/src/mapi/glapi/gen/glX_proto_send.py
@@ -26,7 +26,7 @@
 #Ian Romanick 
 #Jeremy Kolb 
 
-from __future__ import print_function
+from __future__ import division, print_function
 
 import argparse
 
@@ -809,7 +809,7 @@ generic_%u_byte( GLint rop, const void * ptr )
 # Dividing by the array size (1 for
 # non-arrays) gives us this.
 
-s = p.size() / p.get_element_count()
+s = p.size() // p.get_element_count()
 print("   %s __glXReadReply(dpy, %s, %s, %s);" % 
(return_str, s, p.name, aa))
 got_reply = 1
 
diff --git a/src/mesa/main/format_info.py b/src/mesa/main/format_info.py
index bbecaa2451..00e27b3fba 100644
--- a/src/mesa/main/format_info.py
+++ b/src/mesa/main/format_info.py
@@ -21,7 +21,7 @@
 # TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 # SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
-from __future__ import print_function
+from __future__ import division, print_function
 
 import format_parser as parser
 import sys
@@ -198,7 +198,7 @@ for fmat in formats:
   chan = fmat.array_element()
   norm = chan.norm or chan.type == parser.FLOAT
   print('  .ArrayFormat = MESA_ARRAY_FORMAT({0}),'.format(', '.join([
- str(chan.size / 8),
+ str(chan.size // 8),
  str(int(chan.sign)),
  str(int(chan.type == parser.FLOAT)),
  str(int(norm)),
diff --git a/src/mesa/main/format_pack.py b/src/mesa/main/format_pack.py
index d3c8d24acd..0b9e0d424d 100644
--- a/src/mesa/main/format_pack.py
+++ b/src/mesa/main/format_pack.py
@@ -356,7 +356,7 @@ _mesa_pack_ubyte_rgba_row(mesa_format format, GLuint n,
case ${f.name}:
   for (i = 0; i < n; ++i) {
  pack_ubyte_${f.short_name()}(src[i], d);
- d += ${f.block_size() / 8};
+ d += ${f.block_size() // 8};
   }
   break;
 %endfor
@@ -388,7 +388,7 @@ _mesa_pack_uint_rgba_row(mesa_format format, GLuint n,
case ${f.name}:
   for (i = 0; i < n; 

Re: [Mesa-dev] [PATCH v2] intel/ppgtt: memory address alignment

[Chris Wilson]

Quoting Sergii Romantsov (2018-07-25 10:37:29)
> Hello, Chris.
> Your variant also works.
> But i wonder about comment:
>    /* If we don't have caching at this size, don't actually round the
>     * allocation up.
>     */
>    if (bucket == NULL) {
> 
> Has it any sense now? If 'no' - will delete it in next patch update.

It's actually talking about rounding up to bucket size which started off
as next power-of-two, since reduced to some fractions and even now the
rounding is debatable. The page size allocation is a property of the
uABI -- objects are allocated in pages.

Now there is no reason the bufmgr can't do sub-page allocations, it
would take a bit of work to factor out the offset_in_page() later but
doable.
-Chris
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Re: [Mesa-dev] [PATCH v2] intel/ppgtt: memory address alignment

[Sergii Romantsov]

Hello, Chris.
Your variant also works.
But i wonder about comment:
   /* If we don't have caching at this size, don't actually round the
* allocation up.
*/
   if (bucket == NULL) {

Has it any sense now? If 'no' - will delete it in next patch update.

Was trying to get commit where and why it was added and it brings me to:
commit 514db96c117adc84940bb08ebd0e8f84879bd4ad
Author: Kenneth Graunke 
Date:   Mon Mar 20 16:40:01 2017 -0700

i965: Import libdrm_intel.

This imports commit 19c4cfc54918d361f2535aec16650e9f0be667cd of
libdrm/intel/*.[ch], minus a few files that we're never going to use
(and would immediately delete), plus a few necessary dependencies.

We rename intel_bufmgr.h to brw_bufmgr.h to avoid #include conflicts.
We also fix UTF-8 symbol problems in intel_bufmgr_gem.c comments
because vim keeps trying to fix that every time I edit the file,
and we may as well fix it right away.


Repository of libdrm (master and tags about 2.4.7 and 2.4.8) doesn't
contain such commit. Observed only that it fixes some crash of VB (
https://www.mail-archive.com/ubuntu-bugs@lists.ubuntu.com/msg5146035.html)

On Wed, Jul 25, 2018 at 10:48 AM, Chris Wilson 
wrote:

> Quoting Sergii Romantsov (2018-07-25 08:42:55)
> > Hello,
> > here is a backtrace:
> ...
>
> Please try:
> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> index 09d45e30ecc..8274c2e0b2f 100644
> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> @@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
>uint32_t stride)
>  {
> struct brw_bo *bo;
> -   unsigned int page_size = getpagesize();
> int ret;
> struct bo_cache_bucket *bucket;
> bool alloc_from_cache;
> @@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
>  * allocation up.
>  */
> if (bucket == NULL) {
> -  bo_size = size;
> -  if (bo_size < page_size)
> - bo_size = page_size;
> +  unsigned int page_size = getpagesize();
> +  bo_size = ALIGN(size, page_size);
> } else {
>bo_size = bucket->size;
> }
> +   assert(bo_size);
>
> mtx_lock(>lock);
> /* Get a buffer out of the cache if available */
>



-- 
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GlobalLogic Inc.
www.globallogic.com
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[Mesa-dev] [Bug 106283] Shader replacements works only for limited use cases

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=106283

Tapani Pälli  changed:

   What|Removed |Added

 Status|NEW |ASSIGNED
   Assignee|mesa-dev@lists.freedesktop. |lem...@gmail.com
   |org |

--- Comment #15 from Tapani Pälli  ---
FYI I've sent patch for review:
https://lists.freedesktop.org/archives/mesa-dev/2018-July/200885.html

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Re: [Mesa-dev] [PATCH] st/nir: Fix st_nir_opts() prototype.

[Christian Gmeiner]

Reviewed-by: Christian Gmeiner 

--
Christian Gmeiner, MSc

https://christian-gmeiner.info

Kenneth Graunke  schrieb am Di., 24. Juli 2018,
23:55:

> This wasn't updated for the new scalar ISA parameter.  It worked anyway
> because all the function's callers live in the same file, so it found
> the correct function.  Tim made this external for the new st prog_to_nir
> translator, which got reverted, but which I'd like to land eventually.
>
> So, fix the prototype.
> ---
>  src/mesa/state_tracker/st_nir.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_nir.h
> b/src/mesa/state_tracker/st_nir.h
> index 15f1ce93e5a..aa6e32758e8 100644
> --- a/src/mesa/state_tracker/st_nir.h
> +++ b/src/mesa/state_tracker/st_nir.h
> @@ -42,7 +42,7 @@ void st_finalize_nir(struct st_context *st, struct
> gl_program *prog,
>   struct gl_shader_program *shader_program,
>   struct nir_shader *nir);
>
> -void st_nir_opts(struct nir_shader *nir);
> +void st_nir_opts(struct nir_shader *nir, bool is_scalar);
>
>  bool
>  st_link_nir(struct gl_context *ctx,
> --
> 2.18.0
>
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Re: [Mesa-dev] [PATCH v3] vulkan: Fix compilation on older platforms

[Danylo Piliaiev]

Hi Emil,


On 24.07.18 19:23, Emil Velikov wrote:

Hi Danylo,

Having a closer look inspired by Eric's comments

On 24 July 2018 at 15:37, Danylo Piliaiev  wrote:

Check for DRM_EVENT_CONTEXT_VERSION >= 4 to use sequence_handler.


As you bump the libdrm version:
  - drop the existing DRM_EVENT_CONTEXT_VERSION guard
  - swap the DRM_EVENT_CONTEXT_VERSION macro with the actual version implemented

Makes sense, will be done.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107170
https://bugs.freedesktop.org/show_bug.cgi?id=106972
https://bugs.freedesktop.org/show_bug.cgi?id=107176


Separate bugs it seems - hence separate patches?


Yes

+LIBDRM_CRT_SEQUENCE_REQUIRED=2.4.89
+

There is no need for yet another version - just bump LIBDRM_REQUIRED.

Bumping LIBDRM_REQUIRED would mean that older platforms won't be supported.
I don't know how the decisions about support of older platforms are made but
from my point of view bumping required libdrm version due to one vulkan
extension
may be overkill.


If we consider this as the only merit, then the number of
checks/version would practically explore.
Simply take each user libGL, libEGL, gbm, other multiply that with the
number of features we use.

Looking at Eero's bug (last one in the list) - he's using Ubuntu 16.04
which has 2.4.91 in xenial-updates



I didn't notice that libdrm is easy to update thus my argument fails.
Managing dependencies is hard...

Why do we need the new define? From a quick look we should be above to
reuse VK_USE_PLATFORM_DISPLAY_KHR, we simply need the ifdef guards.

If we will not bump global libdrm version requirement new define is
necessary because
rest of the code guarded by VK_USE_PLATFORM_DISPLAY_KHR works fine with
older libdrm versions.


And by addressing that, this can go - one diverging codepath less ;-)

For good.

HTH
Emil


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Re: [Mesa-dev] [PATCH v3] vulkan: Fix compilation on older platforms

[Danylo Piliaiev]

Hi Eric,


On 24.07.18 18:43, Eric Engestrom wrote:

On Friday, 2018-07-13 16:57:34 +0300, Danylo Piliaiev wrote:

Make xlease automatically enabled only if xcb-randr >= 1.13,
check its version if manually enabled.

Enable VK_EXT_display_control only when libdrm >= 2.4.89

Check for DRM_EVENT_CONTEXT_VERSION >= 4 to use sequence_handler.

You're changing 3 unrelated things here; please send 3 patches :)


Ok, I'll separate patches this time:
1) xcb-randr check
2) Bumping libdrm for vulkan
3) Removal checks of DRM_EVENT_CONTEXT_VERSION as suggested by Emil.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107170
   https://bugs.freedesktop.org/show_bug.cgi?id=106972
   https://bugs.freedesktop.org/show_bug.cgi?id=107176

v2: - Add 'protect="VK_USE_DISPLAY_CONTROL"' attribute to
VK_EXT_display_control in vk.xml
 - Add support for 'protect' attribute to anv_entrypoints_gen
(copied from radv_entrypoints_gen)
 - Turn #if into #ifdef
 - Remove unnecessary pkg-config call from meson build (Dylan Baker)

v3: by Dylan Baker
 - Remove previously added changes to vk.xml and entrypoints
generation because vk.xml is meant to be pulled from the external
source.

Signed-off-by: Danylo Piliaiev 
---
  configure.ac   | 29 +-
  meson.build| 10 -
  src/amd/vulkan/radv_extensions.py  |  9 +++-
  src/amd/vulkan/radv_wsi_display.c  |  5 ++---
  src/intel/vulkan/anv_extensions.py |  2 +-
  src/intel/vulkan/anv_extensions_gen.py |  7 +++
  src/intel/vulkan/anv_wsi_display.c |  4 ++--
  src/vulkan/wsi/wsi_common_display.c|  8 +--
  src/vulkan/wsi/wsi_common_display.h|  3 ++-
  9 files changed, 51 insertions(+), 26 deletions(-)

diff --git a/configure.ac b/configure.ac
index f135d05736..0b04525014 100644
--- a/configure.ac
+++ b/configure.ac
@@ -82,6 +82,8 @@ LIBDRM_FREEDRENO_REQUIRED=2.4.92
  LIBDRM_ETNAVIV_REQUIRED=2.4.89
  LIBDRM_VC4_REQUIRED=2.4.89
  
+LIBDRM_CRT_SEQUENCE_REQUIRED=2.4.89

I agree with everyone else here: just bump the libdrm version required
for vulkan :)

Making sure I got it right:
Since it's vulkan only issue LIBDRM_REQUIRED=2.4.75 should be left 
intact and

new variable like LIBDRM_VULKAN_REQUIRED=2.4.89 be introduced
which will be checked when vulkan is enabled.

libdrm is absolutely trivial to update; any system that can update its
mesa can also update its libdrm.


Didn't notice that it's easy to update, thanks.

+
  dnl Versions for external dependencies
  DRI2PROTO_REQUIRED=2.8
  GLPROTO_REQUIRED=1.4.14
@@ -97,6 +99,7 @@ XCBDRI2_REQUIRED=1.8
  XCBDRI3_MODIFIERS_REQUIRED=1.13
  XCBGLX_REQUIRED=1.8.1
  XCBPRESENT_MODIFIERS_REQUIRED=1.13
+XCBRANDR_XLEASE_REQUIRED=1.13
  XDAMAGE_REQUIRED=1.1
  XSHMFENCE_REQUIRED=1.1
  XVMC_REQUIRED=1.0.6
@@ -1874,20 +1877,6 @@ if test x"$enable_dri3" = xyes; then
  fi
  fi
  
-

-if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 'drm'; then
-have_xlease=yes
-else
-have_xlease=no
-fi
-
-if test x"$have_xlease" = xyes; then
-randr_modules="x11-xcb xcb-randr"
-PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
-xlib_randr_modules="xrandr"
-PKG_CHECK_MODULES([XLIB_RANDR], [$xlib_randr_modules])
-fi
-
  AM_CONDITIONAL(HAVE_PLATFORM_X11, echo "$platforms" | grep -q 'x11')
  AM_CONDITIONAL(HAVE_PLATFORM_WAYLAND, echo "$platforms" | grep -q 'wayland')
  AM_CONDITIONAL(HAVE_PLATFORM_DRM, echo "$platforms" | grep -q 'drm')
@@ -1905,14 +1894,24 @@ xno)
  ;;
  *)
  if echo "$platforms" | grep -q 'x11' && echo "$platforms" | grep -q 
'drm'; then
-enable_xlib_lease=yes
+xlease_modules="x11-xcb xcb-randr >= $XCBRANDR_XLEASE_REQUIRED xrandr"
+PKG_CHECK_EXISTS([$xlease_modules], [enable_xlib_lease=yes], 
[enable_xlib_lease=no])
  else
  enable_xlib_lease=no
  fi
  esac
  
+if test x"$enable_xlib_lease" = xyes; then

+randr_modules="x11-xcb xcb-randr >= $XCBRANDR_XLEASE_REQUIRED"
+PKG_CHECK_MODULES([XCB_RANDR], [$randr_modules])
+xlib_randr_modules="xrandr"
+PKG_CHECK_MODULES([XLIB_RANDR], [$xlib_randr_modules])
+fi
+
  AM_CONDITIONAL(HAVE_XLIB_LEASE, test "x$enable_xlib_lease" = xyes)
  
+PKG_CHECK_EXISTS([libdrm >= $LIBDRM_CRT_SEQUENCE_REQUIRED], [DEFINES="${DEFINES} -DVK_USE_DISPLAY_CONTROL"], [])

+
  dnl
  dnl More DRI setup
  dnl
diff --git a/meson.build b/meson.build
index 7d12af3d51..902074819c 100644
--- a/meson.build
+++ b/meson.build
@@ -1088,6 +1088,8 @@ _drm_freedreno_ver = '2.4.92'
  _drm_intel_ver = '2.4.75'
  _drm_ver = '2.4.75'
  
+_drm_crt_sequence_ver = '2.4.89'

+
  _libdrm_checks = [
['intel', with_dri_i915 or with_gallium_i915],
['amdgpu', with_amd_vk or with_gallium_radeonsi],
@@ -1361,11 +1363,17 @@ if with_platform_x11
  dep_xcb_xfixes = dependency('xcb-xfixes')
endif
if with_xlib_lease
-dep_xcb_xrandr = dependency('xcb-randr', version : '>= 

Re: [Mesa-dev] [PATCH] intel: tools: dump: only store device id on success

[Tapani Pälli]

Reviewed-by: Tapani Pälli 

On 07/24/2018 11:11 PM, Lionel Landwerlin wrote:

We might fail on master node drm fd because we won't have the right
permissions.

Signed-off-by: Lionel Landwerlin 
---
  src/intel/tools/intel_dump_gpu.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/tools/intel_dump_gpu.c b/src/intel/tools/intel_dump_gpu.c
index 1abe54147cf..a71103f1889 100644
--- a/src/intel/tools/intel_dump_gpu.c
+++ b/src/intel/tools/intel_dump_gpu.c
@@ -111,7 +111,7 @@ align_u32(uint32_t v, uint32_t a)
  }
  
  static struct gen_device_info devinfo = {0};

-static uint32_t device;
+static uint32_t device = 0;
  static struct aub_file aub_file;
  
  static void *

@@ -419,7 +419,7 @@ ioctl(int fd, unsigned long request, ...)
* (they typically do), we'll piggy-back on
* their ioctl and store the id for later
* use. */
- if (getparam->param == I915_PARAM_CHIPSET_ID)
+ if (ret == 0 && getparam->param == I915_PARAM_CHIPSET_ID)
  device = *getparam->value;
  
   return ret;



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Re: [Mesa-dev] [PATCH v2] intel/ppgtt: memory address alignment

[Chris Wilson]

Quoting Sergii Romantsov (2018-07-25 08:42:55)
> Hello,
> here is a backtrace:
...

Please try:
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 09d45e30ecc..8274c2e0b2f 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
   uint32_t stride)
 {
struct brw_bo *bo;
-   unsigned int page_size = getpagesize();
int ret;
struct bo_cache_bucket *bucket;
bool alloc_from_cache;
@@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
 * allocation up.
 */
if (bucket == NULL) {
-  bo_size = size;
-  if (bo_size < page_size)
- bo_size = page_size;
+  unsigned int page_size = getpagesize();
+  bo_size = ALIGN(size, page_size);
} else {
   bo_size = bucket->size;
}
+   assert(bo_size);

mtx_lock(>lock);
/* Get a buffer out of the cache if available */
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