Re: [Mesa-dev] [PATCH 1/4] meson: Enable SSE4.1 optimizations

On Thu, Nov 16, 2017 at 2:19 PM, Dylan Baker <dy...@pnwbakers.com> wrote: > Quoting Matt Turner (2017-11-15 21:57:37) >> On Wed, Nov 15, 2017 at 5:10 PM, Dylan Baker <dy...@pnwbakers.com> wrote: >> > This patch checks for an and then enables sse4.1 optimiza

Re: [Mesa-dev] [PATCH 1/4] meson: Enable SSE4.1 optimizations

On Wed, Nov 15, 2017 at 5:10 PM, Dylan Baker wrote: > This patch checks for an and then enables sse4.1 optimizations if the > host machine will be x86/x86_64. There's some stack realignment stuff that probably needs to stay, but depending on what gcc version we require we

Re: [Mesa-dev] [ANNOUNCE] mesa 17.3.0-rc4

On Tue, Nov 14, 2017 at 6:37 AM, Emil Velikov wrote: > The fourth release candidate for Mesa 17.3.0 is now available. > > As per the issue tracker [1] we still have a number of outstanding bugs > blocking the release. > > [1]

Re: [Mesa-dev] [PATCH] i965: disable BLORP color clears for gen 4-5

On Thu, Nov 9, 2017 at 9:23 AM, Jason Ekstrand wrote: > This is a really rubbish solution. Yes, it fixes a crash in MPV but unless > we disable all blorp on gen4-5 (which I don't think is possible anymore), we > haven't actually fixed it for real. Are you planning to look

Re: [Mesa-dev] [PATCH] i965/fs: Fix extract_i8/u8 to a 64-bit destination

On Mon, Nov 13, 2017 at 11:20 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On November 13, 2017 22:54:02 Matt Turner <matts...@gmail.com> wrote: > >> On Mon, Nov 13, 2017 at 10:06 PM, Jason Ekstrand <ja...@jlekstrand.net> >> wrote: >>> >>&g

Re: [Mesa-dev] [PATCH] i965/fs: Fix extract_i8/u8 to a 64-bit destination

On Mon, Nov 13, 2017 at 10:06 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Mon, Nov 13, 2017 at 3:23 PM, Matt Turner <matts...@gmail.com> wrote: >> >> The MOV instruction can extract bytes to words/double words, and >> words/double words to qua

Re: [Mesa-dev] [PATCH v3 13/48] intel/fs: Use the original destination region for int MUL lowering

On Wed, Oct 25, 2017 at 4:25 PM, Jason Ekstrand wrote: > Some hardware (CHV, BXT) have special restrictions on register regions > when doing integer multiplication. We want to respect those when we > lower to DxW multiplication. This is not a good commit message. I am very

[Mesa-dev] [PATCH] i965/fs: Fix extract_i8/u8 to a 64-bit destination

The MOV instruction can extract bytes to words/double words, and words/double words to quadwords, but not byte to quadwords. For unsigned byte to quadword, we can read them as words and AND off the high byte and extract to quadword in one instruction. For signed bytes, we need to first sign

Re: [Mesa-dev] [PATCH 07/18] intel/compiler: fix for memmove argument on annotating error

On Mon, Nov 13, 2017 at 1:12 PM, Rogovin, Kevin wrote: > Hi, > > > I confess I am not 100% on this code and I did educated guessing what it is > trying to do; I figured it was trying to insert contents at the current index > i; and that ann_count is the size -after-

Re: [Mesa-dev] [PATCH 09/18] intel/tools/disasm: gen_disasm_disassemble to take const void* instead of void*

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 10/18] intel/tools/disasm: add gen_disasm_assembly_length function

Pending the questions about 07/18, I don't think this should be necessary. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 08/18] intel/compiler:add function to give option to print offsets into assembly

On Mon, Nov 13, 2017 at 5:17 AM, wrote: > From: Kevin Rogovin > > Signed-off-by: Kevin Rogovin > --- > src/intel/compiler/brw_eu.c | 11 ++- > src/intel/compiler/brw_eu.h | 3 +++ > 2 files changed, 13

Re: [Mesa-dev] [PATCH 11/18] intel/tools/disasm: make sure that entire range is disassembled

On Mon, Nov 13, 2017 at 5:17 AM, wrote: > From: Kevin Rogovin > > Without this patch, if a shader has errors, the disassembly of the > shader often stops after the first opcode that has errors. I can't see anything wrong with the current code.

Re: [Mesa-dev] [PATCH 07/18] intel/compiler: fix for memmove argument on annotating error

On Mon, Nov 13, 2017 at 5:17 AM, wrote: > From: Kevin Rogovin > > Without this fix, disassembling of GEN shaders with GPU commands > that the disassembler does not know would result in errors being > added to the annotator which would crash when

Re: [Mesa-dev] [PATCH 3/4] util/disk_cache: Make zlib support optional

On Fri, Nov 10, 2017 at 4:44 PM, Timothy Arceri <tarc...@itsqueeze.com> wrote: > On 11/11/17 08:49, Jordan Justen wrote: >> >> On 2017-11-10 13:15:10, Matt Turner wrote: >>> >>> Why? >> >> >> For patch 4. Patch 4 can't happen unless zlib is

Re: [Mesa-dev] [PATCH 05/10] nir: Use well-known power-of-two test instead of util_bitscan

On Fri, Nov 10, 2017 at 4:02 PM, Ian Romanick <i...@freedesktop.org> wrote: > On 11/10/2017 04:54 PM, Matt Turner wrote: >> On Fri, Nov 10, 2017 at 2:32 PM, Ian Romanick <i...@freedesktop.org> wrote: >>> From: Ian Romanick <ian.d.roman...@intel.com> >&g

Re: [Mesa-dev] [PATCH 05/10] nir: Use well-known power-of-two test instead of util_bitscan

On Fri, Nov 10, 2017 at 2:32 PM, Ian Romanick wrote: > From: Ian Romanick > > This prevents the next change from breaking the build, and I felt that > it was different enough from the rest of that patch to stand on its own. > > Signed-off-by: Ian

Re: [Mesa-dev] [PATCH 3/4] util/disk_cache: Make zlib support optional

Why? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] autotools: Set C++ visibility flags on Intel

4 > --- a/src/intel/Makefile.am > +++ b/src/intel/Makefile.am > @@ -46,6 +46,9 @@ AM_CFLAGS = \ > $(VISIBILITY_CFLAGS) \ > $(WNO_OVERRIDE_INIT) > > +AM_CXXFLAGS = \ > + $(VISIBILITY_CXXFLAGS) > + Reviewed-by: Matt Turner <matts..

Re: [Mesa-dev] [PATCH] intel/fs: Use a pure vertical stride for large register strides

On Thu, Nov 2, 2017 at 3:54 PM, Jason Ekstrand wrote: > Register strides higher than 4 are uncommon but they can happen. For > instance, if you have a 64-bit extract_u8 operation, we turn that into > UB -> UQ MOV with a source stride of 8. Our previous calculation would >

[Mesa-dev] [PATCH] i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK

Fixes the following tests on CHV, BXT, and GLK: KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115 --- src/intel/compiler/brw_fs_nir.cpp | 8 1

Re: [Mesa-dev] Couple patches for debian-experimental mesa branch

Wrong list, I think. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH mesa 2/2] meson: only turn on Mesa's DEBUG for buildtype==debug

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH mesa 1/2] meson: switch default build type to debugoptimized

Acked-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] Meson's default build type

On Fri, Nov 3, 2017 at 6:28 PM, Christian Schmidbauer wrote: >> On Thu, Nov 2, 2017 at 11:45 AM, Andres Rodriguez wrote: >>> >>> >>> On 2017-11-02 01:52 PM, Eric Engestrom wrote: On Thursday, 2017-11-02 17:39:53 +, Eric Engestrom wrote:

Re: [Mesa-dev] Meson's default build type

On Thu, Nov 2, 2017 at 11:45 AM, Andres Rodriguez wrote: > > > On 2017-11-02 01:52 PM, Eric Engestrom wrote: >> >> On Thursday, 2017-11-02 17:39:53 +, Eric Engestrom wrote: >>> >>> On Thursday, 2017-11-02 09:46:05 -0700, Chad Versace wrote: On Wed 01 Nov 2017,

Re: [Mesa-dev] [PATCH v2 4/4] i965/gen10: Implement Wa3DStateMode

On Fri, Nov 3, 2017 at 11:08 AM, Nanley Chery <nanleych...@gmail.com> wrote: > On Fri, Nov 03, 2017 at 09:50:41AM -0700, Nanley Chery wrote: >> On Thu, Nov 02, 2017 at 06:13:43PM -0700, Matt Turner wrote: >> > On Thu, Nov 2, 2017 at 11:26 AM, Nanley Chery <nanleyc

Re: [Mesa-dev] [PATCH v2 4/4] i965/gen10: Implement Wa3DStateMode

On Thu, Nov 2, 2017 at 11:26 AM, Nanley Chery wrote: > On Wed, Nov 01, 2017 at 03:52:15PM -0700, Anuj Phogat wrote: >> V2: Remove the bits enabling Float blend optimization. It is >> enabled through CACHE_MODE_SS register. >> Update the comment. >> >> This

Re: [Mesa-dev] [PATCH 07/13] autotools: set XA versions in configure.ac and configure header file

With Emil's suggestions, Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] Meson's default build type

On Thu, Nov 2, 2017 at 9:51 AM, Michel Dänzer wrote: > FWIW, my vote is for debugoptimized: Assertions are enabled and there's > debugging information useful for bug reports, but performance should be > decent. If debugoptimized turns on DEBUG, then I don't think performance

Re: [Mesa-dev] [PATCH 1/2] configure.ac: append to existing MSVC compat flags

Oops! Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] radeonsi: remove 'Authors:' comments

On Tue, Oct 31, 2017 at 10:47 AM, Marek Olšák wrote: > From: Marek Olšák > > It's inaccurate. Instead, see the copyright and use "git log" and > "git blame" to know the authorship. Agreed. I've tried to discourage adding new ones. Maybe it's time to clean

Re: [Mesa-dev] [PATCH 3/3] i965/fs/nir: Don’t let nir lower nir_intrinsic_load_subgroup_all_mask

On Tue, Oct 31, 2017 at 10:55 AM, Neil Roberts wrote: > Instead of letting nir lower nir_intrinsic_load_subgroup_all_mask this > is now generated directly. This is more efficient because it can be > calculated in the compiler based on the dispatch width. > > Sadly it’s still

[Mesa-dev] [PATCH] nir: Don't print swizzles when there are more than 4 components

... as can happen with various types like mat4, or else we'll smash the stack writing past the end of components_local[]. Fixes: 5a0d3e1129b7 ("nir: Print the components referenced for split or packed shader in/outs.") --- Reproduce with INTEL_DEBUG=vs and

Re: [Mesa-dev] [PATCH 1/2] i965/gen10: Don't set Smooth Point Enable in 3DSTATE_SF if num_samples > 1

On Fri, Oct 27, 2017 at 10:50 AM, Anuj Phogat wrote: > Signed-off-by: Anuj Phogat > --- > src/mesa/drivers/dri/i965/genX_state_upload.c | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git

Re: [Mesa-dev] [PATCH] i965: Delete unused brw_vs_prog_data::nr_attributes field.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/2] i965: fix unused var warnings in release build

I would suggest just marking the devinfo variables as UNUSED. I really wish we didn't have to deal with this triviality :( ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] intel: fix memmem() warning first arg shouldn't be NULL

On Sun, Oct 22, 2017 at 6:26 PM, Timothy Arceri wrote: > --- > src/intel/compiler/brw_eu_validate.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/src/intel/compiler/brw_eu_validate.c > b/src/intel/compiler/brw_eu_validate.c > index 9f72c650ddb..07318b9d3c0

Re: [Mesa-dev] [PATCH mesa] intel/eu/validate: avoid null deref

On Mon, Oct 23, 2017 at 10:08 AM, Eric Engestrom wrote: > src/intel/compiler/brw_eu_validate.c:50:11: warning: argument 1 null where > non-null expected [-Wnonnull] > return memmem(haystack.str, haystack.len, needle.str, needle.len) != NULL; >

Re: [Mesa-dev] [PATCH] i965: Fix memmem compiler warnings.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 31/32] i965: Initialize disk shader cache if MESA_GLSL_CACHE_DISABLE is false

On Wed, Oct 18, 2017 at 10:32 PM, Jordan Justen wrote: > Double negative FTW! > > For now, the shader cache is disabled by default on i965 to allow us > to verify its stability. > > In other words, to enable the shader cache on i965, set > MESA_GLSL_CACHE_DISABLE to

Re: [Mesa-dev] [PATCH] i965: Add align1 ternary instruction-word support

On Fri, Oct 20, 2017 at 1:32 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: > >> Reviewed-by: Scott D Phillips <scott.d.phill...@intel.com> >> --- >> src/intel/compiler/brw_inst.h | 108 >> +

Re: [Mesa-dev] [PATCH] i965: Add align1 ternary instruction emission support

On Fri, Oct 20, 2017 at 1:42 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: > >> --- >> src/intel/compiler/brw_eu_emit.c | 219 >> +-- >> 1 file changed, 166 inser

[Mesa-dev] [PATCH] i965/fs: Use align1 mode on ternary instructions on Gen10+

Align1 mode offers some nice features over align16, like access to more data types and the ability to use a 16-bit immediate. This patch does not start using any new features. It just emits ternary instructions in align1 mode. --- src/intel/compiler/brw_fs_generator.cpp | 12 1 file

Re: [Mesa-dev] [PATCH 10/13] i965: Add align1 ternary instruction disassembler support

On Fri, Sep 29, 2017 at 5:11 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: > >> --- >> src/intel/compiler/brw_disasm.c | 399 >> +--- >> src/intel/compiler/brw_eu_

[Mesa-dev] [PATCH] i965: Add align1 ternary instruction emission support

--- src/intel/compiler/brw_eu_emit.c | 219 +-- 1 file changed, 166 insertions(+), 53 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 7495a19fd8..4f98860044 100644 --- a/src/intel/compiler/brw_eu_emit.c +++

[Mesa-dev] [PATCH] i965: Add align1 ternary instruction-word support

Reviewed-by: Scott D Phillips --- src/intel/compiler/brw_inst.h | 108 ++ 1 file changed, 108 insertions(+) diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 1ddee77164..40723f9012 100644 ---

Re: [Mesa-dev] [PATCH 09/13] i965: Add align1 ternary instruction-word support

On Fri, Sep 29, 2017 at 5:08 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: > >> --- >> src/intel/compiler/brw_inst.h | 114 >> ++ >> 1 file changed, 114

[Mesa-dev] [PATCH] i965: Add align1 ternary instruction support to conversion functions

--- src/intel/compiler/brw_disasm.c | 16 ++- src/intel/compiler/brw_inst.h | 4 +- src/intel/compiler/brw_reg_type.c | 99 --- src/intel/compiler/brw_reg_type.h | 16 +-- 4 files changed, 101 insertions(+), 34 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 12/13] i965/fs: Use align1 mode on ternary instructions on Gen10+

On Fri, Sep 29, 2017 at 5:20 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: > >> Align1 mode offers some nice features over align16, like access to more >> data types and the ability to use a 16-bit immediate. This

Re: [Mesa-dev] [PATCH 08/13] i965: Add align1 ternary instruction support to conversion functions

On Fri, Sep 29, 2017 at 5:07 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: > >> --- >> src/intel/compiler/brw_disasm.c | 12 --- >> src/intel/compiler/brw_inst.h | 4 +-- >&g

Re: [Mesa-dev] [PATCH 04/21] intel: Rewrite the world of push/pull params

On Fri, Sep 29, 2017 at 2:25 PM, Jason Ekstrand wrote: > diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c > b/src/mesa/drivers/dri/i965/gen6_constant_state.c > index b2e357f..93a12c7 100644 > --- a/src/mesa/drivers/dri/i965/gen6_constant_state.c > +++

Re: [Mesa-dev] [PATCH 2/2] i965: Use is_scheduling_barrier instead of schedule_node::is_barier.

uctions, > but not future ones. So we'll never see it, and walk further than we > need to. Dang. I should have realized that in my original patch. With the typo Dylan pointed out fixed, both are: Reviewed-by: Matt Turner <matts...@gmail.com>

Re: [Mesa-dev] [PATCH v2 07/52] intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all

On Tue, Oct 17, 2017 at 2:53 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Tue, Oct 17, 2017 at 2:18 PM, Matt Turner <matts...@gmail.com> wrote: >> >> On 10/12, Jason Ekstrand wrote: >>> >>> For some reason, the any/all predicates don't

Re: [Mesa-dev] [PATCH v2 07/52] intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all

. Assuming that still fixes the bug you see, that would be Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/m

Re: [Mesa-dev] [PATCH v2 06/52] intel/fs: Use an explicit D type for vote any/all/eq intrinsics

On 10/12, Jason Ekstrand wrote: They return a boolean so this is the right type. Unfortunately, get_nir_dest has the annoying behavior of giving us a float type by default. This is mostly to work around the fact that gen7 has 64-bit float but no Q types. I'd really like to see a clearer

Re: [Mesa-dev] [PATCH v2 05/52] intel/fs: Don't stomp f0.1 in SIMD16 ballot

On 10/12, Jason Ekstrand wrote: In fragment shaders f0.1 is used for discards so doing ballot after a discard can potentially cause the discard to not happen. Since - SIMD32 currently only used in compute shaders - discard only available in fragment shaders this will fix

Re: [Mesa-dev] [PATCH v2 04/52] intel/fs: Use ANY/ALL32 predicates in SIMD32

, that hardware looks at the execution group and knows to shift it's flag usage up correctly so a 2H instruction will write to f0.1 instead of f0.0. Cc: mesa-sta...@lists.freedesktop.org Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital sig

Re: [Mesa-dev] [PATCH v2 03/52] intel/fs: Handle flag read/write aliasing in needs_src_copy

interference, will force us to emit a copy of the source. Cc: mesa-sta...@lists.freedesktop.org Reviewed-by: Matt Turner <matts...@gmail.com> signature.asc Description: Digital signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH] i965: Fix src0 vs src1 typo

On Tue, Oct 10, 2017 at 4:43 AM, Eero Tamminen <eero.t.tammi...@intel.com> wrote: > Hi, > > On 03.10.2017 08:20, Matt Turner wrote: >> >> A typo caused us to copy src0's reg file to src1 rather than reading >> src1's as intended. This caused us to fail to compact

Re: [Mesa-dev] [PATCH] Replace byte-swapping code with builtins in pack.c

On Sun, Oct 8, 2017 at 12:15 PM, Jochen Rollwagen <joro-2...@t-online.de> wrote: > Am 06.10.2017 um 11:57 schrieb Nicolai Hähnle: >> >> On 05.10.2017 20:59, Jochen Rollwagen wrote: >>> >>> Am 04.10.2017 um 05:59 schrieb Matt Turner: >>>> >

Re: [Mesa-dev] [PATCH 2/4] intel/compiler: Don't propagate cmod into integer multiplies

saturation > + *(.sat) cannot be used in this case. Please indent the lines in the block quote one space more than the " Patches 1-2 are Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] Replace byte-swapping code with builtins in pack.c

On Tue, Oct 3, 2017 at 11:01 AM, Jochen Rollwagen wrote: > From 4cebe50a9bade6717923e104c954f3fad75f71bb Mon Sep 17 00:00:00 2001 > From: Jochen Rollwagen > Date: Tue, 3 Oct 2017 19:54:10 +0200 > Subject: [PATCH] Replace byte-swapping code with

Re: [Mesa-dev] [PATCH] intel: compiler: vec4: add missing default 0 lod

ything we implement using those > +* two opcodes provides one. Provide a default LOD of 0. > +*/ > + if ((instr->op == nir_texop_txs || > +instr->op == nir_texop_txl) && > + lod.file == BAD_FILE) { > + lod = brw_

[Mesa-dev] [PATCH] i965: Fix src0 vs src1 typo

A typo caused us to copy src0's reg file to src1 rather than reading src1's as intended. This caused us to fail to compact instructions like mov(8) g4<1>D0D { align1 1Q }; because src1 was set to immediate rather than architecture file. Fixing this reenables compaction

Re: [Mesa-dev] [PATCH] intel: Always set Cube Face Enables for all surfaces.

Looks good to me. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 03/13] i965: Print subreg in units of type-size on ternary instructions

On Fri, Sep 29, 2017 at 5:03 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: > >> The instruction word contains SubRegNum[4:2] so it's in units of dwords >> (hence the * 4 to get it in terms of bytes). Before this p

Re: [Mesa-dev] [PATCH 10/15] gallium: Remove util_format_s3tc_enabled

On Mon, Oct 2, 2017 at 6:17 AM, Emil Velikov <emil.l.veli...@gmail.com> wrote: > On 2 October 2017 at 07:59, Matt Turner <matts...@gmail.com> wrote: > >> +#include "../../../mesa/main/texcompress_s3tc_tmp.h" >> > This feels a bit dirty. If people are n

Re: [Mesa-dev] [PATCH 06/15] mesa: Call DXTn functions directly

On Mon, Oct 2, 2017 at 4:23 AM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > On 02.10.2017 08:59, Matt Turner wrote: >> >> --- >> src/mesa/main/texcompress_s3tc.c | 117 >> +-- >> 1 file changed, 25 insertions(+), 92 d

Re: [Mesa-dev] [PATCH 05/15] mesa: Remove fprintf referring to libdxtn

On Mon, Oct 2, 2017 at 4:20 AM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > On 02.10.2017 08:59, Matt Turner wrote: >> >> When this file is included by Gallium, the fprintf causes it to fail to >> compile. This is an unreachable error case, and we shouldn't be

[Mesa-dev] [PATCH 14/15] build: Remove HAVE_DLOPEN

--- Android.common.mk | 1 - configure.ac| 4 ++-- meson.build | 1 - src/mesa/SConscript | 4 4 files changed, 2 insertions(+), 8 deletions(-) diff --git a/Android.common.mk b/Android.common.mk index 4d5daf8e9d..483f6c5be2 100644 --- a/Android.common.mk +++

[Mesa-dev] [PATCH 10/15] gallium: Remove util_format_s3tc_enabled

--- src/gallium/auxiliary/util/u_format.c | 4 -- src/gallium/auxiliary/util/u_format_s3tc.c| 54 +-- src/gallium/auxiliary/util/u_format_s3tc.h| 2 - src/gallium/drivers/llvmpipe/lp_screen.c | 4 -- src/gallium/drivers/llvmpipe/lp_test_format.c |

[Mesa-dev] [PATCH 15/15] travis: Remove libtxc_dxtn from the build

--- .travis.yml | 14 -- 1 file changed, 14 deletions(-) diff --git a/.travis.yml b/.travis.yml index d9a8bf5a9d..088295e133 100644 --- a/.travis.yml +++ b/.travis.yml @@ -20,7 +20,6 @@ env: - XCBPROTO_VERSION=xcb-proto-1.11 - LIBXCB_VERSION=libxcb-1.11 -

[Mesa-dev] [PATCH 08/15] mesa: Drop Mesa_DXTn from gl_context

--- src/mesa/drivers/dri/i915/intel_extensions.c | 5 + src/mesa/drivers/dri/i965/intel_extensions.c | 4 +--- src/mesa/drivers/dri/nouveau/nv10_context.c | 6 ++ src/mesa/drivers/dri/nouveau/nv20_context.c | 6 ++ src/mesa/drivers/dri/r200/r200_context.c | 10 ++---

[Mesa-dev] [PATCH 09/15] mesa/st: Drop has_lib_dxtc argument from st_init_extensions()

--- src/mesa/state_tracker/st_context.c| 2 +- src/mesa/state_tracker/st_extensions.c | 8 +--- src/mesa/state_tracker/st_extensions.h | 3 +-- src/mesa/state_tracker/st_manager.c| 2 +- 4 files changed, 4 insertions(+), 11 deletions(-) diff --git

[Mesa-dev] [PATCH 11/15] gallium: Remove util_format_s3tc_init()

--- src/gallium/auxiliary/util/u_format_s3tc.c | 79 ++-- src/gallium/auxiliary/util/u_format_s3tc.h | 4 -- src/gallium/drivers/freedreno/freedreno_screen.c | 2 - src/gallium/drivers/i915/i915_screen.c | 2 - src/gallium/drivers/llvmpipe/lp_screen.c

[Mesa-dev] [PATCH 13/15] mesa: Delete now unused dlopen.h

--- src/mesa/Makefile.sources| 1 - src/mesa/main/dlopen.h | 97 src/mesa/main/texcompress_s3tc.c | 1 - 3 files changed, 99 deletions(-) delete mode 100644 src/mesa/main/dlopen.h diff --git a/src/mesa/Makefile.sources

[Mesa-dev] [PATCH 12/15] mesa: Remove force_s3tc_enable driconf variable

--- src/gallium/auxiliary/pipe-loader/driinfo_gallium.h | 1 - src/gallium/include/state_tracker/st_api.h | 1 - src/gallium/state_trackers/dri/dri_screen.c | 2 -- src/gallium/state_trackers/osmesa/osmesa.c | 1 - src/mesa/drivers/dri/i915/intel_screen.c| 1

[Mesa-dev] [PATCH 07/15] mesa: Drop function pointer checks in s3tc code

Now never null! --- src/mesa/main/texcompress_s3tc.c | 193 --- 1 file changed, 60 insertions(+), 133 deletions(-) diff --git a/src/mesa/main/texcompress_s3tc.c b/src/mesa/main/texcompress_s3tc.c index e74e4c402a..14067f0e99 100644 ---

[Mesa-dev] [PATCH 06/15] mesa: Call DXTn functions directly

--- src/mesa/main/texcompress_s3tc.c | 117 +-- 1 file changed, 25 insertions(+), 92 deletions(-) diff --git a/src/mesa/main/texcompress_s3tc.c b/src/mesa/main/texcompress_s3tc.c index e08ed23d3a..e74e4c402a 100644 --- a/src/mesa/main/texcompress_s3tc.c +++

[Mesa-dev] [PATCH 05/15] mesa: Remove fprintf referring to libdxtn

When this file is included by Gallium, the fprintf causes it to fail to compile. This is an unreachable error case, and we shouldn't be calling fprintf directly. --- src/mesa/main/texcompress_s3tc_tmp.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/main/texcompress_s3tc_tmp.h

[Mesa-dev] [PATCH 04/15] mesa: Remove prototypes and mark S3TC functions static

This file will be #included, so the functions should be static. --- src/mesa/main/texcompress_s3tc_tmp.h | 23 +-- 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/src/mesa/main/texcompress_s3tc_tmp.h b/src/mesa/main/texcompress_s3tc_tmp.h index

[Mesa-dev] [PATCH 02/15] mesa: Combine libtxc_dxtn sources into texcompress_s3tc_tmp.h

TODO: Squash with previous commit --- src/mesa/Makefile.sources | 3 - src/mesa/main/texcompress_s3tc.c | 1 + ...{txc_compress_dxtn.c => texcompress_s3tc_tmp.h} | 249 - src/mesa/main/txc_dxtn.h | 55

[Mesa-dev] [PATCH 00/15] Import libtxc_dxtn's S3TC code into Mesa!

The patent on S3TC has now expired! Rejoice! This series imports the code from Roland's libtxc_dxtn into Mesa and cleans up some mess dealing with the possibility of S3TC not being available. EXT_texture_compression_s3tc and ANGLE_texture_compression_dxt are now always enabled where supported.

[Mesa-dev] [PATCH 03/15] mesa: Remove commented-out DXTn fetch code

Has been disabled for 12 years. --- src/mesa/main/texcompress_s3tc_tmp.h | 80 1 file changed, 80 deletions(-) diff --git a/src/mesa/main/texcompress_s3tc_tmp.h b/src/mesa/main/texcompress_s3tc_tmp.h index b67b7a299e..57bbf7e0ae 100644 ---

[Mesa-dev] [PATCH 01/15] mesa: Import libtxc_dxtn sources

Straight import of the libtxc_dxtn sources. Will be squashed with next commit that reorganizes them into a more familiar form --- src/mesa/Makefile.sources | 3 + src/mesa/main/txc_compress_dxtn.c | 843 ++ src/mesa/main/txc_dxtn.h | 55 +++

Re: [Mesa-dev] [PATCH] intel: Always set Cube Face Enables for all surfaces.

On Fri, Sep 29, 2017 at 10:54 PM, Kenneth Graunke wrote: > These shouldn't matter for non-cubes, and we always enable them all > for cubes, so we may as well set them all the time. We can just mark > the fields "mbo" (must be one) and genxml will automatically set them >

Re: [Mesa-dev] [PATCH 02/12] i965/fs: Rewrite fsign64 to skip the float -> double conversion

On Fri, Sep 29, 2017 at 4:48 AM, Iago Toral <ito...@igalia.com> wrote: > On Thu, 2017-09-28 at 23:05 -0700, Matt Turner wrote: >> ... without the float -> double conversion. Low power parts have >> additional restrictions when it comes to operating on 64-bit types, >&g

[Mesa-dev] [PATCH 08/12] i965: Remove validate_reg()

Replaced by the assembly validator, and in fact gets in the way of writing tests for the assembly validator. --- src/intel/compiler/brw_eu_emit.c | 80 1 file changed, 80 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c

[Mesa-dev] [PATCH 09/12] i965: Avoid validation error when src1 is not present

There can be no violation of the restriction that source offsets are aligned if there is only one source offset. --- src/intel/compiler/brw_eu_validate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_validate.c

[Mesa-dev] [PATCH 11/12] i965: Fix and enable forgotten validation test

I seem to have forgotten I still had work to do. --- src/intel/compiler/test_eu_validate.cpp | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index

[Mesa-dev] [PATCH 12/12] i965: Validate "Special Requirements for Handling Double Precision Data Types"

I did not implement: CNL's restriction on 64-bit int + align16, because I don't think we'll ever use this combination regardless of hardware generation. The restriction on immediate DF -> F conversions, because there's no reason to ever generate that, and I don't even know how DF ->

[Mesa-dev] [PATCH 05/12] i965: Add GLK, CFL, CNL to test_eu_validate.c

--- src/intel/compiler/test_eu_validate.cpp | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index 46d2b83e34..3dd560074f 100644 --- a/src/intel/compiler/test_eu_validate.cpp +++

[Mesa-dev] [PATCH 04/12] i965: Add Atom graphics names to parse_devid_override()

--- src/mesa/drivers/dri/i965/intel_screen.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index bd1365f232..10253eb5a4 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++

[Mesa-dev] [PATCH 02/12] i965/fs: Rewrite fsign64 to skip the float -> double conversion

... without the float -> double conversion. Low power parts have additional restrictions when it comes to operating on 64-bit types, and the instruction used to do the conversion violates one of them: specifically, the restriction that "Source and Destination horizontal stride must be aligned to

[Mesa-dev] [PATCH 03/12] i965: Fix support for disassembling 64-bit integer immediates

The type suffixes were wrong, and the 16 was missing the 0 prefix. Fixes: 92f787ff86ab ("i965: Add support for disassembling 64-bit integer immediates") --- src/intel/compiler/brw_disasm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_disasm.c

[Mesa-dev] [PATCH 06/12] i965: Add parentheses around usage of macro arguments

Otherwise I cannot use this macro in test_eu_validate.cpp --- src/intel/common/gen_device_info.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/common/gen_device_info.h b/src/intel/common/gen_device_info.h index ede4915e28..59b345e949 100644 ---

[Mesa-dev] [PATCH 10/12] i965: Only insert error message if not already present

Some restrictions require something like strides to match between src and dest. For multi-source instructions, I'd rather encapsulate the logic for not inserting already present errors in ERROR_IF than open-coding it multiple places. --- src/intel/compiler/brw_eu_validate.c | 18

[Mesa-dev] [PATCH 01/12] i965/fs: Unpack count argument to 64-bit shift ops on Atom

64-bit operations on Atom parts have additional restrictions over their big-core counterparts (validated by later patches). Specifically, the restriction that "Source and Destination horizontal stride must be aligned to the same qword" is violated by most shift operations since NIR uses a 32-bit

[Mesa-dev] [PATCH 07/12] i965: Add and use STRIDE and WIDTH macros

You'll notice there were bugs in some of the code being replaced. --- src/intel/compiler/brw_eu_validate.c | 33 +++-- 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index

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