t; + pinctrl-0 = <_copper_eth_phy_reset>;
> + reset-gpios = <_gpio1 11 GPIO_ACTIVE_LOW>;
> + reset-assert-us = <1>;
> };
>
> switch0: switch0@4 {
> --
> 2.19.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
compatible = "regulator-fixed";
> - gpio = <_gpio2 15 GPIO_ACTIVE_HIGH>;
> + gpio = <_gpio2 15 GPIO_ACTIVE_LOW>;
> pinctrl-names = "default";
> pinctrl-0 = <_xhci_vbus_pins>;
>
rs/net/ethernet/marvell/Kconfig | 1 +
> drivers/net/ethernet/marvell/mvpp2.c | 931 +++---
> drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 17 +-
> include/linux/phy/phy.h | 1 +
> 7 files changed, 680 insertions(+), 355 deletions(-)
>
> --
> 2.17.0
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
Hi agin,
On mer., avril 25 2018, Gregory CLEMENT <gregory.clem...@bootlin.com> wrote:
> Hi Maxime,
>
> On mer., avril 25 2018, Maxime Chevallier <maxime.chevall...@bootlin.com>
> wrote:
>
>> The Marvell XSMI controller needs 3 clocks to operate corr
ases.
>
> Fixes: 4792ea04bcd0 ("net: mvpp2: Fix clock resource by adding an optional
> bus clock")
> Signed-off-by: Maxime Chevallier <maxime.chevall...@bootlin.com>
Acked-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
Thanks,
Gregory
> ---
> drivers
_mg_core_clk;
> }
>
> /* Get system's tclk rate */
> @@ -8851,6 +8862,10 @@ static int mvpp2_probe(struct platform_device *pdev)
> }
> err_axi_clk:
> clk_disable_unprepare(priv->axi_clk);
> +
> +err_mg_core_clk:
> + if (priv->hw_version == MVPP22)
> + clk_disable_unprepare(priv->mg_core_clk);
> err_mg_clk:
> if (priv->hw_version == MVPP22)
> clk_disable_unprepare(priv->mg_clk);
> @@ -8898,6 +8913,7 @@ static int mvpp2_remove(struct platform_device *pdev)
> return 0;
>
> clk_disable_unprepare(priv->axi_clk);
> + clk_disable_unprepare(priv->mg_core_clk);
> clk_disable_unprepare(priv->mg_clk);
> clk_disable_unprepare(priv->pp_clk);
> clk_disable_unprepare(priv->gop_clk);
> --
> 2.11.0
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
#size-cells = <0>;
> compatible = "marvell,xmdio";
> reg = <0x12a600 0x10>;
> + clocks = <_LABEL(clk) 1 5>,
> + <_LABEL(clk) 1 6>, <_LABEL(clk) 1
> 18>;
>
From: Yelena Krivosheev <yel...@marvell.com>
In mvneta_port_up() we enable relevant RX and TX port queues by write
queues bit map to an appropriate register.
q_map must be ZERO in the beginning of this process.
Signed-off-by: Yelena Krivosheev <yel...@marvell.com>
Signed-off-by: Gre
Hi Andrew,
On mar., févr. 27 2018, Andrew Lunn <and...@lunn.ch> wrote:
> On Tue, Feb 27, 2018 at 11:24:02AM +0100, Gregory CLEMENT wrote:
>> Hi Andrew,
>>
>> On jeu., févr. 22 2018, Andrew Lunn <and...@lunn.ch> wrote:
>>
>> > Not all boards
| 3 +
> 3 files changed, 138 insertions(+), 43 deletions(-)
>
> --
> 2.15.1
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
Hello,
here it is a small series of fixes found on the mvneta driver. They
had been already used in the vendor kernel and are now ported to
mainline.
Thanks,
Gregory
Yelena Krivosheev (3):
net: mvneta: clear interface link status on port disable
net: mvneta: use proper rxq_number in loop
rg>
Fixes: c5aff18204da ("net: mvneta: driver for Marvell Armada 370/XP network
unit")
Signed-off-by: Yelena Krivosheev <yel...@marvell.com>
Tested-by: Dmitri Epshtein <d...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/et
Fixes: dc35a10f68d3 ("net: mvneta: bm: add support for hardware buffer
management")
Signed-off-by: Yelena Krivosheev <yel...@marvell.com>
Tested-by: Dmitri Epshtein <d...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/e
("net: mvneta: Associate RX queues with each CPU")
Signed-off-by: Yelena Krivosheev <yel...@marvell.com>
Tested-by: Dmitri Epshtein <d...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
On Armada 7K/8K we need to explicitly enable the bus clock. The bus clock
is optional because not all the SoCs need them but at least for Armada
7K/8K it is actually mandatory.
The binding documentation is updating accordingly.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.
ed Linux and Kernel engineering
> http://free-electrons.com
>
> ___________
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
On Armada 7K/8K we need to explicitly enable the bus clock. The bus clock
is optional because not all the SoCs need them but at least for Armada
7K/8K it is actually mandatory.
The binding documentation is updating accordingly.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.
Hi Rob,
On jeu., juil. 20 2017, Rob Herring <r...@kernel.org> wrote:
> On Thu, Jul 20, 2017 at 10:06 AM, Gregory CLEMENT
> <gregory.clem...@free-electrons.com> wrote:
>> Hi Rob,
>>
>> On jeu., juil. 20 2017, Rob Herring <r...@kernel.org> wrote:
>
err = mvneta_bm_port_init(pdev, pp);
> if (err < 0) {
> dev_info(>dev, "use SW buffer management\n");
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,xmdio";
> + reg = <0x12a600 0x10>;
> + status = "disabled";
&
faces by
> default, or add explicit disables in the mcbin device tree.
>
> What's your thoughts on this?
I prefer that we disable it by default and only enable it on the boards
using it.
Thanks,
Gregory
>
> Thanks!
> Antoine
>
> --
> Antoine Ténart, Free Electro
t; + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,xmdio";
> + reg = <0x12a600 0x10>;
> + };
> +
>
+-
> arch/arm/boot/dts/armada-xp-db-xc3-24g4xg.dts | 2 +-
> arch/arm/mach-mvebu/mvebu-soc-id.c | 43 -
> 10 files changed, 242 insertions(+), 67 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/arm/marvell/mv98dx3236-soc-id.txt
>
> --
> 2.11.0.24.ge6920cf
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
rom rx_desc again
> net: mvneta: avoid reading from tx_desc as much as possible
> net: mvneta: Use cacheable memory to store the rx buffer DMA address
>
> drivers/net/ethernet/marvell/mvneta.c | 80
> +++
> 1 file changed, 43 insertions(+), 37 deletions(-)
>
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
ure I still remember how mvneta works in
> the details.
>
> Best regards,
>
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
om uncached memory is
> fairly slow. So reuse the read out rx_status to avoid the second
> reading from uncached memory.
>
> Signed-off-by: Jisheng Zhang <jszh...@marvell.com>
> Suggested-by: Arnd Bergmann <a...@arndb.de>
This one is OK and I didn't see a regression:
Tes
@@ static int mvneta_init(struct device *dev, struct
> mvneta_port *pp)
> rxq->buf_virt_addr = devm_kmalloc(pp->dev->dev.parent,
> rxq->size * sizeof(void *),
> GFP_K
>
> drivers/net/ethernet/marvell/mvneta.c | 36
> ---
> 1 file changed, 21 insertions(+), 15 deletions(-)
>
> --
> 2.11.0
>
>
> ___________
> linux-arm-kernel mailing list
> linux-arm-ker...@lists
ove support for temperature sensor
v5 -> v6:
- rebased on net-next/master (d140199af510)
- Fix the redundant check on mv88e6xxx_6341_family (reported by Julia
Lawall)
- Add support for the 88E6141
- Move support for temperature sensor in the phy part
Gregory CLEMENT (2):
net: dsa: mv88e6xx
for this switch by describing its
capabilities to the driver and introducing a new family.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 54 ++--
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 19 +-
2
The Marvell 88E6341 device is single-chip, 6-port Ethernet switch with
four integrated 10/100/1000Mbps Ethernet transceivers and one high speed
SerDes interfaces.
It belongs to the Topaz family and unlike the 88E6341 it does not have
a TCAM.
Signed-off-by: Gregory CLEMENT <gregory.clem...@f
;and...@lunn.ch>
Reviewed-by: Vivien Didelot <vivien.dide...@savoirfairelinux.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/
r FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Contains definitions specific to the 98dx4521 SoC that are not
> + * common to all Armada XP SoCs.
> + */
> +
> +#include "armada-xp-98dx3236.dtsi"
> +
> +/ {
> + model = "Marvell 98DX4251 SoC";
> + compatible = "marvell,armadaxp-98dx4521", "marvell,armadaxp-98dx3236",
> "marvell,armadaxp", "marvell,armada-370-xp";
> +
> + cpus {
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "marvell,sheeva-v7";
> + reg = <1>;
> + clocks = < 1>;
> + clock-latency = <100>;
> + };
> + };
> +
> + soc {
> + internal-regs {
> + resume@20980 {
> + compatible = "marvell,98dx3336-resume-ctrl";
> + reg = <0x20980 0x10>;
> + };
> + };
> + };
> +};
> +
> + {
> + status = "okay";
> +};
> +
> + {
> + compatible = "marvell,98dx4251-pinctrl";
> +
> + sdio_pins: sdio-pins {
> + marvell,pins = "mpp5", "mpp6", "mpp7",
> +"mpp8", "mpp9", "mpp10";
> + marvell,function = "sd0";
> + };
> +};
> +
> + {
> + compatible = "marvell,prestera-98dx4251";
> +};
> --
> 2.11.0.24.ge6920cf
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
this by trapping reads to the ID, and if it is
>> zero, return the MV88E6390 family ID.
>
> Because of the ID masking issue, I am expecting a respin of this.
Do you think you will send a new version soon?
It is the last missing part to send my v7 for the Topaz support on the
EspressoBin.
riction, including without limitation the rights to use
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
}
> + }
> +
> + return 0;
> }
>
> int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
w phy_id for the 6341 family with the hwmon support.
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
t.
Gregory
> + if (chip->info->family == MV88E6XXX_FAMILY_6390)
> + *val |= PORT_SWITCH_ID_PROD_NUM_6390;
> + }
> + }
> +
> + return 0;
> }
>
> int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
>
I confirm that 88E6341 has Global 2, register 0x18, bit 13 referred as
"External access"
Gregory
>
> Thanks
> Andrew
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
et. There is currently
> a bug in the mv88e6390 support code. I also set it to 15s. But in fact
> it is 3.75 seconds. The 6341 might also use 3.75 seconds.
When I read your series I also thought about it and indeed it is 3.75
seconds. I will fix it.
Thanks,
Gregory
>
>Thanks
>
d.
Gregory
>
> Other than that, I have no objection on the patch itself if that is
> indeed expected from them...
>
> Thanks,
>
> Vivien
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Andrew,
On mar., janv. 24 2017, Andrew Lunn <and...@lunn.ch> wrote:
> On Tue, Jan 24, 2017 at 09:10:26PM +0100, Gregory CLEMENT wrote:
>> The PHY with the ID 0x1410C00
>
> :-(
>
> I don't have a better reference, but
> Linux/Documentation/devicetree/bind
Hi,
On mar., janv. 24 2017, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> From: Romain Perier <romain.per...@free-electrons.com>
>
> Some Marvell ethernet switches have internal ethernet transceivers with
> hardcoded phy addresses. These addre
The Marvell 88E6341 device is single-chip, 6-port Ethernet switch with
four integrated 10/100/1000Mbps Ethernet transceivers and one high speed
SerDes interfaces.
It belongs to the Topaz family and unlike the 88E6341 it does not have
a TCAM.
Signed-off-by: Gregory CLEMENT <gregory.clem...@f
The PHY with the ID 0x1410C00 can be found embedded in the Marvell Topaz
switches (88E6141/88E6341). It is compatible with the 88E1510 (at least for
the temperature information), so add support for it, using the 88E1510
specific functions.
Signed-off-by: Gregory CLEMENT <gregory.clem...@f
;and...@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index c7e08e13bb54..7d942f8a42a7 100644
--- a/d
,
Gregory
Changelog:
v5 -> v6:
- rebased on net-next/master (d140199af510)
- Fix the redundant check on mv88e6xxx_6341_family (reported by Julia
Lawall)
- Add support for the 88E6141
- Move support for temperature sensor in the phy part
Gregory CLEMENT (3):
net: dsa: mv88e6xxx: Add supp
for this switch by describing its
capabilities to the driver and introducing a new family.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 54 ++--
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 19 +-
2
Hi David,
On ven., janv. 20 2017, David Miller <da...@davemloft.net> wrote:
> From: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> Date: Thu, 19 Jan 2017 22:49:32 +0100
>
>> I created a new family for this switch and filled the ops structure
>>
Hi Vvien and Andrew,
On ven., janv. 20 2017, Andrew Lunn <and...@lunn.ch> wrote:
> On Thu, Jan 19, 2017 at 05:26:03PM -0500, Vivien Didelot wrote:
>> Gregory CLEMENT <gregory.clem...@free-electrons.com> writes:
>>
>> > +static bool mv88e6xxx_634
he same here. I've mostly been working on where the 6390 is
> different. Where it is the same i've mostly ignored it so far :-)
>
> There is also an ongoing effort to remove all these big if statements
> with a list of families.
Thanks for this answers I understand it a little bett
;and...@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 987b2dbbd35a..d1960ae0a618 100644
--- a/d
for this switch by describing its
capabilities to the driver and introducing a new family.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/dsa/mv88e6xxx/chip.c | 55 +--
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 21 ++
ame.
Thanks,
Gregory
Gregory CLEMENT (1):
net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341
Romain Perier (1):
net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >=
num_of_ports
drivers/net/dsa/mv88e6xxx/chip.c | 61 +--
drivers/n
by Gregory, I have removed the patch for the DT (already
> merged).
>
> 2.9.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
#size-cells = <0>;
> +
> + switch0phy0: switch0phy0@11 {
> + reg = <0x11>;
> + };
> + switch0phy1: switch0phy1@12 {
> + reg = <0x12>;
> +
> - if (phy >= mv88e6xxx_num_ports(chip))
> - return 0x;
> -
> mutex_lock(>reg_lock);
> err = mv88e6xxx_phy_write(chip, phy, reg, val);
> mutex_unlock(>reg_lock);
> --
> 2.9.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
bt_dev_err(hdev, "%s: configuration failed\n", __func__);
> + kfree_skb(skb);
> + return ret;
> + }
> +
> + return 0;
> +}
> +#endif
> +
> static int btusb_set_bdaddr_marvell(struct hci_dev *hdev,
> con
For HWBM all buffers are allocated in mvneta_bm_construct() and in runtime
they are put into descriptors by hardware. There is no need to fill them
at this point.
Suggested-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Teste
ihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by: Marcin Wojtas <m...@semihalf.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by: Marcin Wojtas <m...@semihalf.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1
tation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by
For small frame reuse the phys_addr variable instead of accessing the
uncacheable value in the rx descriptor.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Tested-by: Marcin Wojtas <m...@semihalf.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 fil
is introduced.
- Move the memory allocation of the buf_virt_addr of the rxq to be
called by the probe function in order to avoid a memory leak.
Thanks,
Gregory
Gregory CLEMENT (5):
net: mvneta: Optimize rx path for small frame
net: mvneta: Do not allocate buffer in rxq init with HWBM
net: mvneta: Use ca
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
(no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory
anks, I am going to send a new version with tour tested-by and the dts
fix for the second port.
Gregory
>
> Best regards,
> Marcin
>
> 2016-11-30 22:42 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
>> Hi,
>>
>> The Armada 37xx is a new ARM
ihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
For small frame reuse the phys_addr variable instead of accessing the
uncacheable value in the rx descriptor.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
For HWBM all buffers are allocated in mvneta_bm_construct() and in runtime
they are put into descriptors by hardware. There is no need to fill them
at this point.
Suggested-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
(no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory
_offset_correction is introduced.
- Move the memory allocation of the buf_virt_addr of the rxq to be
called by the probe function in order to avoid a memory leak.
Thanks,
Gregory
Gregory CLEMENT (5):
net: mvneta: Optimize rx path for small frame
net: mvneta: Do not allocate buffer in rxq init wit
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
tation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Docume
Hi David,
On mer., nov. 30 2016, David Miller <da...@davemloft.net> wrote:
> From: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> Date: Tue, 29 Nov 2016 15:55:21 +0100
>
>> +/* Virtual address of the RX buffer */
>> +void **buf_virt_addr
For HWBM all buffers are allocated in mvneta_bm_construct() and in runtime
they are put into descriptors by hardware. There is no need to fill them
at this point.
Suggested-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
For small frame reuse the phys_addr variable instead of accessing the
uncacheable value in the rx descriptor.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
(no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory
small frame"
- Fix the kbuild error by moving the "phys_addr += pp->rx_offset_correction;"
line from patch 2 to patch 3 where rx_offset_correction is introduced.
- Move the memory allocation of the buf_virt_addr of the rxq to be
called by the probe function in order to avoid a
tation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Docume
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
ihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> Gregory,
>
> 2016-11-29 11:19 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
>> Hi Marcin,
>>
>> On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.c
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> Hi Gregory,
>
> Another remark below, sorry for noise.
>
> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
>> Until now the virtual addres
Hi Marcin,
On mar., nov. 29 2016, Marcin Wojtas <m...@semihalf.com> wrote:
> Hi Gregory,
>
> Apparently HWBM had a mistake in implementation, please see below.
>
> 2016-11-29 10:37 GMT+01:00 Gregory CLEMENT
> <gregory.clem...@free-electrons.com>:
&g
Hi,
On mar., nov. 29 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> Hi,
>
> The Armada 37xx is a new ARMv8 SoC from Marvell using same network
> controller as the older Armada 370/38x/XP SoCs. This series adapts the
> driver in order to be able to u
(no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory
For small frame reuse the phys_addr variable instead of accessing the
uncacheable value in the rx descriptor.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/d
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
tation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Docume
ihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
by patch 4.
In patch 5 the dt support is added.
Beside Armada 37xx, the series have been tested on Armada XP and
Armada 38x (with Hardware Buffer Management and with Software Buffer
Managment).
Thanks,
Gregory
Gregory CLEMENT (4):
net: mvneta: Optimize rx path for small frame
net: mvneta
Hi Jisheng,
On lun., nov. 28 2016, Jisheng Zhang <jszh...@marvell.com> wrote:
> Hi Gregory,
>
> On Fri, 25 Nov 2016 16:30:14 +0100 Gregory CLEMENT wrote:
>
>> Until now the virtual address of the received buffer were stored in the
>> cookie field of the rx descrip
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++-
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
tation depend on the per cpu interrupts.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Docume
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
(no more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory
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