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which you can find at https://review.openocd.org/c/openocd/+/7422
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commit 9f13f3a85350ee22e42694f8b7d93c58c2d9827b
Author: Daniel Anselmi
Date: Thu Dec 29 20:02:39 2022 +0100
flas
Tommy Murphy - Thanks for sharing these details.
---
** [tickets:#379] Create custom jtag driver in openocd **
**Status:** new
**Milestone:** 0.10.0
**Labels:** openocd
**Created:** Thu Dec 29, 2022 02:25 PM UTC by Ashi Gupta
**Last Updated:** Thu Dec 29, 2022 06:13 PM UTC
**Owner:** nobody
Paul - on that ticket you have asked me to open a ticket on openocd devel
mailing list. I did not found that option while creating a ticket hence created
a new one without adding any owners. It will be great if you can share me how i
can create ticket in openocd-devel or i have to send a email o
FWIW, Some Microchip FPGAs/SoC FPGAs can support hard and/or soft IP Cortex-M
and RISC-V CPUs. But my recollection (from working for Microchip in the past)
is that neither supported SWD. Certainly there is no SWD debug access to the
RISC-V.
---
** [tickets:#378] SWD support for RISCV artchite
Apologies Paul - if I had been aware that it had been asked already, and
potentially involved closed source/GPL breaches, I would not have answered
here.
---
** [tickets:#379] Create custom jtag driver in openocd **
**Status:** new
**Milestone:** 0.10.0
**Labels:** openocd
**Created:** Thu
Agree with Tommy, SWD is ARM proprietary protocol part of ARM CoreSight,
Nevertheless, somewhere or sometimes we could have a SoC that integrates
together some ARM core with some RISC-V cores. In this hybrid SoC the debug
port can either be:
* a JTAG chain with two TAPs (one for ARM and the othe
Hi,
On Thu, Dec 29, 2022 at 02:25:23PM -, Ashi Gupta wrote:
> I am working on creating a custom JTAG driver for my custom interface. I am
...
You have already asked about it in
https://sourceforge.net/p/openocd/tickets/374/ . The answer is still
the same.
And if you plan to violate GPL then
In my en my eIxperience, there's not much/any documentation about this but it's
relatively straightforward to look at existing debug interface drivers and
follow those as a guide:
https://github.com/openocd-org/openocd/tree/master/src/jtag
The main task is to implement the public methods for yo
---
** [tickets:#379] Create custom jtag driver in openocd **
**Status:** new
**Milestone:** 0.10.0
**Labels:** openocd
**Created:** Thu Dec 29, 2022 02:25 PM UTC by Ashi Gupta
**Last Updated:** Thu Dec 29, 2022 02:25 PM UTC
**Owner:** nobody
Hello,
I am working on creating a custom JTAG d
That seems to be about using ESP32 as an SWD debug interface.
Not about debugging ESP32 using SWD.
And nothing there is obviously about the RISC-V based ESP32-C3.
As such, I don't see its relevance in this thread?
---
** [tickets:#378] SWD support for RISCV artchitecture**
**Status:** new
**Mil
i found this thread for SWD debug support using SPI for esp32 (have not tried
anything though)
https://esp32.com/viewtopic.php?t=3627
---
** [tickets:#378] SWD support for RISCV artchitecture**
**Status:** new
**Milestone:** 0.10.0
**Labels:** openocd
**Created:** Wed Dec 28, 2022 07:00 AM UT
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